Ðþí  xâ   8  nä   (            	þ  n¬                             <    bananapi,bpi-r4-pro-8x bananapi,bpi-r4-pro mediatek,mt7988a                                  +            7Bananapi BPI-R4 Pro 8X     cci       (    mediatek,mt7988-cci mediatek,mt8183-cci          =                       Dcci intermediate             P            d            p         opp-table-cci             operating-points-v2           x         p      opp-480000000            ƒ    œ8          Š øP      opp-660000000            ƒ    'VÍ          Š øP      opp-900000000            ƒ    5¤é          Š øP      opp-1080000000           ƒ    @_~          Š »          cpus                         +       cpu@0             arm,cortex-a73           ˜             œcpu          ¨psci             =                      Dcpu intermediate             P            ¶            d            p   :      cpu@1             arm,cortex-a73           ˜            œcpu          ¨psci             =                      Dcpu intermediate             P            ¶            d            p   ;      cpu@2             arm,cortex-a73           ˜            œcpu          ¨psci             =                      Dcpu intermediate             P            ¶            d            p   <      cpu@3             arm,cortex-a73           ˜            œcpu          ¨psci             =                      Dcpu intermediate             P            ¶            d            p   =      opp-table-0           operating-points-v2           x         p      opp-800000000            ƒ    /¯          Š øP      opp-1100000000           ƒ    A�«          Š øP      opp-1500000000           ƒ    Yh/          Š øP      opp-1800000000           ƒ    kIÒ          Š »             oscillator-40m            fixed-clock          ÃbZ          Ó             àclkxtal       pmu           arm,cortex-a73-pmu                       ó               psci              arm,psci-0.2             ¯smc       reserved-memory                      +             þ   secmon@43000000          ˜    C                            soc           simple-bus            þ                     +      interrupt-controller@c000000              arm,gic-v3        P   ˜                                @              A             B                               ó      	                    !            p         clock-controller@10001000              mediatek,mt7988-infracfg syscon          ˜                      Ó           2            p   	      clock-controller@1001b000              mediatek,mt7988-topckgen syscon          ˜    °                 Ó            p         watchdog@1001c000             mediatek,mt7988-wdt          ˜    À                 ó       n           2           ?okay             p   !      clock-controller@1001e000             mediatek,mt7988-apmixedsys           ˜    à                 Ó            p         pinctrl@1001f000              mediatek,mt7988-pinctrl       p   ˜    ð            Á             Ð             Ò             à             ð              °              7  Fgpio iocfg_tr iocfg_br iocfg_rb iocfg_lb iocfg_tl eint           P        `           l              T                  ó       á                       !            p      pcie0-pins           p      mux         xpcie          3  �pcie_2l_0_pereset pcie_clk_req_n0_0 pcie_wake_n0_0           pcie1-pins           p      mux         xpcie          1  �pcie_2l_1_pereset pcie_clk_req_n1 pcie_wake_n1_0             pcie2-pins           p      mux         xpcie          3  �pcie_1l_0_pereset pcie_clk_req_n2_0 pcie_wake_n2_0           pcie3-pins           p      mux         xpcie          1  �pcie_1l_1_pereset pcie_clk_req_n3 pcie_wake_n3_0             spi1-pins            p      mux         xspi         �spi1             uart0-pins           p   
   mux         xuart            �uart0            gbe0-led0-pins           p   )   mux         xled       
  �gbe0_led0            i2c0-g0-pins             p      mux         xi2c         �i2c0_1           i2c1-g0-pins             p      mux         xi2c         �i2c1_0           i2c2-g1-pins             p      mux         xi2c         �i2c2_1           mdio0-pins           p   /   mux         xeth       
  �mdc_mdio0         conf            ˆSMI_0_MDC SMI_0_MDIO            �            mmc0-emmc-51-pins            p   >   mux         xflash           �emmc_51          mmc0-sdcard-pins             p   ?   mux         xflash           �sdcard           pcie-2-hog           	ó         œ        ¥   O             «      pcie-3-hog           œ        ¥   ?             «      pwm0-pins            p   5   mux         �pwm0            xpwm          spi0-flash-pins          p      mux         xspi         �spi0 spi0_wp_hold               pwm@10048000              mediatek,mt7988-pwm          ˜    €              P   =   	      	      	      	      	      	      	      	      	       	   !      1   Dtop main pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 pwm8            ·           ?okay             p   6      mcusys@100e0000           mediatek,mt7988-mcusys syscon            ˜                      Ó            p         serial@11000000       *    mediatek,mt7988-uart mediatek,mt6577-uart            ˜                       ó       {           Âuart wakeup          =      '   	   /      	   Dbaud bus            Òdefault         à   
        ?okay             p   @      serial@11000100       *    mediatek,mt7988-uart mediatek,mt6577-uart            ˜                      ó       |           Âuart wakeup          =      '   	   0      	   Dbaud bus          	  ?disabled          serial@11000200       *    mediatek,mt7988-uart mediatek,mt6577-uart            ˜                      ó       }           Âuart wakeup          =      '   	   1      	   Dbaud bus          	  ?disabled          i2c@11003000              mediatek,mt7981-i2c           ˜     0            !p€       €         ó       ˆ           ê            =   	   .   	   *      	   Dmain dma                         +            ?okay            à           Òdefault          p   A   rt5190a@64            richtek,rt5190a          ˜   d        ô                                   p   B   regulators     buck1           rt5190a-buck1           ' MªÐ        ? MªÐ        W                o         �         p         buck2           vcore           ' 	'À        ? \À         o         �      buck3           vproc           ' 	'À        ? \À         o         �         p         buck4           rt5190a-buck4           ' w@        ? w@        W                o         �      ldo         rt5190a-ldo         ' w@        ? w@         o         �               i2c@11004000              mediatek,mt7981-i2c           ˜     @            !q        €         ó       �           ê            =   	   .   	   *      	   Dmain dma                         +            ?okay            à           Òdefault          p   C      i2c@11005000              mediatek,mt7981-i2c           ˜     P            !q€       €         ó       ‘           ê            =   	   .   	   *      	   Dmain dma                         +            ?okay            à           Òdefault          p   D   i2c-mux@70            nxp,pca9545          ˜   p                     +             p   E   i2c@0            ˜                         +             p   F   i2c-gpio-expander@20              nxp,pca9555          ˜             P        `            p   7      rtc@51            nxp,pcf8563          ˜   Q      eeprom@57             atmel,24c02          ˜   W        •           £           §            i2c@1            ˜                        +             p   8      i2c@2            ˜                        +             p   9      i2c@3            ˜                        +             p   G            spi@11007000          *    mediatek,mt7988-spi-quad mediatek,spi-ipm            ˜     p                 ó       Œ             =            *   	   5   	   8          Dparent-clk sel-clk spi-clk hclk                      +            ?okay            à           Òdefault          p   H   nand@0        	    spi-nand             ˜            ¬u         ¾           Ï            p   I   partitions            fixed-partitions                         +      partition@0          ˜                àbl2       partition@200000          
    linux,ubi            ˜    à          àubi                spi@11008000          ,    mediatek,mt7988-spi-single mediatek,spi-ipm          ˜     €                 ó       �             =            +   	   6   	   9          Dparent-clk sel-clk spi-clk hclk                      +            Òdefault         à         	  ?disabled             p   J      spi@11009000          *    mediatek,mt7988-spi-quad mediatek,spi-ipm            ˜     �                 ó       Ž             =            *   	   7   	   :          Dparent-clk sel-clk spi-clk hclk                      +          	  ?disabled             p   K      lvts@1100a000             mediatek,mt7988-lvts-ap         æ            ˜                       =   	   -         ó       Š           ü   	                      lvts-calib-data-1            p   0      usb@11190000          '    mediatek,mt7988-xhci mediatek,mtk-xhci            ˜            .     >              	  Fmac ippc             ó       ­         (   =   	   K   	   M   	   I   	   G   	   U      $   Dsys_ck ref_ck mcu_ck dma_ck xhci_ck                        ?okay            %            p   L      usb@11200000          '    mediatek,mt7988-xhci mediatek,mtk-xhci            ˜             .      >              	  Fmac ippc             ó       ¬         (   =   	   L   	   N   	   J   	   H   	   V      $   Dsys_ck ref_ck mcu_ck dma_ck xhci_ck                              ?okay             p   M      mmc@11230000             	ì        	ß   o        	Ó   o         	Â        °Ül         Å           	¹                 	¯   ?        à   ?        Òdefault state_uhs c           mediatek,mt7988-mmc           ˜    #             Ö                  ó       �             =   	   ?   	   @   	   B   	   A        :      (      )        J                     Dsource hclk axi_cg ahb_cg                        +            ?okay led         p   N      pcie@11280000         *    mediatek,mt7986-pcie mediatek,mt8192-pcie            œpci                      +            ˜    (                	  Fpcie-mac            a            ó       ª           r       ÿ      8   þ�                           ‚                       à            =   	   ]   	   Y   	      	   a      !   Dpl_250m tl_26m peri_26m top_133m            Òdefault         à           ?okay                         	  |pcie-phy            !           †                     `  ™                                                                                              p   O   interrupt-controller                         !                     p            pcie@11290000         *    mediatek,mt7986-pcie mediatek,mt8192-pcie            œpci                      +            ˜    )                	  Fpcie-mac            a            ó       «           r       ÿ      8   þ�       (       (           ‚       (       (       à            =   	   ^   	   Z   	      	   b      !   Dpl_250m tl_26m peri_26m top_133m            Òdefault         à           ?okay            !           †                     `  ™                                                                                              p   P   interrupt-controller                         !                     p            pcie@11300000         *    mediatek,mt7986-pcie mediatek,mt8192-pcie            œpci                      +            ˜    0                	  Fpcie-mac            a             ó       ¨           r       ÿ      8   þ�       0       0           ‚       0       0       à            =   	   [   	   W   	      	   _      !   Dpl_250m tl_26m peri_26m top_133m            Òdefault         à           ?okay            !           †                     `  ™                                                                                              p   Q   interrupt-controller                         !                     p            pcie@11310000         *    mediatek,mt7986-pcie mediatek,mt8192-pcie            œpci                      +            ˜    1                	  Fpcie-mac            a            ó       ©           r       ÿ      8   þ�       8       8           ‚       8       8       à            =   	   \   	   X   	      	   `      !   Dpl_250m tl_26m peri_26m top_133m            Òdefault         à           ?okay            !           †                     `  ™                                                                                              p   R   interrupt-controller                         !                     p            t-phy@11c50000        .    mediatek,mt7986-tphy mediatek,generic-tphy-v2                        +            þ        Å             ?okay             p   S   usb-phy@0            ˜                =   	   T         Dref         §            p         usb-phy@700          ˜     	          =   	   R         Dref         §            p            system-controller@11d10084            mediatek,mt7988-topmisc syscon           ˜    Ñ „      ÿ€         p         xs-phy@11e10000       %    mediatek,mt7988-xsphy mediatek,xsphy                         +            þ        á    9         ?okay             p   T   usb-phy@0            ˜                =   	   S         Dref         §            p         usb-phy@3400             ˜  4             =   	   Q         Dref         §           ²     ”             p            phy@11f20000              mediatek,mt7988-xfi-tphy             ˜    ò                  =             G         Dxfipll topxtal          ü   !            Ç        §             p   U      phy@11f30000              mediatek,mt7988-xfi-tphy             ˜    ó                  =             H         Dxfipll topxtal          ü   !           §             p   V      clock-controller@11f40000             mediatek,mt7988-xfi-pll          ˜    ô                 ü   !            Ó            p          efuse@11f50000        %    mediatek,mt7988-efuse mediatek,efuse             ˜    õ                              +      soc-uuid@140             ˜  @         calib@918            ˜  	   (         p         calib@940            ˜  	@            p   (      calib@954            ˜  	T            p   *      calib@968            ˜  	h            p   +      calib@97c            ˜  	|            p   ,         clock-controller@15000000             mediatek,mt7988-ethsys syscon            ˜                       Ó           2            p   -      switch@15020000           mediatek,mt7988-switch           ˜            €                  !            ó       Ñ           ü   "            ë               ?okay             p   W   ports                        +       port@0           ˜            ö   #      	  internal            àmgmt             p   X      port@1           ˜           ö   $      	  internal          	  ?disabled             p   Y      port@2           ˜           ö   %      	  internal          	  ?disabled             p   Z      port@3           ˜           ö   &      	  internal          	  ?disabled             p   [      port@6           ˜           
   '      	  internal       fixed-link            '                  %            mdio                         +            +      ethernet-phy@0            ethernet-phy-ieee802.3-c22           ˜             ó               (        phy-cal-data            à   )        Ògbe-led          p   #   leds                         +       led@0            ˜            ?okay            8            p   \      led@1            ˜         	  ?disabled             p   ]            ethernet-phy@1            ethernet-phy-ieee802.3-c22           ˜            ó              *        phy-cal-data          	  ?disabled             p   $   leds                         +       led@0            ˜          	  ?disabled             p   ^      led@1            ˜         	  ?disabled             p   _            ethernet-phy@2            ethernet-phy-ieee802.3-c22           ˜            ó              +        phy-cal-data          	  ?disabled             p   %   leds                         +       led@0            ˜          	  ?disabled             p   `      led@1            ˜         	  ?disabled             p   a            ethernet-phy@3            ethernet-phy-ieee802.3-c22           ˜            ó              ,        phy-cal-data          	  ?disabled             p   &   leds                         +       led@0            ˜          	  ?disabled             p   b      led@1            ˜         	  ?disabled             p   c                  clock-controller@15031000             mediatek,mt7988-ethwarp          ˜                     Ó           2            p   "      ethernet@15100000             mediatek,mt7988-eth          ˜                   `   ó       Ä          Å          Æ          Ç          ½          ¾          ¿          À         (  Âfe0 fe1 fe2 fe3 pdma0 pdma1 pdma2 pdma3       À   =   -      -      -      -      -      "       "      "      -         "      K      L      M      N      f                  $      a      d      e   -       -      -        D   Dcrypto fe gp2 gp1 gp3 ethwarp_wocpu2 ethwarp_wocpu1 ethwarp_wocpu0 esw top_eth_gmii_sel top_eth_refck_50m_sel top_eth_sys_200m_sel top_eth_sys_sel top_eth_xgmii_sel top_eth_mii_sel top_netsys_sel top_netsys_500m_sel top_netsys_pao_2x_sel top_netsys_sync_250m_sel top_netsys_ppefb_250m_sel top_netsys_warp_sel xgp1 xgp2 xgp3       0  :             !      A      B      C      E      0  J                                            >   .                     +            C   -        S           à   /        Òdefault         ?okay             p   d   mac@0             mediatek,eth-mac             ˜          	  internal            ?okay             p   '   fixed-link            '                  %         mac@1             mediatek,eth-mac             ˜         	  ?disabled             p   e      mac@2             mediatek,eth-mac             ˜         	  ?disabled             p   f      mdio-bus                         +             p   g   ethernet-phy@15           ethernet-phy-ieee802.3-c45           ˜         	  ?disabled             p   h            sram@15400000         
    mmio-sram            ˜    @                               +            þ    @                   p   .         thermal-zones      cpu-thermal         e  è        {  è        ‰   0             p   i   trips      crit            ™ èH        ¥  Ð      	   £critical             p   j      hot         ™ ÔÀ        ¥  Ð         £hot          p   k      active-high         ™ Á8        ¥  Ð         £active           p   2      active-med          ™ L        ¥  Ð         £active           p   3      active-low          ™  œ@        ¥  Ð         £active           p   4         cooling-maps       map-cpu-active-high         °   1              ¿   2      map-cpu-active-med          °   1              ¿   3      map-cpu-active-low          °   1              ¿   4               timer             arm,armv8-timer                   0   ó                                 
         aliases         Ä/soc/ethernet@15100000/mac@0            Î/soc/i2c@11003000           Ó/soc/i2c@11004000           Ø/soc/i2c@11005000         #  Ý/soc/i2c@11005000/i2c-mux@70/i2c@0        #  â/soc/i2c@11005000/i2c-mux@70/i2c@1        #  ç/soc/i2c@11005000/i2c-mux@70/i2c@2        #  ì/soc/i2c@11005000/i2c-mux@70/i2c@3        chosen          ñ/soc/serial@11000000          pwm-fan           pwm-fan         ý       P   €   ÿ        à   5        Òdefault            6      ÃP                   ?okay             p   1      gpio-keys         
    gpio-keys      button-reset            àreset           ¥                    ˜      button-wps          àWPS         ¥                             gpio-leds         
    gpio-leds      sys-led-red         8           ¥   7               +on           p   l      sys-led-blue            8           ¥   7               +on           p   m         regulator-dvdd1v8             regulator-fixed         DVDD1V8_SOC         ' w@        ? w@         o         �         p   n      regulator-3v3vd           regulator-fixed         3V3VD           ' 2Z         ? 2Z          o         �         p   o      sfp1              sff,sfp         9   8        A      F            K      E           Z                  k  ¸         p   p      sfp2              sff,sfp         9   9        A                  K                 Z                   k  ¸         p   q      __symbols__          ¿/cci            ƒ/opp-table-cci          ‹/cpus/cpu@0         �/cpus/cpu@1         •/cpus/cpu@2         š/cpus/cpu@3         Ÿ/cpus/opp-table-0         "  ¬/soc/interrupt-controller@c000000           \/soc/clock-controller@10001000          °/soc/clock-controller@1001b000          ¹/soc/watchdog@1001c000          Â/soc/clock-controller@1001e000          4/soc/pinctrl@1001f000         !  Í/soc/pinctrl@1001f000/pcie0-pins          !  Ø/soc/pinctrl@1001f000/pcie1-pins          !  ã/soc/pinctrl@1001f000/pcie2-pins          !  î/soc/pinctrl@1001f000/pcie3-pins             ù/soc/pinctrl@1001f000/spi1-pins       !  /soc/pinctrl@1001f000/uart0-pins          %  /soc/pinctrl@1001f000/gbe0-led0-pins          #  /soc/pinctrl@1001f000/i2c0-g0-pins        #  '/soc/pinctrl@1001f000/i2c1-g0-pins        #  1/soc/pinctrl@1001f000/i2c2-g1-pins        !  =/soc/pinctrl@1001f000/mdio0-pins          (  H/soc/pinctrl@1001f000/mmc0-emmc-51-pins       '  Z/soc/pinctrl@1001f000/mmc0-sdcard-pins           k/soc/pinctrl@1001f000/pwm0-pins       &  u/soc/pinctrl@1001f000/spi0-flash-pins           …/soc/pwm@10048000           ‰/soc/mcusys@100e0000            �/soc/serial@11000000            Î/soc/i2c@11003000           ˜/soc/i2c@11003000/rt5190a@64          .  £/soc/i2c@11003000/rt5190a@64/regulators/buck1         .  °/soc/i2c@11003000/rt5190a@64/regulators/buck3           Ó/soc/i2c@11004000           Ø/soc/i2c@11005000           ½/soc/i2c@11005000/i2c-mux@70          #  Å/soc/i2c@11005000/i2c-mux@70/i2c@0        8  Ë/soc/i2c@11005000/i2c-mux@70/i2c@0/i2c-gpio-expander@20       #  Ó/soc/i2c@11005000/i2c-mux@70/i2c@1        #  Þ/soc/i2c@11005000/i2c-mux@70/i2c@2        #  é/soc/i2c@11005000/i2c-mux@70/i2c@3          ô/soc/spi@11007000           ù/soc/spi@11007000/nand@0            /soc/spi@11008000           /soc/spi@11009000           /soc/lvts@1100a000          /soc/usb@11190000           /soc/usb@11200000           /soc/mmc@11230000           $/soc/pcie@11280000        (  */soc/pcie@11280000/interrupt-controller         5/soc/pcie@11290000        (  ;/soc/pcie@11290000/interrupt-controller         F/soc/pcie@11300000        (  L/soc/pcie@11300000/interrupt-controller         W/soc/pcie@11310000        (  ]/soc/pcie@11310000/interrupt-controller         h/soc/t-phy@11c50000         m/soc/t-phy@11c50000/usb-phy@0            y/soc/t-phy@11c50000/usb-phy@700          …/soc/system-controller@11d10084         �/soc/xs-phy@11e10000            “/soc/xs-phy@11e10000/usb-phy@0        "  Ÿ/soc/xs-phy@11e10000/usb-phy@3400           «/soc/phy@11f20000           µ/soc/phy@11f30000           ¿/soc/clock-controller@11f40000          Ç/soc/efuse@11f50000/calib@918           Ø/soc/efuse@11f50000/calib@940           ë/soc/efuse@11f50000/calib@954           þ/soc/efuse@11f50000/calib@968           /soc/efuse@11f50000/calib@97c           L/soc/clock-controller@15000000          $/soc/switch@15020000          "  +/soc/switch@15020000/ports/port@0         "  5/soc/switch@15020000/ports/port@1         "  ?/soc/switch@15020000/ports/port@2         "  I/soc/switch@15020000/ports/port@3         )  S/soc/switch@15020000/mdio/ethernet-phy@0          4  \/soc/switch@15020000/mdio/ethernet-phy@0/leds/led@0       4  j/soc/switch@15020000/mdio/ethernet-phy@0/leds/led@1       )  x/soc/switch@15020000/mdio/ethernet-phy@1          4  �/soc/switch@15020000/mdio/ethernet-phy@1/leds/led@0       4  �/soc/switch@15020000/mdio/ethernet-phy@1/leds/led@1       )  �/soc/switch@15020000/mdio/ethernet-phy@2          4  ¦/soc/switch@15020000/mdio/ethernet-phy@2/leds/led@0       4  ´/soc/switch@15020000/mdio/ethernet-phy@2/leds/led@1       )  Â/soc/switch@15020000/mdio/ethernet-phy@3          4  Ë/soc/switch@15020000/mdio/ethernet-phy@3/leds/led@0       4  Ù/soc/switch@15020000/mdio/ethernet-phy@3/leds/led@1         ç/soc/clock-controller@15031000          ï/soc/ethernet@15100000          ó/soc/ethernet@15100000/mac@0            ù/soc/ethernet@15100000/mac@1            ÿ/soc/ethernet@15100000/mac@2             	/soc/ethernet@15100000/mdio-bus       0  	/soc/ethernet@15100000/mdio-bus/ethernet-phy@15         	/soc/sram@15400000          	$/thermal-zones/cpu-thermal        &  	0/thermal-zones/cpu-thermal/trips/crit         %  	>/thermal-zones/cpu-thermal/trips/hot          -  	K/thermal-zones/cpu-thermal/trips/active-high          ,  	`/thermal-zones/cpu-thermal/trips/active-med       ,  	t/thermal-zones/cpu-thermal/trips/active-low       	  	ˆ/pwm-fan            	Œ/gpio-leds/sys-led-red          	”/gpio-leds/sys-led-blue         	�/regulator-dvdd1v8          	¦/regulator-3v3vd            Ù/sfp1           ä/sfp2            	compatible interrupt-parent #address-cells #size-cells model clocks clock-names operating-points-v2 proc-supply phandle opp-shared opp-hz opp-microvolt reg device_type enable-method mediatek,cci clock-frequency #clock-cells clock-output-names interrupts ranges no-map interrupt-controller #interrupt-cells #reset-cells status reg-names gpio-controller #gpio-cells gpio-ranges function groups pins drive-strength gpio-hog gpios output-high #pwm-cells interrupt-names pinctrl-names pinctrl-0 clock-div vin2-supply vin3-supply vin4-supply regulator-name regulator-min-microvolt regulator-max-microvolt regulator-allowed-modes regulator-boot-on regulator-always-on address-width pagesize spi-max-frequency spi-rx-bus-width spi-tx-bus-width label #thermal-sensor-cells resets nvmem-cells nvmem-cell-names phys mediatek,u3p-dis-msk assigned-clocks assigned-clock-parents linux,pci-domain bus-range phy-names interrupt-map-mask interrupt-map #phy-cells mediatek,syscon-type mediatek,usxgmii-performance-errata dsa,member phy-handle phy-mode ethernet speed full-duplex pause mediatek,pio color sram mediatek,ethsys mediatek,infracfg polling-delay-passive polling-delay thermal-sensors temperature hysteresis cooling-device trip ethernet0 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 stdout-path cooling-levels pwms #cooling-cells linux,code default-state i2c-bus los-gpios mod-def0-gpios tx-disable-gpios maximum-power-milliwatt cci_opp cpu0 cpu1 cpu2 cpu3 cluster0_opp gic topckgen watchdog apmixedsys pcie0_pins pcie1_pins pcie2_pins pcie3_pins spi1_pins uart0_pins gbe0_led0_pins i2c0_pins i2c1_pins i2c2_1_pins mdio0_pins mmc0_pins_emmc_51 mmc0_pins_sdcard pwm0_pins spi0_flash_pins pwm mcusys serial0 rt5190a_64 rt5190_buck1 rt5190_buck3 pca9545 imux0 pca9555 imux1_sfp1 imux2_sfp2 imux3_wifi spi0 spi_nand spi1 spi2 lvts ssusb0 ssusb1 mmc0 pcie2 pcie_intc2 pcie3 pcie_intc3 pcie0 pcie_intc0 pcie1 pcie_intc1 tphy tphyu2port0 tphyu3port0 topmisc xsphy xphyu2port0 xphyu3port0 xfi_tphy0 xfi_tphy1 xfi_pll lvts_calibration phy_calibration_p0 phy_calibration_p1 phy_calibration_p2 phy_calibration_p3 switch gsw_port0 gsw_port1 gsw_port2 gsw_port3 gsw_phy0 gsw_phy0_led0 gsw_phy0_led1 gsw_phy1 gsw_phy1_led0 gsw_phy1_led1 gsw_phy2 gsw_phy2_led0 gsw_phy2_led1 gsw_phy3 gsw_phy3_led0 gsw_phy3_led1 ethwarp eth gmac0 gmac1 gmac2 mdio_bus int_2p5g_phy eth_sram cpu_thermal cpu_trip_crit cpu_trip_hot cpu_trip_active_high cpu_trip_active_med cpu_trip_active_low fan led_red led_blue reg_1p8v reg_3p3v pinctrl-1 cd-gpios cap-sd-highspeed vmmc-supply vqmmc-supply no-mmc output-low 