Ðþí Rh   8 D    (            H Cè                             -    google,ciri-sku0 google,ciri mediatek,mt8188                                     +            7Google Ciri sku0 board     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/dsc@1c009000            Y/soc/ethdr@1c114000          `/soc/mailbox@10320000            e/soc/mailbox@10330000            j/soc/merge0@1c014000             q/soc/merge@1c10c000          x/soc/merge@1c10d000          /soc/merge@1c10e000          †/soc/merge@1c10f000          �/soc/merge@1c110000          ”/soc/mutex@1c016000          ›/soc/mutex@1c101000          ¢/soc/padding@1c11d000            «/soc/padding@1c11e000            ´/soc/padding@1c11f000            ½/soc/padding@1c120000            Æ/soc/padding@1c121000            Ï/soc/padding@1c122000            Ø/soc/padding@1c123000            á/soc/padding@1c124000            ê/soc/rdma@1c104000           õ/soc/rdma@1c105000           /soc/rdma@1c106000          /soc/rdma@1c107000          /soc/rdma@1c108000          !/soc/rdma@1c109000          ,/soc/rdma@1c10a000          7/soc/rdma@1c10b000          B/soc/dsi@1c008000           G/soc/i2c@11280000           L/soc/i2c@11e00000           Q/soc/i2c@11281000           V/soc/i2c@11282000           [/soc/i2c@11e01000           `/soc/i2c@11ec0000           e/soc/i2c@11ec1000           j/soc/mmc@11230000           o/soc/serial@11001100          cpus                         +       cpu@0           wcpu           arm,cortex-a55          ƒ            ‡psci            •w5”         ¥          ¸              È  €         Õ   @        ç   €        ô  €            @           €                    1               E           T   	      cpu@100         wcpu           arm,cortex-a55          ƒ           ‡psci            •w5”         ¥          ¸              È  €         Õ   @        ç   €        ô  €            @           €                    1               E           T   
      cpu@200         wcpu           arm,cortex-a55          ƒ           ‡psci            •w5”         ¥          ¸              È  €         Õ   @        ç   €        ô  €            @           €                    1               E           T         cpu@300         wcpu           arm,cortex-a55          ƒ           ‡psci            •w5”         ¥          ¸              È  €         Õ   @        ç   €        ô  €            @           €                    1               E           T         cpu@400         wcpu           arm,cortex-a55          ƒ           ‡psci            •w5”         ¥          ¸              È  €         Õ   @        ç   €        ô  €            @           €                    1               E           T         cpu@500         wcpu           arm,cortex-a55          ƒ           ‡psci            •w5”         ¥          ¸              È  €         Õ   @        ç   €        ô  €            @           €                    1               E           T         cpu@600         wcpu           arm,cortex-a78          ƒ           ‡psci            •šøÚ         ¥           ¸              È           Õ   @        ç           ô              @                               1              E           T         cpu@700         wcpu           arm,cortex-a78          ƒ           ‡psci            •šøÚ         ¥           ¸              È           Õ   @        ç           ô              @                               1              E           T         cpu-map    cluster0       core0           \   	      core1           \   
      core2           \         core3           \         core4           \         core5           \         core6           \         core7           \               idle-states         `psci       cpu-off-l             arm,idle-state          m            „        •   2        ¦   _        ¶  D        T         cpu-off-b             arm,idle-state          m            „        •   -        ¦   Œ        ¶  ä        T         cluster-off-l             arm,idle-state          m          „        •   7        ¦   ›        ¶  H        T         cluster-off-b             arm,idle-state          m          „        •   2        ¦   È        ¶  è        T            l2-cache0             cache           Ç           Ê           ×   @        é                        Ó        T         l2-cache1             cache           Ç           Ê           ×   @        é                        Ó        T         l3-cache              cache           Ç           Ê            ×   @        é            Ó        T            oscillator-13m            fixed-clock         á            • Æ]@        îclk13m          T   A      oscillator-26m            fixed-clock         á            •Œº€        îclk26m          T   D      oscillator-32k            fixed-clock         á            •  €         îclk32k        opp-table-gpu             operating-points-v2                  T   z   opp-390000000               >í€         Æ        !   ÿ      opp-431000000               °‰À         öì        !   ÿ      opp-473000000               1h@         	'À        !   ÿ      opp-515000000               ²FÀ         	X”        !   ÿ      opp-556000000               !#ã          	‰h        !   ÿ      opp-598000000               #¤Á€         	º<        !   ÿ      opp-640000000               &%           	ë        !   ÿ      opp-670000000               'ïc€         
ä        !   ÿ      opp-700000000               )¹'          
L¸        !   ÿ      opp-730000000               +‚ê€         
}Œ        !   ÿ      opp-760000000               -L®          
®`        !   ÿ      opp-790000000               /q€         
ß4        !   ÿ      opp-835000000               1ÅÀ         (r        !   ÿ      opp-880000000               4s¼          q°        !   ÿ      opp-915000000               6‰ÊÀ         ÓX        !   �      opp-915000000-5             6‰ÊÀ         ¢„        !   0      opp-915000000-6             6‰ÊÀ         q°        !   p      opp-950000000               8ŸÙ€         5         !   �      opp-950000000-5             8ŸÙ€         ÓX        !   0      opp-950000000-6             8ŸÙ€         q°        !   p         pmu-a55           arm,cortex-a55-pmu                      2                  pmu-a78           arm,cortex-a78-pmu                      2                  psci              arm,psci-1.0            Žsmc       sound           =           Ookay          ]  Vaud_etdm_hp_on aud_etdm_hp_off aud_etdm_spk_on aud_etdm_spk_off aud_mtkaif_on aud_mtkaif_off            d           n           x           ‚           Œ           –                         mediatek,mt8188-rt5682s          7mt8188_m98390_5682        á  ®ETDM1_OUT ETDM_SPK_PIN ETDM2_OUT ETDM_HP_PIN ETDM1_IN ETDM_SPK_PIN ETDM2_IN ETDM_HP_PIN ADDA Capture MTKAIF_PIN Headphone Jack HPOL Headphone Jack HPOR IN1P Headset Mic Left Spk Front Left BE_OUT Right Spk Front Right BE_OUT       dai-link-0          ¼ETDM1_IN_BE         Æi2s         Ñcpu       dai-link-1          ¼ETDM1_OUT_BE            Æi2s         Ñcpu    codec           ç               dai-link-2          ¼ETDM2_IN_BE         Ñcpu    codec           ç                dai-link-3          ¼ETDM2_OUT_BE            Ñcpu    codec           ç                dai-link-4          ¼DPTX_BE    codec           ç               thermal-zones      cpu-little0-thermal         ñ  è        ÿ   –                   trips      trip-alert0         % _�        1  Ð        ~passive         T   !      trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical             cooling-maps       map0            <   !      H  A   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little1-thermal         ñ  è        ÿ   –                  trips      trip-alert0         % _�        1  Ð        ~passive         T   "      trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical             cooling-maps       map0            <   "      H  A   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little2-thermal         ñ  è        ÿ   –                  trips      trip-alert0         % _�        1  Ð        ~passive         T   #      trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical             cooling-maps       map0            <   #      H  A   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little3-thermal         ñ  è        ÿ   –                  trips      trip-alert0         % _�        1  Ð        ~passive         T   $      trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical             cooling-maps       map0            <   $      H  A   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-big0-thermal            ñ  è        ÿ   d                  trips      trip-alert0         % _�        1  Ð        ~passive         T   %      trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical             cooling-maps       map0            <   %        A   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-big1-thermal            ñ  è        ÿ   d                  trips      trip-alert0         % _�        1  Ð        ~passive         T   &      trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical             cooling-maps       map0            <   &        A   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            apu-thermal         ñ  è        ÿ   ú           '       trips      trip-alert0         % L        1  Ð        ~passive       trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical                gpu-thermal         ñ  è        ÿ   ú           '      trips      trip-alert0         % L        1  Ð        ~passive         T   (      trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical             cooling-maps       map0            <   (        A   )ÿÿÿÿÿÿÿÿ            gpu1-thermal            ñ  è        ÿ   ú           '      trips      trip-alert0         % L        1  Ð        ~passive         T   *      trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical             cooling-maps       map0            <   *        A   )ÿÿÿÿÿÿÿÿ            adsp-thermal            ñ  è        ÿ   ú           '      trips      trip-alert0         % L        1  Ð        ~passive       trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical                vdo-thermal         ñ  è        ÿ   ú           '      trips      trip-alert0         % L        1  Ð        ~passive       trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical                infra-thermal           ñ  è        ÿ   ú           '      trips      trip-alert0         % L        1  Ð        ~passive       trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical                cam1-thermal            ñ  è        ÿ   ú           '      trips      trip-alert0         % L        1  Ð        ~passive       trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical                cam2-thermal            ñ  è        ÿ   ú           '      trips      trip-alert0         % L        1  Ð        ~passive       trip-alert1         % s        1  Ð        ~hot       trip-crit           % †         1          	  ~critical                   timer             arm,armv8-timer                   @  2                                             
               • Æ]@      soc                      +             simple-bus          P                                T   performance-controller@11bc10             mediatek,cpufreq-hw          ƒ     ¼            ½0               [           T         interrupt-controller@c000000              arm,gic-v3          u           †                        �         ƒ                                    2      	               T      ppi-partitions     interrupt-partition-0           ²   	   
                    T         interrupt-partition-1           ²              T               syscon@10000000            mediatek,mt8188-topckgen syscon         ƒ                      á           T   .      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon          ƒ                     á           »           T   /      syscon@10003000           mediatek,mt8188-pericfg syscon          ƒ     0                á           T   X      pinctrl@10005000              mediatek,mt8188-pinctrl       `  ƒ     P            À             á             â             ê              °              0  Èiocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint          Ò        â           î   +           °         �        2       ë               u        B  úGSC_AP_INT_ODL AP_DISP_BKLTEN  EN_PPVAR_MIPI_DISP EN_PPVAR_MIPI_DISP_150MA TCHSCR_RST_1V8_L      I2S_SPKR_DATAOUT EN_PP3300_WLAN_X WIFI_KILL_1V8_L BT_KILL_1V8_L AP_FLASH_WP_L   WCAM_PWDN_L WCAM_RST_L UCAM_PWDM_L UCAM_RST_L WCAM_24M_CLK UCAM_24M_CLK MT6319_INT DISP_RST_1V8_L DSIO_DSI_TE  TP MIPI_BL_PWM_1V8  UART_AP_TX_GSC_RX UART_GSC_TX_AP_RX UART_SSPM_TX_DBGCON_RX UART_DBGCON_TX_SSPM_RX UART_ADSP_TX_DBGCON_RX UART_DBGCON_TX_ADSP_RX JTAG_AP_TMS JTAG_AP_TCK JTAG_AP_TDI JTAG_AP_TDO JTAG_AP_TRST AP_KPCOL0 TP  TP EC_AP_HPD_OD PCIE_WAKE_1V8_ODL PCIE_RST_1V8_L PCIE_CLKREQ_1V8_ODL      AP_I2C_AUD_SCL_1V8 AP_I2C_AUD_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_TPM_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_PMIC_SAR_SCL_1V8 AP_I2C_PMIC_SAR_SDA_1V8 AP_I2C_EC_HID_KB_SCL_1V8 AP_I2C_EC_HID_KB_SDA_1V8 AP_I2C_UCAM_SCL_1V8 AP_I2C_UCAM_SDA_1V8 AP_I2C_WCAM_SCL_1V8 AP_I2C_WCAM_SDA_1V8 SPI_AP_CS_EC_L SPI_AP_CLK_EC SPI_AP_DO_EC_DI SPI_AP_DI_EC_DO TP TP SPI_AP_CS_TCHSCR_L SPI_AP_CLK_TCHSCR SPI_AP_DO_TCHSCR_DI SPI_AP_DI_TCHSCR_DO TP TP TP TP    TP      PWRAP_SPI_CS_L PWRAP_SPI_CK PWRAP_SPI_MOSI PWRAP_SPI_MISO SRCLKENA0 SRCLKENA1 SCP_VREQ_VAO AP_RTC_CLK32K AP_PMIC_WDTRST_L AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1  HP_INT_ODL SPKR_INT_ODL I2S_HP_DATAIN EN_SPKR I2S_SPKR_MCLK I2S_SPKR_BCLK I2S_HP_MCLK I2S_HP_BCLK I2S_HP_LRCK I2S_HP_DATAOUT RST_SPKR_L I2S_SPKR_LRCK I2S_SPKR_DATAIN     SPI_AP_CLK_ROM SPI_AP_CS_ROM_L SPI_AP_DO_ROM_DI SPI_AP_DI_ROM_DO TP TP         EN_PP2800A_UCAM_X EN_PP1200_UCAM_X EN_PP2800A_WCAM_X EN_PP1100_WCAM_X TCHSCR_INT_1V8_L  MT7921_PMU_EN_1V8  AP_EC_WARM_RST_REQ EC_AP_HID_INT_ODL EC_AP_INT_ODL AP_XHCI_INIT_DONE EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_RST_L EMMC_CMD EMMC_CLK EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 EMMC_DSL         USB3_HUB_RST_L EC_AP_RSVD0_ODL   SPMI_SCL SPMI_SDA           T   +   adsp-uart-pins          T   L   pins-bus            
  #  $         aud-etdm-hp-on-pins         T      pins-bus            
  n  s  t  u      pins-mclk           
  r         aud-etdm-hp-off-pins            T      pins-bus            
  n   s   t   u                          pins-mclk           
  r                             aud-etdm-spk-on-pins            T      pins-bus            
    q  w  x        -            aud-etdm-spk-off-pins           T      pins-bus            
     q   w   x                             aud-mtkaif-on-pins          T      pins-bus            
  e  f  g  h  i  j         aud-mtkaif-off-pins         T      pins-bus            
  e   f   g   h   i   j                             cros-ec-int-pins            T   O   pins-ec-ap-int-odl          
  •                    disp-pwm0-pins          T   Q   pins-disp-pwm0          
           <         disp-pwm1-pins          T   R   pins-disp-pwm1          
           <         dp-tx-hpd-pins          T   ±   pins-dp-tx-hpd          
  .         gsc-int-pins            T   s   pins-gsc-ap-int-odl         
                       i2c0-pins           T   c   pins-bus            
  8  7         i2c1-pins           T   r   pins-bus            
  :  9         i2c2-pins           T   g   pins-bus            
  <  ;         H        -            i2c3-pins           T   h   pins-bus            
  >  =         i2c4-pins           T   t   pins-bus            
  @  ?         i2c5-pins           T   v   pins-bus            
  B  A         i2c6-pins           T   w   pins-bus            
  D  C         mipi-disp-avdd-en-pins          T   ·   pins-en-ppvar-mipi-disp         
            U         mipi-disp-avee-en-pins          T   ¸   pins-en-ppvar-mipi-disp-150ma           
            U         mipi-dsi-pins           T   —   pins-bus            
               U         mmc0-default-pins           T   ^   pins-bus          $  
  ¡     Ÿ  ž  š  ™  ˜  —  œ                  -           `   e      pins-clk            
  �        -              f      pins-rst            
  ›        -           `   e         mmc0-uhs-pins           T   _   pins-bus          $  
  ¡     Ÿ  ž  š  ™  ˜  —  œ                  -           `   e      pins-clk            
  �        -              f      pins-ds         
  ¢        -              f      pins-rst            
  ›        -           `   e         nor-default-pins            T   p   pins-clk            
    }  €               pins-cs         
  ~         `         pcie-default-pins           T   o   pins-bus            
  /  0  1         scp-pins            T   B   pins-scp-vreq           
  b         H         spi0-pins           T   N   pins-bus            
  E  F  G  H         H         spi1-default-pins           T   S   pins-bus            
  K  L  M  N         H         spi1-sleep-pins         T   T   pins-bus            
  K   L   M   N                             spi2-pins           T   U   pins-bus            
  O  P  Q  R         H         uart0-pins          T   M   pins-bus            
              `         wlan-en-pins            T   µ   pins-en-pp3300-wlan         
            U         audio-codec-pins            T   d   pins-hp-int-odl         
  l                    speaker-en-pins         T   f   pins-en-spkr            
  o             syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd            ƒ     `           power-controller          !    mediatek,mt8188-power-controller                         +            m           T   E   power-domain@0          ƒ                         +            m           �   ,   power-domain@1          ƒ           �   -      .           –mfg alt         ¢   /                     +            m           �   0   power-domain@2          ƒ           m          power-domain@3          ƒ           m          power-domain@4          ƒ           m                power-domain@15         ƒ         à  �   .      .      .      .   
   .   3   .   4   .   =   .   ¹   .   ¾   1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1      1          û  –top cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1          ¢   /                     +            m      power-domain@16         ƒ         H  �   .   »   .   À   2      2      2      2      2      2      2         A  –cfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus            ¢   /                     +            m      power-domain@20         ƒ         0  �   .   º   .   ¿   3      3      3      3         8  –cfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6         ¢   /        m          power-domain@22         ƒ           �   4            –ss-vdec1-soc-l1         ¢   /                     +            m      power-domain@23         ƒ           �   5            –ss-vdec2-l1         ¢   /        m             power-domain@29         ƒ            �   .      .      .   	   .   ½        –cam ccu bus cfgck           ¢   /                     +            m           �   6   power-domain@30         ƒ         (  �   7       7      7      7      7         6  –ss-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys           ¢   /                     +            m      power-domain@32         ƒ            �   7      8       9          $  –ss-camb-sub ss-camb-raw ss-camb-yuv         m          power-domain@31         ƒ           �   7      :       ;          $  –ss-cama-sub ss-cama-raw ss-cama-yuv         m                power-domain@17         ƒ         (  �   .   ¼   .   Á   <       <      <         &  –cfgck cfgxo ss-larb2 ss-larb3 ss-gals           ¢   /                     +            m      power-domain@9          ƒ   	        �   .   @   .   ?      	  –bus hdcp            ¢   /        m          power-domain@18         ƒ           ¢   /        m          power-domain@19         ƒ           ¢   /        m             power-domain@24         ƒ            �   =       =      =      =         0  –ss-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram         ¢   /        m          power-domain@21         ƒ           �   >      >           –ss-wpe-l7 ss-wpe-l7pce          ¢   /        m                power-domain@5          ƒ           ¢   /        �   ?           –ss-pextp-fmem           m          power-domain@7          ƒ           �   .   0   .   1        –seninf0 seninf1         m          power-domain@6          ƒ           m          power-domain@10         ƒ   
        �   .   E   .   D      	  –bus main            ¢   /                     +            m      power-domain@11         ƒ           ¢   /                     +            m      power-domain@14         ƒ           �   .   F        –asm         ¢   /        m          power-domain@13         ƒ           �   .   S   .      @            –a1sys intbus adspck         ¢   /        m          power-domain@12         ƒ           ¢   /        m                power-domain@8          ƒ           �   ?         	  –ethermac            ¢   /        m                watchdog@10007000             mediatek,mt8188-wdt         ƒ     p                 ´        »           T   F      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon           ƒ     À                á           T   -      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer         ƒ    p                2      	               �   A      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon          ƒ    @                Èpwrap           2       ó               �   /      /          	  –spi wrap       pmic              mediatek,mt6359          �        u           Ì           Ý   +   Þ      adc           mediatek,mt6359-auxadc          ñ         audio-codec           mediatek,mt6359-codec                                 *         regulators            mediatek,mt6359-regulator      buck_vs1            >vs1         M 5         e !‘À        }             ™      buck_vgpu11         >vgpu11          M €        e 7        ­  ˆ        }   È        Â                   ™      buck_vmodem         >vmodem          M ÓX        e ÓX        ­  *        }   È      buck_vpu            >vpu         M €        e 7        ­  ˆ        }   È        Â                   ™      buck_vcore          >vcore           M €        e Ö         ­  ˆ        }   È        Â                   ™      buck_vs2            >vs2         M 5         e j         }             ™      buck_vpa            >vpa         M ¡         e /M`        }  ,      buck_vproc2         >ppvar_dvdd_vgpu         M dp        e 5         ­  L        }   È        Â                  Ú   0        ñ  j        T   ,      buck_vproc1         >vproc1          M €        e 7        ­  L        }   È        Â                  T   6      buck_vcore_sshub            >vcore_sshub         M €        e 7      buck_vgpu11_sshub           >vgpu11_sshub            M dp        e dp         ™      ldo_vaud18          >vaud18          M w@        e w@        }   ð      ldo_vsim1           >vsim1           M ð         e /M`      ldo_vibr            >vibr            M O€        e 2Z       ldo_vrf12           >vrf12           M Èà        e Ö          ™      ldo_vusb            >vusb            M -ÆÀ        e -ÆÀ        }  À         ™      ldo_vsram_proc2         >vsram_proc2         M ¡         e ½¶        ­  L        }   ð         ™      ldo_vio18           >vio18           M ð         e ýà        }  À         ™        T   e      ldo_vcamio          >vcamio          M ð         e ýà      ldo_vcn18           >vcn18           M w@        e w@        }   ð      ldo_vfe28           >vfe28           M *¹€        e *¹€        }   x      ldo_vcn13           >vcn13           M »         e Ö       ldo_vcn33_1_bt          >vcn33_1_bt          M *¹€        e 5gà      ldo_vcn33_1_wifi            >vcn33_1_wifi            M *¹€        e 5gà      ldo_vaux18          >vaux18          M w@        e w@        }   ð         ™      ldo_vsram_others            >pp0850_dvdd_sram_gpu            M q°        e 5         ­  ˆ        }   ð        Ú   ,        ñ  j        T   0      ldo_vefuse          >vefuse          M ð         e „€      ldo_vxo22           >vxo22           M w@        e !‘À         ™      ldo_vrfck           >vrfck           M ã`        e ð       ldo_vrfck_1         >vrfck           M ëÀ        e j       ldo_vbif28          >vbif28          M *¹€        e *¹€        }   ð      ldo_vio28           >vio28           M *¹€        e 2Z       ldo_vemc            >vemc            M ,@         e 2Z       ldo_vemc_1          >vemc            M &%         e 2Z         T   `      ldo_vcn33_2_bt          >vcn33_2_bt          M *¹€        e 5gà      ldo_vcn33_2_wifi            >vcn33_2_wifi            M *¹€        e 5gà      ldo_va12            >va12            M O€        e Ö          ™      ldo_va09            >va09            M 5         e O€      ldo_vrf18           >vrf18           M ð         e žP      ldo_vsram_md          	  >vsram_md            M 5         e 5         ­  *        }   ð      ldo_vufs            >vufs            M ð         e ýà         ™        T   a      ldo_vm18            >vm18            M w@        e ýà         †         T   ›      ldo_vbbck           >vbbck           M Èà        e O€      ldo_vsram_proc1         >vsram_proc1         M ¡         e ½¶        ­  L        }   ð         ™      ldo_vsim2           >vsim2           M ð         e /M`      ldo_vsram_others_sshub          >vsram_others_sshub          M ¡         e ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi            ƒ    p            �                Èpmif spmimst            )   .   8        9   .   ¬        �   /      /       .   8      (  –pmif_sys_ck pmif_tmr_ck spmimst_clk_mux       iommu@10315000            mediatek,mt8188-iommu-infra         ƒ    1P                2                     P           T   m      mailbox@10320000              mediatek,mt8188-gce         ƒ    2        @         2       â               ]           �   /           T   {      mailbox@10330000              mediatek,mt8188-gce         ƒ    3        @         2       ä               ]           �   /           T   }      scp@10720000              mediatek,mt8188-scp-dual            ƒ    r                 Ècfg                      +           T        P             Ookay       scp@0             mediatek,scp-core           ƒ               Èsram            2      Î               Ookay            Vdefault         d   B        i   C        T   ~      scp@d0000             mediatek,scp-core           ƒ    ð         Èsram            2      Ï             	  Odisabled             audio-controller@10b10000             mediatek,mt8188-afe         ƒ    ±                 )   .   S        9   .   „      ´  �   D   -   	   -   
   .   ³   .   ´   .   µ   .   ¶   .   ¸   .   S   .      .       .   E   .   Q   .   M   .   N   .   O   .   P   @       .   „   .   †   .   ·   .   T   .   R      ÿ  –clk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          2      6               w   E           …   F         	  Œaudiosys            ¢   /        ˜   .        Ookay            i   G        ª            Ë           T         adsp@10b80000             mediatek,mt8188-dsp       @  ƒ    ¸              Ð             ¸°            ¸ð                Ècfg sram sec bus            )   .   D        �   .   D   .   E        –audiodsp adsp_bus           ë   H   I        òrx tx           w   E           Ookay            i   J   K        Vdefault         d   L        T         mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         ƒ    ¸a                2      Þ               ]            T   H      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         ƒ    ¸q                2      ß               ]            T   I      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m           ƒ    ¹                á           T   @      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart           ƒ                     2       �               �   D   /         	  –baud bus            Ookay            Vdefault         d   M      serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart           ƒ                     2       Ž               �   D   /         	  –baud bus          	  Odisabled          serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart           ƒ                     2       �               �   D   /         	  –baud bus          	  Odisabled          serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart           ƒ                     2      Ó               �   D   /         	  –baud bus          	  Odisabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc           ƒ                      �   /           –main            ñ           Ookay          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon           ƒ     0                á           T   ?      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ƒ                      2       ¿               �   .   y   .      /           –parent-clk sel-clk spi-clk          Ookay            Vdefault         d   N   ec@0              google,cros-ec-spi          ƒ            Ý   +   •           Vdefault         d   O        ý -ÆÀ   i2c-tunnel            google,cros-ec-i2c-tunnel                                   +       sbs-battery@f             sbs,sbs-battery         ƒ           !           5            cbas              google,cros-cbas          keyboard-controller           google,cros-ec-keyb         J           Z            m     D  ‡  ž ­t x à á ø	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	 Ž + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      (  ”               	  	                 thermal-sensor@1100b000           mediatek,mt8188-lvts-ap         ƒ     °                2       È               �   /           …   /           ©   P        µlvts-calib-data-1           Æ           T   '      pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           ƒ     à                �   .   '   /   /        –main mm         2       Ë               Ü           Ookay            Vdefault         d   Q        T   ´      pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           ƒ     ð                �   .   (   /   F        –main mm         2                     Ü         	  Odisabled            Vdefault         d   R      spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ƒ                     2       À               �   .   y   .      /   2        –parent-clk sel-clk spi-clk          Ookay            Vdefault sleep           d   S        n   T      spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ƒ                     2       Á               �   .   y   .      /   3        –parent-clk sel-clk spi-clk          Ookay            Vdefault         d   U      spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ƒ    0                2       Â               �   .   y   .      /   4        –parent-clk sel-clk spi-clk        	  Odisabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ƒ    €                2       Ã               �   .   y   .      /   8        –parent-clk sel-clk spi-clk        	  Odisabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ƒ    �                2       Ä               �   .   y   .      /   9        –parent-clk sel-clk spi-clk        	  Odisabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ƒ            -ÿ     >              	  Èmac ippc            T                     ?                      +           2       €               )   .   )        9   .   v        �   ?   	   .   Å   ?   
        –sys_ck ref_ck mcu_ck            ç   V      W            ì        ú   X  h           Ookay            	host            	   Y   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ƒ                       Èmac         2       �               )   .   *        9   .   v        �   ?   
        –sys_ck          Ookay            	   Y        	'   Z         ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a          ƒ           @         2      Ì               	3macirq        0  �   ?       ?      .   A   .   B   .   C   ?         .  –axi apb mac_main ptp_ref rmii_internal mac_cg           )   .   A   .   B   .   C        9   .       .   ¢   .   £        w   E           	C   /        	T   [        	d   \        	w   ]        	Š           	•           	           	  Odisabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           	­                                 	·           	Ç           T   [      rx-queues-config            	×            	í        T   \   queue0           	þ        
          queue1           	þ        
          queue2           	þ        
          queue3           	þ        
             tx-queues-config            
)            
?        T   ]   queue0           	þ        
Q            
_         queue1           	þ        
Q           
_         queue2           	þ        
Q           
_         queue3           	þ        
Q           
_               mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ƒ    #             õ                 Ý          ƒ                �   .      /      /      /   M      !  –source hclk source_cg crypto_clk            Ookay            
k            
u         
‡        
˜ H        ëÂ          
§         
¶         
Å         
ß         
å         
í        Vdefault state_uhs           d   ^        n   _         
û           `           a      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ƒ    $             ë                 Ý          ‡               �   .      /      /   $        –source hclk source_cg           )   .           9   .   �      	  Odisabled          mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ƒ    %             æ                 Ý          ˆ               �   .      /      /   A        –source hclk source_cg           )   .           9   .   �      	  Odisabled          thermal-sensor@11278000           mediatek,mt8188-lvts-mcu            ƒ    '€                2       Ê               �   /           …   /            ©   P        µlvts-calib-data-1           Æ           T          i2c@11280000              mediatek,mt8188-i2c          ƒ    (             " €       €        2       —               !           �   b       /   7      	  –main dma                         +            Ookay            Vdefault         d   c        • €   audio-codec@1a            realtek,rt5682s         ƒ           Ý   +   l           Vdefault         d   d        Ì           +   e        7   e        D   e        S   Y        a           T         amplifier@38              maxim,max98390          ƒ   8        pFront Right         ‚   +   v           Vdefault         d   f        Ì            T         amplifier@39              maxim,max98390          ƒ   9        pFront Left          Ì            T            i2c@11281000              mediatek,mt8188-i2c          ƒ    (            "€       €        2       ’               !           �   b      /   7      	  –main dma                         +            Ookay            Vdefault         d   g        • €      i2c@11282000              mediatek,mt8188-i2c          ƒ    (             "€       €        2       “               !           �   b      /   7      	  –main dma                         +            Ookay            Vdefault         d   h        • €      clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c          ƒ    (0                á           T   b      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ƒ    *       -ÿ    *>              	  Èmac ippc            T            *        ?                      +           2                     )   .   -        9   .   v        �   ?      .   Ë   ?           –sys_ck ref_ck mcu_ck            ç   i            ì        ú   X  p           Ookay            	host            	   Y   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ƒ                       Èmac         2                     )   .   .        9   .   v        �   ?           –sys_ck          Ookay             Ž         usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ƒ    +       -ÿ    +>              	  Èmac ippc            T            +        ?                      +           2                     )   .   ,        9   .   v        �   ?      .   É   ?           –sys_ck ref_ck mcu_ck            ç   j            ì        ú   X  `           Ookay            	host            	   Y   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ƒ                       Èmac         2                     )   .   +        9   .   v        �   ?           –sys_ck          Ookay            	'   k         pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie           ƒ    /                	  Èpcie-mac            T‚                                  Ÿ       ÿ        wpci         ©                         +         0  �   /   L   /   #   /   &   /   +   /   C   ?         /  –pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          u           2                   `  º                  l                      l                     l                     l           È                       Û       m      ÿÿ        å            ç   n         	  ôpcie-phy            w   E           …   F           Œmac         Ookay            Vdefault         d   o   interrupt-controller                         u            �        T   l         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor         ƒ    2À                �   .   X   ?      ?           –spi sf axi          )   .   X        2      9                            +            Ookay            Vdefault         d   p   flash@0           jedec,spi-nor           ƒ            ýu          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3           T        Â                         +           w   E           Ookay       pcie-phy@0          ƒ               �   .   Ä        –ref         þ           T   n         hdmi-phy@11d5f000         2    mediatek,mt8188-hdmi-phy mediatek,mt8195-hdmi-phy           ƒ    Õð                �   /           –pll_ref         îhdmi_txpll          á            þ            	   
                 	  Odisabled            T   ¯      dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         ƒ    È                 �   D        îmipi_tx0_pll            á            þ            Ookay            *  P        T   –      dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         ƒ    É                 �   D        îmipi_tx0_pll            á            þ          	  Odisabled            T   Ÿ      i2c@11e00000              mediatek,mt8188-i2c          ƒ    à             "        €        2       ˜               !           �   q       /   7      	  –main dma                         +            Ookay            Vdefault         d   r        • €   tpm@50            google,cr50         ƒ   P        Ý   +               Vdefault         d   s         i2c@11e01000              mediatek,mt8188-i2c          ƒ    à            "€       €        2       ”               !           �   q      /   7      	  –main dma                         +            Ookay            Vdefault         d   t        • €      clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w          ƒ    à                 á           T   q      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           T        ã             Ookay       usb-phy@0           ƒ               �   .   Ê   -           –ref da_ref          þ           T   j         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           T        ä             Ookay       usb-phy@0           ƒ               �   .   Æ   -           –ref da_ref          þ           T   V      usb-phy@700         ƒ              �   -      D        –ref da_ref          þ           T   W         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           T        è             Ookay       usb-phy@0           ƒ               �   .   Ì   -           –ref da_ref          þ           T   i         i2c@11ec0000              mediatek,mt8188-i2c          ƒ    ì             "€       €        2       •               !           �   u       /   7      	  –main dma                         +            Ookay            Vdefault         d   v        • €      i2c@11ec1000              mediatek,mt8188-i2c          ƒ    ì            "        €        2       –               !           �   u      /   7      	  –main dma                         +            Ookay            Vdefault         d   w        • €      clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en         ƒ    ì                 á           T   u      efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse         ƒ    ò                              +      dp-calib@1a0            ƒ              T   °      lvts1-calib@1ac         ƒ  ¬   @        T   P      gpu-speedbin@581            ƒ  �           B               T   y      socinfo-data1@7a0           ƒ            socinfo-data2@7e0           ƒ  à            gpu@13000000          )    mediatek,mt8188-mali arm,mali-valhall-jm            ƒ             @         �   x          0  2                   ~             }               	3job mmu gpu         ©   y      
  µspeed-bin           G   z        w   E      E      E           [core0 core1 core2           E           Ookay            n   ,        T   )      clock-controller@13fbf000             mediatek,mt8188-mfgcfg          ƒ    ûð                á           T   x      syscon@14000000           mediatek,mt8188-vppsys0 syscon          ƒ                      á           T   1      dma-controller@14001000           mediatek,mt8188-mdp3-rdma           ƒ                     z           �   1         <  ë   {         {         {         {         {              …   |   €        w   E           Œ   }                  ¤              ¸   ~      display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ƒ                      �   1            Œ   }                 display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ƒ     @                �   1   "        Œ   }      @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ƒ     P                2      F               �   1   
        w   E           Œ   }      P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ƒ     `                �   1           Œ   }      `            ¤    %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ƒ     p                �   1   #        Œ   }      p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ƒ     €                2      I               �   1   $        w   E           Œ   }      €          display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl           ƒ     �                2      J               �   1   %        w   E           Œ   }      �            …   |   ‚      display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ƒ                      �   1           w   E           Œ   }                 display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc           ƒ     °                �   1           Œ   }      °          display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ƒ     À                z           �   1           …   |   ƒ        w   E           Œ   }      À            ¤    +      mutex@1400f000            mediatek,mt8188-vpp-mutex           ƒ     ð                2      P               �   1           w   E           Œ   }      ð          smi@14012000              mediatek,mt8188-smi-common-vpp          ƒ                     �   1      1           –apb smi         w   E           T         smi@14013000              mediatek,mt8188-smi-larb            ƒ    0                �   1      1           –apb smi         w   E           Å           Ö           T   ‚      iommu@14018000            mediatek,mt8188-iommu-vpp           ƒ    €       P         �   1           –bclk            2      R               w   E           P           ã   €   �   ‚   ƒ   „   …        T   |      dma-controller@14f09000           mediatek,mt8188-mdp3-rdma           ƒ    ð�                z           �   3   
        …   †   ¤        w   E           Œ   }   	  �            ¤  …  ©      dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma           ƒ    ð                 z           �   3           …   |   À        w   E           Œ   }   	               ¤  †  ª      display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ƒ    ðÀ                �   3           Œ   }   	  À          display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ƒ    ðÐ                �   3           Œ   }   	  Ð          display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ƒ    ðð                �   3   "        Œ   }   	  ð          display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ƒ    ñ                 �   3   $        Œ   }   
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ƒ    ñ                 2      j               �   3   #        w   E           Œ   }   
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ƒ    ñ0                2      k               �   3   %        w   E           Œ   }   
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ƒ    ñP                �   3           Œ   }   
  P            ¤  ‘  °      display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ƒ    ñ`                �   3           Œ   }   
  `            ¤  ’  ±      display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ƒ    ñ€                �   3           Œ   }   
  €          display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ƒ    ñ�                �   3           Œ   }   
  �          display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           ƒ    ñ                 �   3           w   E           Œ   }   
             display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           ƒ    ñ°                �   3           w   E           Œ   }   
  °          display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ƒ    ñÐ                2      u               �   3           w   E           Œ   }   
  Ð          display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ƒ    ñà                2      v               �   3           w   E           Œ   }   
  à          display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ƒ    ò                �   3           w   E           Œ   }               display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ƒ    ò                 �   3           w   E           Œ   }                display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ƒ    ò@                z           �   3           …   †   ¦        w   E           Œ   }     @            ¤     ¬      display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ƒ    òP                z           �   3           …   |   Â        w   E           Œ   }     P            ¤  ¡  ­      clock-controller@14e00000             mediatek,mt8188-wpesys          ƒ    à                 á           T   >      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0         ƒ    à                 á         smi@14e04000              mediatek,mt8188-smi-larb            ƒ    à@                �   >      >           –apb smi         w   E           Å           Ö           T   „      syscon@14f00000           mediatek,mt8188-vppsys1 syscon          ƒ    ð                 á           T   3      mutex@14f01000            mediatek,mt8188-vpp-mutex           ƒ    ð                2      {               �   3   &        w   E           Œ   }   	            smi@14f02000              mediatek,mt8188-smi-larb            ƒ    ð                 �   3      3           –apb smi         w   E           Å           Ö   ‡        T   ¥      smi@14f03000              mediatek,mt8188-smi-larb            ƒ    ð0                �   3      3           –apb smi         w   E           Å           Ö           T   ƒ      clock-controller@15000000             mediatek,mt8188-imgsys          ƒ                      á         clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top         ƒ                     á           »         clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr          ƒ                     á           »         clock-controller@15220000             mediatek,mt8188-imgsys-wpe1         ƒ    "                 á           »         clock-controller@15330000             mediatek,mt8188-ipesys          ƒ    3                 á           »         clock-controller@15520000             mediatek,mt8188-imgsys-wpe2         ƒ    R                 á           »         clock-controller@15620000             mediatek,mt8188-imgsys-wpe3         ƒ    b                 á           »         clock-controller@16000000             mediatek,mt8188-camsys          ƒ                      á           T   7      clock-controller@1604f000             mediatek,mt8188-camsys-rawa         ƒ    ð                á           »           T   :      clock-controller@1606f000             mediatek,mt8188-camsys-yuva         ƒ    ð                á           »           T   ;      clock-controller@1608f000             mediatek,mt8188-camsys-rawb         ƒ    ð                á           »           T   8      clock-controller@160af000             mediatek,mt8188-camsys-yuvb         ƒ    
ð                á           »           T   9      clock-controller@17200000             mediatek,mt8188-ccusys          ƒ                      á         video-decoder@18000000            mediatek,mt8188-vcodec-dec           ƒ                   @                T                    `         …   |  æ                     +           ¸   ~   video-codec@10000             mediatek,mtk-vcodec-lat         ƒ                      )   .   4        9   .   x         �   .   4   4      4      .   x        –sel vdec lat top            2      Ä             H  …   |  à   |  á   |  â   |  ã   |  ä   |  å   |  æ   |  ç   |  è        w   E         video-codec@25000             mediatek,mtk-vcodec-core            ƒ     P                )   .   4        9   .   x         �   .   4   5      5      .   x        –sel vdec lat top            2      Ã             X  …   †  À   †  Á   †  Â   †  Ã   †  Ä   †  Å   †  Æ   †  Ç   †  È   †  É   †  Ê        w   E            smi@1800d000              mediatek,mt8188-smi-larb            ƒ     Ð                �   4       4            –apb smi         w   E           Å           Ö           T   …      clock-controller@1800f000             mediatek,mt8188-vdecsys-soc         ƒ     ð                á           T   4      smi@1802e000              mediatek,mt8188-smi-larb            ƒ    à                �   5       5            –apb smi         w   E           Å           Ö   ‡        T   §      clock-controller@1802f000             mediatek,mt8188-vdecsys         ƒ    ð                á           T   5      clock-controller@1a000000             mediatek,mt8188-vencsys         ƒ                      á           T   =      smi@1a010000              mediatek,mt8188-smi-larb            ƒ                     �   =      =           –apb smi         w   E           Å           Ö   ‡        T   ¦      video-encoder@1a020000            mediatek,mt8188-vcodec-enc          ƒ                                  +           )   .   3        9   .   p        �   =         	  –venc_sel            2      a             X  …   †      †  ¡   †  ¢   †  £   †  ¤   †  ¶   †  ·   †  ¸   †  ¹   †  ª   †  º        w   E           ¸   ~      jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc          ƒ                     �   =           –jpgenc          2      b                …   †  §   †  ¨   †  ©   †  ¬        w   E         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec           ƒ                     �   =       =           –jpgdec-smi jpgdec           2      c             0  …   †  ­   †  ®   †  ²   †  ³   †  ´   †  µ        w   E         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl           ƒ                      �   2            2      |               …   †           w   E           Œ   {             ports                        +       port@0          ƒ       endpoint            ò   ˆ        T   ¢         port@1          ƒ      endpoint            ò   ‰        T   Š               rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma         ƒ                      �   2           2      ~               …   |            w   E           Œ   {             ports                        +       port@0          ƒ       endpoint            ò   Š        T   ‰         port@1          ƒ      endpoint            ò   ‹        T   Œ               color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color           ƒ     0                �   2           2                     w   E           Œ   {     0       ports                        +       port@0          ƒ       endpoint            ò   Œ        T   ‹         port@1          ƒ      endpoint            ò   �        T   Ž               ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr           ƒ     @                �   2           2      €               w   E           Œ   {     @       ports                        +       port@0          ƒ       endpoint            ò   Ž        T   �         port@1          ƒ      endpoint            ò   �        T   �               aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal           ƒ     P                �   2           2      �               w   E           Œ   {     P       ports                        +       port@0          ƒ       endpoint            ò   �        T   �         port@1          ƒ      endpoint            ò   ‘        T   ’               gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma           ƒ     `                �   2           2      ‚               w   E           Œ   {     `       ports                        +       port@0          ƒ       endpoint            ò   ’        T   ‘         port@1          ƒ      endpoint            ò   “        T                   dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither         ƒ     p                �   2           2      ƒ               w   E           Œ   {     p       ports                        +       port@0          ƒ       endpoint            ò   ”        T   ¡         port@1          ƒ      endpoint            ò   •        T   �               dsi@1c008000              mediatek,mt8188-dsi         ƒ     €                �   2      2      –        –engine digital hs           2      „               ç   –        ôdphy            w   E           …   2           Ookay                         +       panel@0         ƒ               +               Vdefault         d   —           ˜           ™        %   š        1   ›        ?          Ookay              boe,nv110wum-l60 himax,hx83102     port       endpoint            ò   œ        T   ž            ports                        +       port@0          ƒ       endpoint            ò   �        T   •         port@1          ƒ      endpoint            ò   ž        T   œ               dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc           ƒ     �                �   2   
        2      …               w   E           Œ   {     �          dsi@1c012000              mediatek,mt8188-dsi         ƒ                     �   2   	   2      Ÿ        –engine digital hs           2      Ž               ç   Ÿ        ôdphy            w   E           …   2   	      	  Odisabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ƒ    @                �   2      <           –merge merge_async           2      �               w   E           Œ   {     @          dp-intf@1c015000              mediatek,mt8188-dp-intf         ƒ    P                �   2       2      -           –pixel engine pll            2      ‘               w   E         	  Odisabled          mutex@1c016000            mediatek,mt8188-disp-mutex          ƒ    `                �   2           2      ’               w   E           Œ   {     `            ¤  >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask         ƒ                     �   2           2      •               w   E           Œ   {             ports                        +       port@0          ƒ       endpoint            ò            T   “         port@1          ƒ      endpoint            ò   ¡        T   ”               syscon@1c01d000           mediatek,mt8188-vdosys0 syscon          ƒ    Ð                á           »           ë   {               Œ   {     Ð            T   2   port                         +       endpoint@0          ƒ            ò   ¢        T   ˆ            smi@1c022000              mediatek,mt8188-smi-larb            ƒ                     �   2      2           –apb smi         w   E           Å            Ö   ‡        T   £      smi@1c023000              mediatek,mt8188-smi-larb            ƒ    0                �   2      2           –apb smi         w   E           Å           Ö           T   €      smi@1c024000              mediatek,mt8188-smi-common-vdo          ƒ    @                �   2      2           –apb smi         w   E           T   ‡      iommu@1c028000            mediatek,mt8188-iommu-vdo           ƒ    €       P         �   2           –bclk            2      ¡               w   E           P           ã   £   ¤   ¥   ¦   §        T   †      syscon@1c100000           mediatek,mt8188-vdosys1 syscon          ƒ                     á           »           ë   {              Œ   {                  T   <   port                         +       endpoint@1          ƒ           ò   ¨        T   ­            mutex@1c101000            mediatek,mt8188-disp-mutex          ƒ                    �   <           2      î               w   E           Œ   {                 ¤  Å      smi@1c102000              mediatek,mt8188-smi-larb            ƒ                     �   <       <            –apb smi         w   E           Å           Ö   ‡        T   ¤      smi@1c103000              mediatek,mt8188-smi-larb            ƒ    0                �   <      <           –apb smi         w   E           Å           Ö           T   �      rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ƒ    @                �   <           2      ï               …   †   @        w   E           z           Œ   {     @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ƒ    P                �   <           2      ð               …   |   `        w   E           z           Œ   {     P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ƒ    `                �   <           2      ñ               …   †   A        w   E           z           Œ   {     `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ƒ    p                �   <           2      ò               …   |   a        w   E           z           Œ   {     p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ƒ    €                �   <           2      ó               …   †   B        w   E           z           Œ   {     €          rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ƒ    �                �   <           2      ô               …   |   b        w   E           z           Œ   {     �          rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ƒ                     �   <           2      õ               …   †   C        w   E           z           Œ   {                rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ƒ    °                �   <           2      ö               …   |   c        w   E           z           Œ   {     °          merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ƒ    À                �   <   	   <           –merge merge_async           2      ÷               w   E           …   <           Œ   {     À             H      merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ƒ    Ð                �   <   
   <           –merge merge_async           2      ø               w   E           …   <           Œ   {     Ð             H      merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ƒ    à                �   <      <           –merge merge_async           2      ù               w   E           …   <           Œ   {     à             H      merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ƒ    ð                �   <      <           –merge merge_async           2      ú               w   E           …   <           Œ   {     ð             H      merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ƒ                     �   <      <           –merge merge_async           2      û               w   E           …   <           Œ   {                   \   ports                        +       port@0                       +            ƒ       endpoint@1          ƒ           ò   ©        T   ®         port@1                       +            ƒ      endpoint@1          ƒ           ò   ª        T   «               dpi@1c112000          (    mediatek,mt8188-dpi mediatek,mt8195-dpi         ƒ                     �   <   8   <      <   =        –pixel engine pll            2                     w   E           …   <         	  Odisabled       ports                        +       port@0          ƒ       endpoint             port@1          ƒ      endpoint                   dp-intf@1c113000              mediatek,mt8188-dp-intf         ƒ    0                �   <   :   <      -           –pixel engine pll            2                     w   E           Ookay       ports                        +       port@0                       +            ƒ       endpoint@1          ƒ           ò   «        T   ª         port@1                       +            ƒ      endpoint@1          ƒ           ò   ¬        T   ²               ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p  ƒ    @            P            p            �                         °            À              4  Èmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h  �   <   0   <   +   <   .   <   ,   <   /   <   -   <   <   <   1   <   2   <   3   <   4   <   5   .         ƒ  –mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          2      6               …   |   d   |   e        w   E         (  …   <   1   <   2   <   3   <   4   <   5      p  Œ   {     @       {     P       {     p       {     �       {             {     °       {     À       ports                        +       port@0                       +            ƒ       endpoint@1          ƒ           ò   ­        T   ¨         port@1                       +            ƒ      endpoint@1          ƒ           ò   ®        T   ©               padding@1c11d000              mediatek,mt8188-disp-padding            ƒ    Ð                �   <           w   E           Œ   {     Ð          padding@1c11e000              mediatek,mt8188-disp-padding            ƒ    à                �   <            w   E           Œ   {     à          padding@1c11f000              mediatek,mt8188-disp-padding            ƒ    ð                �   <   !        w   E           Œ   {     ð          padding@1c120000              mediatek,mt8188-disp-padding            ƒ                     �   <   "        w   E           Œ   {                padding@1c121000              mediatek,mt8188-disp-padding            ƒ                    �   <   #        w   E           Œ   {               padding@1c122000              mediatek,mt8188-disp-padding            ƒ                     �   <   $        w   E           Œ   {                padding@1c123000              mediatek,mt8188-disp-padding            ƒ    0                �   <   %        w   E           Œ   {     0          padding@1c124000              mediatek,mt8188-disp-padding            ƒ    @                �   <   &        w   E           Œ   {     @          hdmi@1c300000             mediatek,mt8188-hdmi-tx         Ì           ƒ    0                  �   .   @   .   >   .   ?   3   .        –bus hdcp hdcp24m hdmi-split         )   .   >        9   .   s        2      ®               w   E   	        ç   ¯        ôhdmi          	  Odisabled       i2c       2    mediatek,mt8188-hdmi-ddc mediatek,mt8195-hdmi-ddc           �   D      ports                        +       port@0          ƒ       endpoint             port@1          ƒ      endpoint                   edp-tx@1c500000           mediatek,mt8188-edp-tx          ƒ    P        €         2      ¤               ©   °        µdp_calibration_data         w   E           s  ¤      	  Odisabled          dp-tx@1c600000            mediatek,mt8188-dp-tx           ƒ    `        €         2      Ê               ©   °        µdp_calibration_data         w   E           s          Ookay            Vdefault         d   ±        Ì            T      ports                        +       port@0          ƒ       endpoint            ò   ²        T   ¬         port@1          ƒ      endpoint            „                               backlight-lcd0            pwm-backlight           �      ÿ        ¡  @           +               º  ÿ        Ñ   ³        Þ   ´     ¡         T   ˜      chosen          ãserial0:115200n8          dmic-codec            dmic-codec          ï           ü   d      memory@40000000         wmemory          ƒ    @                 regulator-pp1800-ldo-z1           regulator-fixed         >pp1800_ldo_z1            ™                 M w@        e w@           k      regulator-pp3300-s3           regulator-fixed       
  >pp3300_s3            ™                 M 2Z         e 2Z            k        T   Y      regulator-pp3300-z1           regulator-fixed       
  >pp3300_z1            ™                 M 2Z         e 2Z            ³        T   k      regulator-pp3300-wlan             regulator-fixed         >pp3300_wlan          ™        M 2Z         e 2Z          )        <   +               d   µ        Vdefault            k      regulator-pp4200-s5           regulator-fixed       
  >pp4200_s5            ™                 M @@        e @@           ³      regulator-pp5000-z1           regulator-fixed       
  >pp5000_z1            ™                 M LK@        e LK@           ³        T   ¶      regulator-pp5000-usb-vbus             regulator-fixed         >pp5000_usb_vbus         M LK@        e LK@         )        <   +   –               ¶        T   Z      regulator-ppvar-sys           regulator-fixed       
  >ppvar_sys            ™                 T   ³      regulator-ppvar-mipi-disp-avdd            regulator-fixed         >ppvar_mipi_disp_avdd             )        <   +               Vdefault         d   ·           ¶        T   ™      regulator-ppvar-mipi-disp-avee            regulator-fixed         >ppvar_mipi_disp_avee            }  '         )        <   +               Vdefault         d   ¸           ¶        T   š      reserved-memory                      +            T   memory@50000000           shared-dma-pool         ƒ    P        €           A        T   C      memory@55000000           shared-dma-pool         ƒ    U       @        memory@60000000           shared-dma-pool         ƒ    `        ð           A        T   K      memory@60f00000           shared-dma-pool         ƒ    `ð                  A        T   G      memory@61000000           shared-dma-pool         ƒ    a                   A        T   J            	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 dsi0 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 mmc0 serial0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status pinctrl-names pinctrl-0 pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 mediatek,adsp audio-routing link-name dai-format mediatek,clk-provider sound-dai polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux bias-pull-down input-enable drive-strength output-high bias-disable output-low bias-pull-up #power-domain-cells domain-supply clocks clock-names mediatek,infracfg mediatek,disable-extrst #sound-dai-cells interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread regulator-microvolt-offset assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells memory-region power-domains resets reset-names mediatek,topckgen mediatek,etdm-out1-cowork-source mediatek,etdm-in2-cowork-source mboxes mbox-names spi-max-frequency google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells phys wakeup-source mediatek,syscon-wakeup dr_mode vusb33-supply vbus-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay mmc-hs200-1_8v mmc-hs400-1_8v mmc-hs400-enhanced-strobe no-sd no-sdio non-removable supports-cqe vmmc-supply vqmmc-supply clock-div AVDD-supply DBVDD-supply LDO1-IN-supply MICVDD-supply realtek,jd-src sound-name-prefix reset-gpios usb2-lpm-disable bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names #phy-cells mediatek,ibias mediatek,ibias_up drive-strength-microamp bits operating-points-v2 power-domain-names mali-supply #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs remote-endpoint enable-gpios backlight avdd-supply avee-supply pp1800-supply rotation mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz data-lanes brightness-levels default-brightness-level num-interpolated-steps power-supply pwms stdout-path num-channels wakeup-delay-ms regulator-boot-on vin-supply enable-active-high gpio no-map 