Ðþí w2   8 i4   (            þ hü                             8    mediatek,mt8395-evk-ufs mediatek,mt8395 mediatek,mt8195                                  +         !   7MediaTek Genio 1200 EVK-P1V2-UFS       aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/mailbox@10320000            Y/soc/mailbox@10330000            ^/soc/hdmi-tx@1c300000            d/soc/hdr-engine@1c114000             k/soc/mutex@1c016000          r/soc/mutex@1c101000          y/soc/vpp-merge@1c10c000          €/soc/vpp-merge@1c10d000          ‡/soc/vpp-merge@1c10e000          Ž/soc/vpp-merge@1c10f000          •/soc/vpp-merge@1c110000          œ/soc/dma-controller@1c104000             §/soc/dma-controller@1c105000             ²/soc/dma-controller@1c106000             ½/soc/dma-controller@1c107000             È/soc/dma-controller@1c108000             Ó/soc/dma-controller@1c109000             Þ/soc/dma-controller@1c10a000             é/soc/dma-controller@1c10b000             ô/soc/serial@11001100             ü/soc/ethernet@11021000        cpus                         +       cpu@0           cpu           arm,cortex-a55                      psci            $               8ec3@        H  4        [              k  €         x   @        Š   €        —  €         ¤   @        ¶   €        Ã           Ô           ã           î         cpu@100         cpu           arm,cortex-a55                     psci            $               8ec3@        H  4        [              k  €         x   @        Š   €        —  €         ¤   @        ¶   €        Ã           Ô           ã           î         cpu@200         cpu           arm,cortex-a55                     psci            $               8ec3@        H  4        [              k  €         x   @        Š   €        —  €         ¤   @        ¶   €        Ã           Ô           ã           î         cpu@300         cpu           arm,cortex-a55                     psci            $               8ec3@        H  4        [              k  €         x   @        Š   €        —  €         ¤   @        ¶   €        Ã           Ô           ã           î         cpu@400         cpu           arm,cortex-a78                     psci            $              8�fÔÀ        H           [              k           x   @        Š           —           ¤   @        ¶           Ã   	        Ô           ã   
        î         cpu@500         cpu           arm,cortex-a78                     psci            $              8�fÔÀ        H           [              k           x   @        Š           —           ¤   @        ¶           Ã   	        Ô           ã   
        î         cpu@600         cpu           arm,cortex-a78                     psci            $              8�fÔÀ        H           [              k           x   @        Š           —           ¤   @        ¶           Ã   	        Ô           ã   
        î         cpu@700         cpu           arm,cortex-a78                     psci            $              8�fÔÀ        H           [              k           x   @        Š           —           ¤   @        ¶           Ã   	        Ô           ã   
        î         cpu-map    cluster0       core0           ö         core1           ö         core2           ö         core3           ö         core4           ö         core5           ö         core6           ö         core7           ö               idle-states         úpsci       cpu-retention-l           arm,idle-state                             /   2        @   _        P  D        î         cpu-retention-b           arm,idle-state                             /   -        @   Œ        P  ä        î         cpu-off-l             arm,idle-state                            /   7        @   ›        P  H        î         cpu-off-b             arm,idle-state                            /   2        @   È        P  è        î            l2-cache0             cache           a           m           z   @        Œ           Ã            m        î         l2-cache1             cache           a           m           z   @        Œ           Ã            m        î   	      l3-cache              cache           a           m            z   @        Œ            m        î            dsu-pmu           arm,dsu-pmu         {                       †                                ‹fail          dmic-codec            dmic-codec          ’           Ÿ   È      mt8195-sound            ¯           ‹okay              mediatek,mt8195_mt6359           7mt8395-evk          Ádefault         Ï         ,  ÙHeadphone Headphone L Headphone Headphone R         ç      headphone-dai-link        
  õDL_SRC_BE      codec           ÿ                hdmi-dai-link           õETDM3_OUT_BE       codec           ÿ                   fixed-factor-clock-13m            fixed-factor-clock          	                                  '           2clk13m          î   0      oscillator-26m            fixed-clock         	            8Œº€        2clk26m          î         oscillator-32k            fixed-clock         	            8  €         2clk32k        performance-controller@11bc10             mediatek,cpufreq-hw               ¼            ½0               E           î         opp-table-gpu             operating-points-v2          _        î   ƒ   opp-390000000           j    >í€        q 	‰h      opp-410000000           j    p€        q 	¡Ò      opp-431000000           j    °‰À        q 	¡Ò      opp-473000000           j    1h@        q 	º<      opp-515000000           j    ²FÀ        q 	º<      opp-556000000           j    !#ã         q 	Ò¦      opp-598000000           j    #¤Á€        q 	ë      opp-640000000           j    &%          q 	ë      opp-670000000           j    'ïc€        q 
ä      opp-700000000           j    )¹'         q 
L¸      opp-730000000           j    +‚ê€        q 
}Œ      opp-760000000           j    -L®         q 
®`      opp-790000000           j    /q€        q 
ß4      opp-820000000           j    0à5         q       opp-850000000           j    2©ø€        q @Ü      opp-880000000           j    4s¼         q q°         pmu-a55           arm,cortex-a55-pmu                      {                  pmu-a78           arm,cortex-a78-pmu                      {                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  {                                             
             soc                      +             simple-bus                   †                          interrupt-controller@c000000              arm,gic-v3          ‘           ¢                        ¹                                             {      	               î      ppi-partitions     interrupt-partition-0           Î                    î         interrupt-partition-1           Î                    î               syscon@10000000            mediatek,mt8195-topckgen syscon                               	           î         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                               	           ×           î          syscon@10003000           mediatek,mt8195-pericfg syscon               0                	           î   L      pinctrl@10005000              mediatek,mt8195-pinctrl       €       P            Ñ             Ó             Ô             â             ë             ô              °              B  äiocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            î        þ           
              �         ¹        {       ë               ‘           î      audio-default-pins          î      pins-cmd-dat          4    =  >  A  B  C  D  E  F  G  H  I  J  K         disp-pwm1-default-pins     pins1             h         edp-panel-12v-en-pins           î   è   pins1             `                   edp-panel-3v3-en-pins           î   ç   pins1                                eth-default-pins            î   H   pins-cc           U  V  W  X        )         pins-mdio             Y  Z         8      pins-power            [   \                pins-rxd              Q  R  S  T      pins-txd              M  N  O  P        )            eth-sleep-pins          î   I   pins-cc           U   V   W   X       pins-mdio             Y   Z          E         S      pins-rxd              Q   R   S   T       pins-txd              M   N   O   P          gpio-keys-pins     pins              j          `         8         hdmi-vreg-pins          î   l   pins-pwr                       S         hdmi-pins           î   Õ   pins-hotplug                        m      pins-ddc              "  #        )   
      pins-cec              !         S         i2c0-pins           î   n   pins                	        `   Ï        |  è         i2c1-pins           î   o   pins              
          `   Ï        |  è         i2c2-pins           î   r   pins                        `   Ï        )            i2c6-pins           î   f   pins                         `         mmc0-default-pins           î   Q   pins-clk              z        )           m   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y         8        )           `   e      pins-rst              x        )           `   e         mmc0-uhs-pins           î   R   pins-clk              z        )           m   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y         8        )           `   e      pins-ds                   )           m   f      pins-rst              x        )           `   e         mmc1-default-pins           î   U   pins-clk              o        )           m   f      pins-cmd-dat              n  p  q  r  s         8        )           `   e         mmc1-uhs-pins           î   V   pins-clk              o        )           m   f      pins-cmd-dat              n  p  q  r  s         8        )           `   e         mt6360-pins         î   g   pins                 €          8         `         dsi0-vreg-en-pins           î   é   pins-pwr-en           /          ”         panel-default-pins          î   º   pins-rst              l                pins-en           0          ”         pcie0-default-pins          î   a   pins                           `         pcie0-idle-pins         î   b   pins                        S         ”         pcie1-default-pins          î   d   pins                           `         disp-pwm0-pins          î   ?   pins-disp-pwm             a         spi1-pins           î   @   pins              ˆ  ‰  Š  ‹         S         spi-pins            î   C   pins              Œ  �  Ž  �         S         touch-pins          î   q   pins-irq              „          8         S      pins-reset            …                   u3-p0-vbus-default-pins         î   M   pins-vbus             ?         8         uart0-pins          î   :   pins              b  c         uart1-pins          î   ;   pins              d  e  f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8195-power-controller                         +            Ÿ           î   3   power-domain@8                                  +            Ÿ           ³      power-domain@9             	                            Ámfg alt         Í                         +            Ÿ           ³   !   power-domain@10            
        Ÿ          power-domain@11                    Ÿ          power-domain@12                    Ÿ          power-domain@13                    Ÿ          power-domain@14                    Ÿ                power-domain@15                  Ø                          	      @      A      K      à   "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "           Ávppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           Í                         +            Ÿ      power-domain@16                  8        â   #   $   #   %   #   &   #   '   #   (   #   )      D  Ávdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         Í                         +            Ÿ      power-domain@17                          á   $      $           Ávppsys1 vppsys1-0 vppsys1-1         Í            Ÿ          power-domain@22                        %      %      %      %         $  Áwepsys-0 wepsys-1 wepsys-2 wepsys-3         Í            Ÿ          power-domain@23                       &            Ávdec0-0         Í                         +            Ÿ       power-domain@24                       '            Ávdec1-0         Í            Ÿ          power-domain@25                       (            Ávdec2-0         Í            Ÿ             power-domain@26                       )            Ávenc0-larb          Í                         +            Ÿ       power-domain@27                       *            Ávenc1-larb          Í            Ÿ             power-domain@18                           ã   +       +      +         &  Ávdosys1 vdosys1-0 vdosys1-1 vdosys1-2           Í                         +            Ÿ      power-domain@19                    Í            Ÿ          power-domain@20                    Í            Ÿ          power-domain@21                          Q        Áhdmi_tx         Ÿ             power-domain@28                       ,       ,   
        Áimg-0 img-1         Í                         +            Ÿ      power-domain@29                    Ÿ          power-domain@30                             ,      -           Áipe ipe-0 ipe-1         Í            Ÿ             power-domain@31                  (     .       .      .      .      .           Ácam-0 cam-1 cam-2 cam-3 cam-4           Í                         +            Ÿ      power-domain@32                     Ÿ          power-domain@33            !        Ÿ          power-domain@34            "        Ÿ                   power-domain@0                      Í            Ÿ          power-domain@1                     Í            Ÿ          power-domain@2                     Ÿ          power-domain@3                     Ÿ          power-domain@4                           5      7        Ácsi_rx_top csi_rx_top1          Ÿ          power-domain@5                        /           Áether           Ÿ          power-domain@6                           X      n        Áadsp adsp1                       +            Í            Ÿ      power-domain@7                            g      "      n       2        Áaudio audio1 audio2 audio3          Í            Ÿ                   watchdog@10007000             mediatek,mt8195-wdt          ß             p                ×           î   8      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                À                	           î         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer             p                {      	                  0      pwrap@10024000            mediatek,mt8195-pwrap syscon                @                äpwrap           {       ó                                    	  Áspi wrap            ÷      $              Ë   pmic              mediatek,mt6359          ¹        ‘                      /      Þ           î      adc           mediatek,mt6359-auxadc          C         audio-codec           mediatek,mt6359-codec           U           i           }         regulators            mediatek,mt6359-regulator      buck_vs1            ‘vs1           5         ¸ !‘À        Ð             ì      buck_vgpu11         ‘vgpu11            €        ¸ 7           ˆ        Ð   È                           ì      buck_vmodem         ‘vmodem            €        ¸ Èà           *        Ð   È      buck_vpu            ‘vpu           €        ¸ 7           ˆ        Ð   È                           ì      buck_vcore          ‘vcore             €        ¸ Ö            ˆ        Ð   È                           ì        î         buck_vs2            ‘vs2           5         ¸ j         Ð             ì      buck_vpa            ‘vpa           ¡         ¸ 7±Ð        Ð  ,      buck_vproc2         ‘vproc2            €        ¸ 7           L        Ð   È                        buck_vproc1         ‘vproc1            €        ¸ 7           L        Ð   È                        buck_vcore_sshub            ‘vcore_sshub           €        ¸ 7      buck_vgpu11_sshub           ‘vgpu11_sshub              €        ¸ 7      ldo_vaud18          ‘vaud18            w@        ¸ w@        Ð   ð         ì      ldo_vsim1           ‘vsim1             ð         ¸ /M`      ldo_vibr            ‘vibr              O€        ¸ 2Z         î   s      ldo_vrf12           ‘vrf12             Èà        ¸ Ö          ì      ldo_vusb            ‘vusb              -ÆÀ        ¸ -ÆÀ        Ð  À         ì        î   N      ldo_vsram_proc2         ‘vsram_proc2           ¡         ¸ ½¶           L        Ð   ð         ì      ldo_vio18           ‘vio18             ð         ¸ ýà        Ð  À         ì      ldo_vcamio          ‘vcamio            ð         ¸ ýà         ì      ldo_vcn18           ‘vcn18             w@        ¸ w@        Ð   ð      ldo_vfe28           ‘vfe28             *¹€        ¸ *¹€        Ð   x      ldo_vcn13           ‘vcn13             »         ¸ Ö       ldo_vcn33_1_bt          ‘vcn33_1_bt            *¹€        ¸ 5gà      ldo_vcn33_1_wifi            ‘vcn33_1_wifi              *¹€        ¸ 5gà      ldo_vaux18          ‘vaux18            w@        ¸ w@        Ð   ð         ì      ldo_vsram_others            ‘vsram_others              q°        ¸ q°           ˆ        Ð   ð        î   !      ldo_vefuse          ‘vefuse            ð         ¸ „€      ldo_vxo22           ‘vxo22             w@        ¸ !‘À         ì      ldo_vrfck           ‘vrfck             ã`        ¸ ð       ldo_vrfck_1         ‘vrfck             ëÀ        ¸ j       ldo_vbif28          ‘vbif28            *¹€        ¸ *¹€        Ð   ð      ldo_vio28           ‘vio28             *¹€        ¸ 2Z          ì      ldo_vemc            ‘vemc              ,@         ¸ 2Z       ldo_vemc_1          ‘vemc              &%         ¸ 2Z         î   S      ldo_vcn33_2_bt          ‘vcn33_2_bt            2Z         ¸ 2Z         î   B      ldo_vcn33_2_wifi            ‘vcn33_2_wifi              *¹€        ¸ 5gà      ldo_va12            ‘va12              O€        ¸ Ö          ì      ldo_va09            ‘va09              5         ¸ O€      ldo_vrf18           ‘vrf18             ð         ¸ žP      ldo_vsram_md          	  ‘vsram_md              ¡         ¸ ½¶           *        Ð   ð      ldo_vufs            ‘vufs              ð         ¸ ýà        î   T      ldo_vm18            ‘vm18              ð         ¸ ýà         ì      ldo_vbbck           ‘vbbck             Èà        ¸ O€         ì      ldo_vsram_proc1         ‘vsram_proc1           ¡         ¸ ½¶           L        Ð   ð         ì      ldo_vsim2           ‘vsim2             ð         ¸ /M`      ldo_vsram_others_sshub          ‘vsram_others_sshub            ¡         ¸ ½¶         rtc           mediatek,mt6358-rtc       keys              mediatek,mt6359-keys            -           F       power-key           Y   t         h      home            Y   f               spmi@10027000             mediatek,mt8195-spmi                 p            �                äpmif spmimst                                 E      (  Ápmif_sys_ck pmif_tmr_ck spmimst_clk_mux         ÷      $              Ë                     +       pmic@6            mediatek,mt6315-regulator                     regulators     vbuck1          ‘Vbcpu             “à        ¸ 7        Ð                              ì        î   
            pmic@7            mediatek,mt6315-regulator                     regulators     vbuck1          ‘Vgpu              TÐ        ¸ 8        Ð                             î                  infra-iommu@10315000              mediatek,mt8195-iommu-infra             1P       P       P  {                                                                         v           î   ^      mailbox@10320000              mediatek,mt8195-gce             2        @         {       â               ƒ                          î   ¦      mailbox@10330000              mediatek,mt8195-gce             3        @         {       ä               ƒ                          î   „      scp@10500000              mediatek,mt8195-scp       0      P             r             p        €         äsram cfg l1tcm          {      Î               ‹okay            �   1        �mediatek/mt8195/scp.img         î   …      clock-controller@10720000             mediatek,mt8195-scp_adsp                r                 	           î   2      dsp@10803000              mediatek,mt8195-dsp              €0            „               	  äcfg sram          ,        X         n      Š   2          #      K  Áadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          «   3           ¹rx tx           Ä   4   5        ‹okay            �   6   7        î         mailbox@10816000              mediatek,mt8195-adsp-mbox           ƒ                �`                {      ¾               î   4      mailbox@10817000              mediatek,mt8195-adsp-mbox           ƒ                �p                {      ¿               î   5      mt8195-afe-pcm@10890000           mediatek,mt8195-audio               ‰                 Ë           «   3           {      6               Ý   8         	  äaudiosys          ”                       Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d       2   2          ó  Áclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          ‹okay            �   9        î         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {       �                               	  Ábaud bus            ‹okay            Ï   :        Ádefault       serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {       Ž                               	  Ábaud bus            ‹okay            Ï   ;        Ádefault       serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {       �                               	  Ábaud bus          	  ‹disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {      Ó                               	  Ábaud bus          	  ‹disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {      Ô                               	  Ábaud bus          	  ‹disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                {      Õ                               	  Ábaud bus          	  ‹disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                                Ámain            C         	  ‹disabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                0                	           î   /      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  {       ¿                     ™                     Áparent-clk sel-clk spi-clk        	  ‹disabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap              °                {       ©                              Ý                ð   <   =      $  ülvts-calib-data-1 lvts-calib-data-2                    î   â      svs@1100bc00              mediatek,mt8195-svs              ¼                {       Ç                              Ámain            ð   >   <      (  üsvs-calibration-data t-calibration-data         Ý               äsvs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                à                {       Ë               «   3           #                 *       0        Ámain mm         ‹okay            Ádefault         Ï   ?        î   å      pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                ð                {                     #                 +       N        Ámain mm       	  ‹disabled            î   æ      spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 {       À                     ™             3        Áparent-clk sel-clk spi-clk          ‹okay            Ï   @        Ádefault         .            B      @      can@0             microchip,mcp2518fd                        A        K1-         /                 ]   B        h   B         spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 {       Á                     ™             4        Áparent-clk sel-clk spi-clk          ‹okay            Ï   C        Ádefault         .          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                0                {       Â                     ™             5        Áparent-clk sel-clk spi-clk        	  ‹disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                €                {       Ã                     ™             <        Áparent-clk sel-clk spi-clk        	  ‹disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                �                {       Ä                     ™             =        Áparent-clk sel-clk spi-clk        	  ‹disabled          spi@1101d000              mediatek,mt8195-spi-slave               Ð                {       Å                      R        Áspi         ÷                    ˜      	  ‹disabled          spi@1101e000              mediatek,mt8195-spi-slave               à                {       Æ                      S        Áspi         ÷                    ˜      	  ‹disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                      @         {      Ì               wmacirq        .  Áaxi apb mac_main ptp_ref rmii_internal mac_cg         0     /       /         R      S      T   /           ÷      R      S      T              Â      Ã      Ä        «   3           ‡            ˜   D        ¨   E        »   F        Î           Ù           ä            ‹okay            ñrgmii-rxid          ú   G              ]                  '  '        *  î         ?        Ádefault sleep           Ï   H        P   I   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916                       î   G         stmmac-axi-config           Z           j           z                                 î   D      rx-queues-config            „            š        î   E   queue0           «        ¾          queue1           «        ¾          queue2           «        ¾          queue3           «        ¾             tx-queues-config            Ö            ì        î   F   queue0          þ            «        	
          queue1          þ            «        	
         queue2          þ            «        	
         queue3          þ            «        	
               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                       -ÿ     >              	  ämac ippc                                 ?                      +           {       €                      /      í       B        Ásys_ck ref_ck mcu_ck            	   J      K            h        	   L      g        ‹okay            	4otg         Ádefault         Ï   M         	<        	L   N   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 ämac         {       �               ÷      ,      -              –      –      $         /      í                B      $  Ásys_ck ref_ck mcu_ck dma_ck xhci_ck         ‹okay          ports                        +       port@0                 endpoint            	Z   O        î   i         port@1                endpoint            	Z   P        î   j               mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              #             õ                 {       ƒ                                           Ásource hclk source_cg         	  ‹disabled            Ádefault state_uhs           Ï   Q        P   R        	j           OëÂ          	t         	†         	•         	¤         	µ         	½        	Ã L        	Ò   S        	Þ   T         	ë      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              $             Ç                 {       ‡                                   $        Ásource hclk source_cg           ÷                    ¿        ‹okay            Ádefault state_uhs           Ï   U        P   V        	j           OëÂ          	ù         

         
         
%         	µ        	Ò   W        	Þ   X         	ë      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              %             æ                 {       ˆ                                    I        Ásource hclk source_cg           ÷                     ¿      	  ‹disabled          ufshci@11270000           mediatek,mt8195-ufshci              '        #         {       ‰               	   Y      @         ?       @       A       6       7       8       Z       ]      X  Áufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  
,                                                                         
:        ‹okay            
S   S        
^   T      thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                '€                {       ª                              Ý               ð   <   =      $  ülvts-calib-data-1 lvts-calib-data-2                    î   Ù      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci               )             )>              	  ämac ippc            {                     	   Z      [           ÷      .      /              –      –      $     /         ï            /         $  Ásys_ck ref_ck mcu_ck dma_ck xhci_ck         	   L      h         h        ‹okay            	L   N      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               *       -ÿ    *>              	  ämac ippc                        *        ?                      +           {                     ÷      0              –           /         ñ   /           Ásys_ck ref_ck mcu_ck            	   \            h        	   L      i        ‹okay            	L   N   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 ämac         {                     ÷      1              –           /           Ásys_ck          ‹okay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               +       -ÿ    +>              	  ämac ippc                        +        ?                      +           {                     ÷      2              –           /         ó   /   	        Ásys_ck ref_ck mcu_ck            	   ]            h        	   L      j        ‹okay            	L   N   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 ämac         {                     ÷      3              –           /   	        Ásys_ck          ‹okay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +               /        @       	  äpcie-mac            {                     
k       ÿ      8  �                           ‚                       à          
u       ^              
          0         V       #       &       +       K   /         /  Ápl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ÷      G                      	   _      	  
Žpcie-phy            «   3            ‘           
˜                     `  
«                  `                      `                     `                     `           ‹okay            Ádefault idle            Ï   a        P   b   interrupt-controller             ¹                     ‘           î   `         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +               /€       @       	  äpcie-mac            {                     
k       ÿ      8  �       $       $           ‚       $       $       à          
u       ^              
          (         W          X          Q   /         /  Ápl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ÷      H                      	   [         	  
Žpcie-phy            «   3           ‘           
˜                     `  
«                  c                      c                     c                     c         	  ‹disabled            Ádefault         Ï   d   interrupt-controller             ¹                     ‘           î   c         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor             2À                {      9                     o   /      /           Áspi sf axi                       +          	  ‹disabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                Á                              +      usb3-tx-imp@184,1             „           
¹               î   z      usb3-rx-imp@184,2             „           
¹              î   y      usb3-intr@185             …           
¹              î   x      usb3-tx-imp@186,1             †           
¹               î   w      usb3-rx-imp@186,2             †           
¹              î   v      usb3-intr@187             ‡           
¹              î   u      usb2-intr-p0@188,1            ˆ           
¹             usb2-intr-p1@188,2            ˆ           
¹            usb2-intr-p2@189,1            ‰           
¹            usb2-intr-p3@189,2            ‰           
¹            pciephy-rx-ln1@190,1              �           
¹               î   �      pciephy-tx-ln1-nmos@190,2             �           
¹              î   €      pciephy-tx-ln1-pmos@191,1             ‘           
¹               î         pciephy-rx-ln0@191,2              ‘           
¹              î   ~      pciephy-tx-ln0-nmos@192,1             ’           
¹               î   }      pciephy-tx-ln0-pmos@192,2             ’           
¹              î   |      pciephy-glb-intr@193              “           
¹               î   {      dp-data@1ac           ¬           î   Ø      lvts1-calib@1bc           ¼           î   <      lvts2-calib@1d0           Ð   8        î   =      svs-calib@580             €   d        î   >      socinfo-data1@7a0                          t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   Ä             ‹okay       usb-phy@0                                ò        Áref         
¾           î   \         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   Å             ‹okay       usb-phy@0                                ô        Áref         
¾           î   ]         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             È                            2mipi_tx0_pll            	            
¾            ‹okay            î   ¶      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             É                            2mipi_tx1_pll            	            
¾          	  ‹disabled            î   ¾      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        {       š                             e           ;      	  Ámain dma                         +          	  ‹disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð            "        €        {       ›                             e          ;      	  Ámain dma                         +            ‹okay            8 €        Ï   f        Ádefault    pmic@34           mediatek,mt6360            4                    {   €           wIRQB             ¹        ‘           Ï   g   charger           mediatek,mt6360-chg         
É Ý@    usb-otg-vbus-regulator          ‘usb-otg-vbus              C…(        ¸ Xáè         regulator             mediatek,mt6360-regulator           
â   h   buck1         	  ‘emi_vdd2              “à        ¸ Ö                            ì      buck2         	  ‘emi_vddq              “à        ¸ Ö                            ì        î   h      ldo1          	  ‘tp1_p3v0              2Z         ¸ 2Z                         ì        î   p      ldo2            ‘panel1_p1v8           w@        ¸ w@                       î   ê      ldo3            ‘vmc_pmu           O€        ¸ 6î€                       î   X      ldo5          	  ‘vmch_pmu              )2à        ¸ 6î€                       î   W      ldo6            ‘mt6360_ldo1           ¡         ¸                        ldo7            ‘emi_vmddr_en              ¡         ¸                           ì         tcpc              mediatek,mt6360-tcpc            /                 wPD_IRQB    connector             usb-c-connector         
òUSB-C           
ødual             ˜–€        dual            sink            ."�d        :"�È        D   altmodes       displayport         Pÿ          U  F         ports                        +       port@0                 endpoint            	Z   i        î   O         port@1                endpoint            	Z   j        î   P         port@2                endpoint            	Z   k        î   t                        i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        {       œ                             e          ;      	  Ámain dma                         +          	  ‹disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s              Ð0                	           î   e      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy                Õð                       P                           Ápll_ref 26m pll1 pll2           2hdmi_txpll          	            
¾            Y   
        h           ‹okay            Ádefault         Ï   l        î   Ô      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             " €       €        {       �                             m           ;      	  Ámain dma                         +            ‹okay            8 €        Ï   n        Ádefault       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à            "        €        {       “                             m          ;      	  Ámain dma                         +            ‹okay            8 €        Ï   o        Ádefault    touchscreen@5d            goodix,gt9271              ]        /      „           z      „            „      …            �   p        Ádefault         Ï   q         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             "€       €        {       –                             m          ;      	  Ámain dma                         +            ‹okay            8 €        Ï   r        Ádefault    typec-mux@48              ite,it5205             H        
S   s         ž         ª        ‹okay       port       endpoint            	Z   t        î   k               i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à0            "€       €        {       ˜                             m          ;      	  Ámain dma                         +          	  ‹disabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à@            "        €        {       ™                             m          ;      	  Ámain dma                         +          	  ‹disabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w              àP                	           î   m      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   ã             «   3           ‹okay       usb-phy@0                                ð           Áref da_ref          
¾           î   Z      usb-phy@700                                   ð        Áref da_ref          ð   u   v   w        üintr rx_imp tx_imp          
¾            ½        î   [         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   ä             ‹okay       usb-phy@0                                î           Áref da_ref          
¾           î   J      usb-phy@700                                   î        Áref da_ref          ð   x   y   z        üintr rx_imp tx_imp          
¾           î   K         phy@11e80000              mediatek,mt8195-pcie-phy                è                 äsif         ð   {   |   }   ~      €   �      G  üglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          «   3           
¾            ‹okay            î   _      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy               ú        À                     
  Áunipro mp           
¾            ‹okay            î   Y      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                        @            ‚          0  {      �             Œ             ‹               wjob mmu gpu         Ñ   ƒ      (  «   3   
   3      3      3      3           åcore0 core1 core2 core3 core4           ‹okay            ø         clock-controller@13fbf000             mediatek,mt8195-mfgcfg              ûð                	           î   ‚      syscon@14000000           mediatek,mt8195-vppsys0 syscon                                	              „                   î   "      dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                   „                                0   …        «   3           =   †   €           "         <  Ä   „         „         „         „         „              D         display@14002000              mediatek,mt8195-mdp3-fg                                  „                      "          display@14003000              mediatek,mt8195-mdp3-stitch              0                   „      0               "         display@14004000              mediatek,mt8195-mdp3-hdr                 @                   „      @               "   "      display@14005000              mediatek,mt8195-mdp3-aal                 P                {      F                  „      P               "   
        «   3         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                   „      `                %           "         display@14007000              mediatek,mt8195-mdp3-tdshp               p                   „      p               "   #      display@14008000              mediatek,mt8195-mdp3-color               €                {      I                  „      €               "   $        «   3         display@14009000              mediatek,mt8195-mdp3-ovl                 �                {      J                  „      �               "   %        «   3           =   †   ‚      display@1400a000              mediatek,mt8195-mdp3-padding                                     „                      "           «   3         display@1400b000              mediatek,mt8195-mdp3-tcc                 °                   „      °               "         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              À                   „      À                +           "           =   †   ƒ        «   3           D         mutex@1400f000            mediatek,mt8195-vpp-mutex                ð                {      P                  „      ð               "           «   3         smi@14010000              mediatek,mt8195-smi-sub-common                                  "      "      "           Áapb smi gals0           O   ‡        «   3           î   ˆ      smi@14011000              mediatek,mt8195-smi-sub-common                                 "      "      "           Áapb smi gals0           O   ‡        «   3           î   ¥      smi@14012000              mediatek,mt8195-smi-common-vpp                                   "      "      "      "           Áapb smi gals0 gals1         «   3           î   ‡      larb@14013000             mediatek,mt8195-smi-larb                0                \           O   ˆ           "      "           Áapb smi         «   3           î   ‹      iommu@14018000            mediatek,mt8195-iommu-vpp               €              8  m   ‰   Š   ‹   Œ   �   Ž   �   �   ‘   ’   “   ”   •   –        {      R                  "           Ábclk            v           «   3           î   †      clock-controller@14e00000             mediatek,mt8195-wpesys              à                 	           î   %      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0             à                 	         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1             à0                	         larb@14e04000             mediatek,mt8195-smi-larb                à@                \           O   —           %      %           Áapb smi         «   3           î   Ã      larb@14e05000             mediatek,mt8195-smi-larb                àP                \           O   ‡           %      %      "           Áapb smi gals            «   3           î   �      syscon@14f00000           mediatek,mt8195-vppsys1 syscon              ð                 	              „   	               î   $      mutex@14f01000            mediatek,mt8195-vpp-mutex               ð                {      {                  „   	                 $   '        «   3         larb@14f02000             mediatek,mt8195-smi-larb                ð                 \           O   —           $      $      "           Áapb smi gals            «   3           î   Â      larb@14f03000             mediatek,mt8195-smi-larb                ð0                \           O   ˆ           $      $      "           Áapb smi gals            «   3           î   Œ      display@14f06000              mediatek,mt8195-mdp3-split              ð`                   „   	  `               $      $   +   $   ,        «   3         display@14f07000              mediatek,mt8195-mdp3-tcc                ðp                   „   	  p               $         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma               ð€                   „   	  €              „  ¨           $           =   ˜            «   3           D         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma               ð�                   „   	  �              …  ©           $   
        =   ˜   ¤        «   3           D         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma               ð                    „   	                 †  ª           $           =   †   À        «   3           D         display@14f0b000              mediatek,mt8195-mdp3-fg             ð°                   „   	  °               $   	      display@14f0c000              mediatek,mt8195-mdp3-fg             ðÀ                   „   	  À               $         display@14f0d000              mediatek,mt8195-mdp3-fg             ðÐ                   „   	  Ð               $         display@14f0e000              mediatek,mt8195-mdp3-hdr                ðà                   „   	  à               $         display@14f0f000              mediatek,mt8195-mdp3-hdr                ðð                   „   	  ð               $         display@14f10000              mediatek,mt8195-mdp3-hdr                ñ                    „   
                  $          display@14f11000              mediatek,mt8195-mdp3-aal                ñ                {      i                  „   
                 $           «   3         display@14f12000              mediatek,mt8195-mdp3-aal                ñ                 {      j                  „   
                  $           «   3         display@14f13000              mediatek,mt8195-mdp3-aal                ñ0                {      k                  „   
  0               $   !        «   3         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ@                   „   
  @              �  ¯           $         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñP                   „   
  P              ‘  °           $   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ`                   „   
  `              ’  ±           $   %      display@14f17000              mediatek,mt8195-mdp3-tdshp              ñp                   „   
  p               $         display@14f18000              mediatek,mt8195-mdp3-tdshp              ñ€                   „   
  €               $   (      display@14f19000              mediatek,mt8195-mdp3-tdshp              ñ�                   „   
  �               $   )      display@14f1a000              mediatek,mt8195-mdp3-merge              ñ                    „   
                  $           «   3         display@14f1b000              mediatek,mt8195-mdp3-merge              ñ°                   „   
  °               $           «   3         display@14f1c000              mediatek,mt8195-mdp3-color              ñÀ                {      t                  „   
  À               $           «   3         display@14f1d000              mediatek,mt8195-mdp3-color              ñÐ                   „   
  Ð            {      u                  $           «   3         display@14f1e000              mediatek,mt8195-mdp3-color              ñà                {      v                  „   
  à               $           «   3         display@14f1f000              mediatek,mt8195-mdp3-ovl                ñð                {      w                  „   
  ð               $            «   3           =   ˜   ¢      display@14f20000              mediatek,mt8195-mdp3-padding                ò                    „                     $           «   3         display@14f21000              mediatek,mt8195-mdp3-padding                ò                   „                    $           «   3         display@14f22000              mediatek,mt8195-mdp3-padding                ò                    „                     $           «   3         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò0                   „     0              Ÿ  «           $           =   ˜   £        «   3           D         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò@                   „     @                 ¬           $           =   ˜   ¦        «   3           D         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             òP                   „     P              ¡  ­           $           =   †   Â        «   3           D         clock-controller@15000000             mediatek,mt8195-imgsys                                	           î   ,      larb@15001000             mediatek,mt8195-smi-larb                                 \   	        O   ™           ,       ,       ,   
        Áapb smi gals            «   3           î   Ä      smi@15002000              mediatek,mt8195-smi-sub-common                                   ,      ,      "           Áapb smi gals0           O   ‡        «   3           î   œ      smi@15003000              mediatek,mt8195-smi-sub-common               0                   ,       ,       ,   
        Áapb smi gals0           O   —        «   3           î   ™      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                              	           î   š      larb@15120000             mediatek,mt8195-smi-larb                                 \   
        O   ™           ,      š            Áapb smi         «   3           î   Å      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                               	         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe             "                 	           î   ›      larb@15230000             mediatek,mt8195-smi-larb                #                 \           O   ™           ,      ›            Áapb smi         «   3           î   Æ      clock-controller@15330000             mediatek,mt8195-ipesys              3                 	           î   -      larb@15340000             mediatek,mt8195-smi-larb                4                 \           O   œ           -      -           Áapb smi         «   3           î   Ž      clock-controller@16000000             mediatek,mt8195-camsys                                	           î   .      larb@16001000             mediatek,mt8195-smi-larb                                 \           O   �           .       .       .           Áapb smi gals            «   3           î   Ç      larb@16002000             mediatek,mt8195-smi-larb                                  \           O   ž           .      .           Áapb smi         «   3           î   �      smi@16004000              mediatek,mt8195-smi-sub-common               @                   .       .       .           Áapb smi gals0           O   —        «   3           î   �      smi@16005000              mediatek,mt8195-smi-sub-common               P                   .      .      "           Áapb smi gals0           O   ‡        «   3           î   ž      larb@16012000             mediatek,mt8195-smi-larb                                 \           O   ž           Ÿ       Ÿ            Áapb smi         «   3            î   �      larb@16013000             mediatek,mt8195-smi-larb                0                \           O   �                                Áapb smi         «   3            î   È      larb@16014000             mediatek,mt8195-smi-larb                @                \           O   ž           ¡       ¡            Áapb smi         «   3   !        î   –      larb@16015000             mediatek,mt8195-smi-larb                P                \           O   �           ¢       ¢            Áapb smi         «   3   !        î   Í      clock-controller@1604f000             mediatek,mt8195-camsys_rawa             ð                	           î   Ÿ      clock-controller@1606f000             mediatek,mt8195-camsys_yuva             ð                	           î          clock-controller@1608f000             mediatek,mt8195-camsys_rawb             ð                	           î   ¡      clock-controller@160af000             mediatek,mt8195-camsys_yuvb             
ð                	           î   ¢      clock-controller@16140000             mediatek,mt8195-camsys_mraw                              	           î   £      larb@16141000             mediatek,mt8195-smi-larb                                \           O   �           .       £       .           Áapb smi gals            «   3   "        î   Ì      larb@16142000             mediatek,mt8195-smi-larb                                 \           O   ž           £       £            Áapb smi         «   3   "        î   •      clock-controller@17200000             mediatek,mt8195-ccusys                                	           î   ¤      larb@17201000             mediatek,mt8195-smi-larb                                 \           O   ž           ¤       ¤            Áapb smi         «   3           î   ‘      video-codec@18000000              mediatek,mt8195-vcodec-dec          0   …        =   ˜                        +                               @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                =   †  à   †  á               A   &      &         �        Ásel vdec lat top            ÷      A              �        «   3         video-codec@10000             mediatek,mtk-vcodec-lat                               {      Ä             0  =   ˜      ˜     ˜     ˜     ˜     ˜                 A   &      &         �        Ásel vdec lat top            ÷      A              �        «   3         video-codec@25000             mediatek,mtk-vcodec-core                 P                {      Ã             P  =   ˜      ˜  ¡   ˜  ¢   ˜  £   ˜  ¤   ˜  ¥   ˜  ¦   ˜  §   ˜  ¨   ˜  ©               A   '      '         �        Ásel vdec lat top            ÷      A              �        «   3            larb@1800d000             mediatek,mt8195-smi-larb                 Ð                \           O   —           &       &            Áapb smi         «   3           î   Ë      larb@1800e000             mediatek,mt8195-smi-larb                 à                \           O   ¥           "      &            Áapb smi         «   3           î   ”      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc              ð                	           î   &      larb@1802e000             mediatek,mt8195-smi-larb                à                \           O   —           '       '            Áapb smi         «   3           î   Ê      clock-controller@1802f000             mediatek,mt8195-vdecsys             ð                	           î   '      larb@1803e000             mediatek,mt8195-smi-larb                à                \           O   ¥           "      (            Áapb smi         «   3           î   “      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1               ð                	           î   (      clock-controller@190f3000             mediatek,mt8195-apusys_pll              0                	         clock-controller@1a000000             mediatek,mt8195-vencsys                               	           î   )      larb@1a010000             mediatek,mt8195-smi-larb                                 \           O   —           )      )           Áapb smi         «   3           î   É      video-codec@1a020000              mediatek,mt8195-vcodec-enc                             H  =   ˜  `   ˜  a   ˜  b   ˜  c   ˜  d   ˜  v   ˜  w   ˜  x   ˜  y        {      U               0   …           )         	  Ávenc_sel            ÷      @              �        «   3                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec          «   3         0  =   ˜  m   ˜  n   ˜  r   ˜  s   ˜  t   ˜  u                     +         0                                              jpgdec@0,0            mediatek,mt8195-jpgdec-hw                                0  =   ˜  m   ˜  n   ˜  r   ˜  s   ˜  t   ˜  u        {      W                  )           Ájpgdec          «   3         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw                               0  =   ˜  m   ˜  n   ˜  r   ˜  s   ˜  t   ˜  u        {      X                  )           Ájpgdec          «   3         jpgdec@1,0            mediatek,mt8195-jpgdec-hw                               0  =   †  �   †  Ž   †  ’   †  “   †  ”   †  •        {      \                  *           Ájpgdec          «   3            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                 	           î   *      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                 Ä   ¦               	              ¦                  î   #   port                         +       endpoint@0                      	Z   §        î   ¨            jpeg-encoder@1a030000             mediatek,mt8195-jpgenc          «   3            =   †  ‡   †  ˆ   †  ‰   †  Œ                     +         0                                              jpgenc@0,0            mediatek,mt8195-jpgenc-hw                                   =   ˜  g   ˜  h   ˜  i   ˜  l        {      V                  )           Ájpgenc          «   3         jpgenc@1,0            mediatek,mt8195-jpgenc-hw                                  =   †  ‡   †  ˆ   †  ‰   †  Œ        {      [                  *           Ájpgenc          «   3            larb@1b010000             mediatek,mt8195-smi-larb                                 \           O   ‡           *      *      "            Áapb smi gals            «   3           î   ’      ovl@1c000000              mediatek,mt8195-disp-ovl                                  {      |               «   3              #            =   ˜              ¦             ports                        +       port@0                 endpoint            	Z   ¨        î   §         port@1                endpoint            	Z   ©        î   ª               rdma@1c002000             mediatek,mt8195-disp-rdma                                 {      ~               «   3              #           =   ˜               ¦             ports                        +       port@0                 endpoint            	Z   ª        î   ©         port@1                endpoint            	Z   «        î   ¬               color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                0                {                     «   3              #              ¦     0       ports                        +       port@0                 endpoint            	Z   ¬        î   «         port@1                endpoint            	Z   ­        î   ®               ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                @                {      €               «   3              #              ¦     @       ports                        +       port@0                 endpoint            	Z   ®        î   ­         port@1                endpoint            	Z   ¯        î   °               aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                P                {      �               «   3              #              ¦     P       ports                        +       port@0                 endpoint            	Z   °        î   ¯         port@1                endpoint            	Z   ±        î   ²               gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                `                {      ‚               «   3              #              ¦     `       ports                        +       port@0                 endpoint            	Z   ²        î   ±         port@1                endpoint            	Z   ³        î   ´               dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither              p                {      ƒ               «   3              #   	           ¦     p       ports                        +       port@0                 endpoint            	Z   ´        î   ³         port@1                endpoint            	Z   µ        î   ¼               dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi              €                {      „               «   3              #      #   *   ¶        Áengine digital hs           	   ¶        
Ždphy            ‹okay                         +       panel@0       #    startek,kd070fhfid078 himax,hx8279                      |   ·        †      0            „      l            “   ¸        ]   ¹        Ádefault         Ï   º   port       endpoint            	Z   »        î   ½            ports                        +       port@0                 endpoint            	Z   ¼        î   µ         port@1                endpoint            	Z   ½        î   »               dsc@1c009000              mediatek,mt8195-disp-dsc                 �                {      …               «   3              #              ¦     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              {      Ž               «   3              #      #   +   ¾        Áengine digital hs           	   ¾        
Ždphy          	  ‹disabled          merge@1c014000            mediatek,mt8195-disp-merge              @                {      �               «   3              #              ¦     @          dp-intf@1c015000              mediatek,mt8195-dp-intf             P                {      ‘               «   3              #   ,   #                 Ápixel engine pll          	  ‹disabled          mutex@1c016000            mediatek,mt8195-disp-mutex              `                {      ’               «   3              #              ¦     `              U      larb@1c018000             mediatek,mt8195-smi-larb                €                \            O   —           #   (   #   (   "           Áapb smi gals            «   3           î   À      larb@1c019000             mediatek,mt8195-smi-larb                �                \           O   ‡           #   (   "       "           Áapb smi gals            «   3           î   ‰      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                               Ä   ¦                 ¦                  	           ×           î   +   port                         +       endpoint@1                     	Z   ¿        î   Ò            smi@1c01b000              mediatek,mt8195-smi-common-vdo              °                    #   %   #   &   #   )   #   $        Áapb smi gals0 gals1         «   3           î   —      iommu@1c01f000            mediatek,mt8195-iommu-vdo               ð              8  m   À   Á   Â   Ã   Ä   Å   Æ   Ç   È   É   Ê   Ë   Ì   Í        {      �               v              #   '        Ábclk            «   3           î   ˜      mutex@1c101000            mediatek,mt8195-disp-mutex                              {      î               «   3              +              ¦                   À      larb@1c102000             mediatek,mt8195-smi-larb                                 \           O   —           +       +       +           Áapb smi gals            «   3           î   Á      larb@1c103000             mediatek,mt8195-smi-larb                0                \           O   ‡           +      +      "            Áapb smi gals            «   3           î   Š      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma               @                {      ï                  +           «   3           =   ˜   @           ¦     @            D         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma               P                {      ð                  +           «   3           =   †   `           ¦     P            D         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma               `                {      ñ                  +           «   3           =   ˜   A           ¦     `            D         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma               p                {      ò                  +           «   3           =   †   a           ¦     p            D         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma               €                {      ó                  +           «   3           =   ˜   B           ¦     €            D         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma               �                {      ô                  +           «   3           =   †   b           ¦     �            D         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma                                {      õ                  +           «   3           =   ˜   C           ¦                  D         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma               °                {      ö                  +           «   3           =   †   c           ¦     °            D         vpp-merge@1c10c000            mediatek,mt8195-disp-merge              À                {      ÷                  +   	   +           Ámerge merge_async           «   3              ¦     À                      Ý   +         vpp-merge@1c10d000            mediatek,mt8195-disp-merge              Ð                {      ø                  +   
   +           Ámerge merge_async           «   3              ¦     Ð                      Ý   +         vpp-merge@1c10e000            mediatek,mt8195-disp-merge              à                {      ù                  +      +           Ámerge merge_async           «   3              ¦     à                      Ý   +         vpp-merge@1c10f000            mediatek,mt8195-disp-merge              ð                {      ú                  +      +           Ámerge merge_async           «   3              ¦     ð                      Ý   +         vpp-merge@1c110000            mediatek,mt8195-disp-merge                               {      û                  +      +           Ámerge merge_async           «   3              ¦                   ´        Ý   +      ports                        +       port@0                       +                   endpoint@1                     	Z   Î        î   Ó         port@1                       +                  endpoint@1                     	Z   Ï        î   Ð               dpi@1c112000              mediatek,mt8195-dpi                                 +   -   +      +   2        Ápixel engine pll            {                      «   3           Ý   +           ‹okay       ports                        +       port@0                 endpoint            	Z   Ð        î   Ï         port@1                endpoint            	Z   Ñ        î   Ö               dp-intf@1c113000              mediatek,mt8195-dp-intf             0                {                     «   3              +   /   +                 Ápixel engine pll          	  ‹disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p      @            P            p            �                         °            À              4  ämixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p     ¦     @       ¦     P       ¦     p       ¦     �       ¦             ¦     °       ¦     À          h     +   %   +       +   #   +   !   +   $   +   "   +   1   +   &   +   '   +   (   +   )   +   *            ƒ  Ámixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          «   3           =   †   d   †   e        {                   (  Ý   +   3   +   4   +   5   +   6   +   7      E  ävdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async       ports                        +       port@0                       +                   endpoint@1                     	Z   Ò        î   ¿         port@1                       +                  endpoint@1                     	Z   Ó        î   Î               hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx                        0                        Q      L      M   $   ,        Ábus hdcp hdcp24m hdmi-split         ÷      L              “        {      ¥               «   3           	   Ô        
Žhdmi            ‹okay            Ádefault         Ï   Õ        î      i2c           mediatek,mt8195-hdmi-ddc                       î   ã      ports                        +       port@0                 endpoint            	Z   Ö        î   Ñ         port@1                endpoint            	Z   ×        î   ä               edp-tx@1c500000           mediatek,mt8195-edp-tx              P        €         ð   Ø        üdp_calibration_data         «   3           {      ¤               Ë  ¤      	  ‹disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx               `        €         ð   Ø        üdp_calibration_data         «   3           {      Ê               Ë  ¤      	  ‹disabled             thermal-zones      cpu0-thermal            Ü  è        ê   ú            Ù      trips      trip-alert           L          Ð        passive         î   Ú      trip-crit            †           Ð      	  critical             cooling-maps       map0            '   Ú      0  ,   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            Ü  è        ê   ú            Ù      trips      trip-alert           L          Ð        passive         î   Û      trip-crit            †           Ð      	  critical             cooling-maps       map0            '   Û      0  ,   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            Ü  è        ê   ú            Ù      trips      trip-alert           L          Ð        passive         î   Ü      trip-crit            †           Ð      	  critical             cooling-maps       map0            '   Ü      0  ,   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            Ü  è        ê   ú            Ù      trips      trip-alert           L          Ð        passive         î   Ý      trip-crit            †           Ð      	  critical             cooling-maps       map0            '   Ý      0  ,   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            Ü  è        ê   ú            Ù       trips      trip-alert           L          Ð        passive         î   Þ      trip-crit            †           Ð      	  critical             cooling-maps       map0            '   Þ      0  ,   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            Ü  è        ê   ú            Ù      trips      trip-alert           L          Ð        passive         î   ß      trip-crit            †           Ð      	  critical             cooling-maps       map0            '   ß      0  ,   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            Ü  è        ê   ú            Ù      trips      trip-alert           L          Ð        passive         î   à      trip-crit            †           Ð      	  critical             cooling-maps       map0            '   à      0  ,   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            Ü  è        ê   ú            Ù      trips      trip-alert           L          Ð        passive         î   á      trip-crit            †           Ð      	  critical             cooling-maps       map0            '   á      0  ,   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            Ü  è        ê   ú            â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                vpu1-thermal            Ü  è        ê   ú            â   	   trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                gpu-thermal         Ü  è        ê   ú            â   
   trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                gpu1-thermal            Ü  è        ê   ú            â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                vdec-thermal            Ü  è        ê   ú            â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                img-thermal         Ü  è        ê   ú            â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                infra-thermal           Ü  è        ê   ú            â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                cam0-thermal            Ü  è        ê   ú            â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                cam1-thermal            Ü  è        ê   ú            â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                   chosen          ;serial0:921600n8          connector             hdmi-connector          
òhdmi            a           G   ã        S   Ô   port       endpoint            	Z   ä        î   ×            firmware       optee             linaro,optee-tz         smc          memory@40000000         memory              @                reserved-memory                      +               optee@43200000           c            C        À        memory@50000000           shared-dma-pool             P       �           c        î   1      memory@53000000           shared-dma-pool             S       @        memory@54600000          c            T`                memory@60000000           shared-dma-pool             `        ð           c        î   7      memory@60f00000           shared-dma-pool             `ð                  c        î   9      memory@61000000           shared-dma-pool             a                   c        î   6      memory@62000000           shared-dma-pool             b       @           backlight-lcm0            pwm-backlight           j      ÿ        |  @        •  ÿ        ¬   å     ¡         î   ·      backlight-lcd1            pwm-backlight           ¬   æ     ¡         †      .            j      ÿ        •  ÿ        |  @      	  ‹disabled          can-clk           fixed-clock         	            81-         2can-clk         î   A      regulator-0           regulator-fixed         ‘edp_panel_3v3             2Z         ¸ 2Z          ±                          Ádefault         Ï   ç      regulator-1           regulator-fixed         ‘edp_backlight_12v             ·         ¸ ·          ±              `            Ádefault         Ï   è      gpio-keys         
    gpio-keys      button-volume-up             h        Ä   d        E      j         
  
òvolume_up           Ö   s         regulator-vio18-lcm0              regulator-fixed         ‘vio18_lcm0           ±              /            Ádefault         Ï   é        á   ê        î   ¸      regulator-vsys-lcm0           regulator-fixed       
  ‘vsys_lcm0            ì         ì        á   p        î   ¹      regulator-2           regulator-fixed       	  ‘wifi_3v3              2Z         ¸ 2Z               ‡             ±         ì         	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 ethernet0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform pinctrl-names pinctrl-0 audio-routing mediatek,adsp link-name sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux output-high drive-strength input-enable input-disable bias-disable bias-pull-up bias-pull-down drive-strength-microamp output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells mediatek,mic-type-0 mediatek,mic-type-1 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select cs-gpios spi-max-frequency vdd-supply xceiver-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us mediatek,tx-delay-ps mediatek,mac-wol pinctrl-1 snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup dr_mode usb-role-switch vusb33-supply remote-endpoint bus-width cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc freq-table-hz mediatek,ufs-disable-mcq vcc-supply vccq2-supply bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply label data-role op-sink-microwatt power-role try-power-role source-pdos sink-pdos pd-revision svid vdo mediatek,ibias mediatek,ibias_up irq-gpios reset-gpios AVDD28-supply mode-switch orientation-switch mediatek,force-mode operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs backlight enable-gpios iovcc-supply mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path ddc-i2c-bus hdmi-pwr-supply no-map brightness-levels default-brightness-level num-interpolated-steps pwms enable-active-high debounce-interval linux,code vin-supply regulator-boot-on 