Ðþí i�   8 ]D   (            I ]                             6    kontron,3-5-sbc-i1200 mediatek,mt8395 mediatek,mt8195                                    +            7Kontron 3.5"-SBC-i1200     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/mailbox@10320000            Y/soc/mailbox@10330000            ^/soc/hdmi-tx@1c300000            d/soc/hdr-engine@1c114000             k/soc/mutex@1c016000          r/soc/mutex@1c101000          y/soc/vpp-merge@1c10c000          €/soc/vpp-merge@1c10d000          ‡/soc/vpp-merge@1c10e000          Ž/soc/vpp-merge@1c10f000          •/soc/vpp-merge@1c110000          œ/soc/dma-controller@1c104000             §/soc/dma-controller@1c105000             ²/soc/dma-controller@1c106000             ½/soc/dma-controller@1c107000             È/soc/dma-controller@1c108000             Ó/soc/dma-controller@1c109000             Þ/soc/dma-controller@1c10a000             é/soc/dma-controller@1c10b000             ô/soc/mmc@11230000            ù/soc/mmc@11240000            þ/soc/serial@11001200            /soc/serial@11001300            /soc/serial@11001400            /soc/serial@11001500            /soc/serial@11001100          cpus                         +       cpu@0           &cpu           arm,cortex-a55          2            6psci            D               Xec3@        h  4        {              ‹  €         ˜   @        ª   €        ·  €         Ä   @        Ö   €        ã           ô              	      cpu@100         &cpu           arm,cortex-a55          2           6psci            D               Xec3@        h  4        {              ‹  €         ˜   @        ª   €        ·  €         Ä   @        Ö   €        ã           ô              
      cpu@200         &cpu           arm,cortex-a55          2           6psci            D               Xec3@        h  4        {              ‹  €         ˜   @        ª   €        ·  €         Ä   @        Ö   €        ã           ô                    cpu@300         &cpu           arm,cortex-a55          2           6psci            D               Xec3@        h  4        {              ‹  €         ˜   @        ª   €        ·  €         Ä   @        Ö   €        ã           ô                    cpu@400         &cpu           arm,cortex-a78          2           6psci            D              X�fÔÀ        h           {              ‹           ˜   @        ª           ·           Ä   @        Ö           ã           ô                    cpu@500         &cpu           arm,cortex-a78          2           6psci            D              X�fÔÀ        h           {              ‹           ˜   @        ª           ·           Ä   @        Ö           ã           ô                    cpu@600         &cpu           arm,cortex-a78          2           6psci            D              X�fÔÀ        h           {              ‹           ˜   @        ª           ·           Ä   @        Ö           ã           ô                    cpu@700         &cpu           arm,cortex-a78          2           6psci            D              X�fÔÀ        h           {              ‹           ˜   @        ª           ·           Ä   @        Ö           ã           ô                    cpu-map    cluster0       core0              	      core1              
      core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state                     3        D   2        U   _        e  D                 cpu-retention-b           arm,idle-state                     3        D   -        U   Œ        e  ä                 cpu-off-l             arm,idle-state                    3        D   7        U   ›        e  H                 cpu-off-b             arm,idle-state                    3        D   2        U   È        e  è                    l2-cache0             cache           v           �           š   @        ¬           ã            ‚                 l2-cache1             cache           v           �           š   @        ¬           ã            ‚                 l3-cache              cache           v           �            š   @        ¬            ‚                    dsu-pmu           arm,dsu-pmu         �                       ›   	   
                           fail          dmic-codec            dmic-codec          §           ´   2      mt8195-sound            Ä         	   disabled          fixed-factor-clock-13m            fixed-factor-clock          Ö            ã           ê           ô           ÿclk13m             (      oscillator-26m            fixed-clock         Ö            XŒº€        ÿclk26m                   oscillator-32k            fixed-clock         Ö            X  €         ÿclk32k        performance-controller@11bc10             mediatek,cpufreq-hw          2     ¼            ½0                                   opp-table-gpu             operating-points-v2          ,           n   opp-390000000           7    >í€        > 	‰h      opp-410000000           7    p€        > 	¡Ò      opp-431000000           7    °‰À        > 	¡Ò      opp-473000000           7    1h@        > 	º<      opp-515000000           7    ²FÀ        > 	º<      opp-556000000           7    !#ã         > 	Ò¦      opp-598000000           7    #¤Á€        > 	ë      opp-640000000           7    &%          > 	ë      opp-670000000           7    'ïc€        > 
ä      opp-700000000           7    )¹'         > 
L¸      opp-730000000           7    +‚ê€        > 
}Œ      opp-760000000           7    -L®         > 
®`      opp-790000000           7    /q€        > 
ß4      opp-820000000           7    0à5         >       opp-850000000           7    2©ø€        > @Ü      opp-880000000           7    4s¼         > q°         pmu-a55           arm,cortex-a55-pmu                      �                  pmu-a78           arm,cortex-a78-pmu                      �                  psci              arm,psci-1.0            =smc       timer             arm,armv8-timer                   @  �                                             
             soc                      +             simple-bus           L        S                          interrupt-controller@c000000              arm,gic-v3          ^           o                        †         2                                    �      	                     ppi-partitions     interrupt-partition-0           ›   	   
                       interrupt-partition-1           ›                                   syscon@10000000            mediatek,mt8195-topckgen syscon         2                      Ö                    syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          2                     Ö           ¤                    syscon@10003000           mediatek,mt8195-pericfg syscon          2     0                Ö              A      pinctrl@10005000              mediatek,mt8195-pinctrl       €  2     P            Ñ             Ó             Ô             â             ë             ô              °              B  ±iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            »        Ë           ×              �         †        �       ë               ^                 eth-default-pins               =   pins-txd            ã  M  N  O  P        ê         pins-rxd            ã  Q  R  S  T      pins-cc         ã  U  V  W  X        ê         pins-mdio           ã  Y  Z         ù      pins-power          ã  [   \                pins-reset          ã  ]                pins-interrupt          ã  ^          ù         eth-sleep-pins             >   pins-txd            ã  M   N   O   P       pins-cc         ã  U   X   W   V       pins-rxd            ã  Q   R   S   T       pins-mdio           ã  Y   Z                             gpio-keys-pins             ¾   pins            ã  j          ù         i2c0-pins              [   pins            ã    	        -   Ï        :  è         i2c1-pins              \   pins            ã  
          -   Ï        :  è         i2c2-default-pins              ]   pins-bus            ã            -   Ï        :  è         i2c3-pins              ^   pins            ã            -   Ï        :  è         i2c4-pins              _   pins            ã            -   Ï        :  è         i2c6-pins              X   pins            ã             -        :  è         mmc0-default-pins              C   pins-clk            ã  z        ê           R   f      pins-cmd-dat          $  ã  ~  }  |  {  w  v  u  t  y         ù        ê           -   e      pins-rst            ã  x        ê           -   e         mmc0-uhs-pins              D   pins-clk            ã  z        ê           R   f      pins-cmd-dat          $  ã  ~  }  |  {  w  v  u  t  y         ù        ê           -   e      pins-ds         ã          ê           R   f      pins-rst            ã  x        ê           -   e         mmc1-default-pins              G   pins-clk            ã  o        ê           R   f      pins-cmd-dat            ã  n  p  q  r  s         ù        ê           -   e         mmc1-detect-pins               H   pins-insert         ã  �          -         nor-default-pins               V   pins-ck-io          ã  Ž  �  �        ê            R      pins-cs         ã  Œ        ê            -         pcie0-default-pins             R   pins-bus            ã               -         pcie1-default-pins             U   pins-bus            ã               -   e         led-pins               ¿   pins-power-en           ã  k                   spi0-default-pins              4   pins-cs-mosi-clk            ã  „  †  …                pins-miso           ã  ‡         R         spi1-default-pins              8   pins-cs-mosi-clk            ã  ˆ  Š  ‰                pins-miso           ã  ‹         R         uart0-pins             /   pins-rx         ã  c         ù         -      pins-tx         ã  b         uart1-pins             0   pins-rx         ã  g         ù         -      pins-tx         ã  f      pins-rts            ã  d      pins-cts            ã  e         ù         uart2-pins             1   pins-rx         ã  D         ù         -      pins-tx         ã  C      pins-rts            ã  B      pins-cts            ã  A         ù         uart3-pins             2   pins-rx         ã           ù        -   e      pins-tx         ã           uart4-pins             3   pins-rx         ã           ù         -      pins-tx         ã              syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            2     `           power-controller          !    mediatek,mt8195-power-controller                         +            a              +   power-domain@8          2                        +            a      power-domain@9          2   	        ã                    umfg alt         �                        +            a      power-domain@10         2   
        a          power-domain@11         2           a          power-domain@12         2           a          power-domain@13         2           a          power-domain@14         2           a                power-domain@15         2         Ø  ã                        	      @      A      K      à                                                                                                                          uvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           �                        +            a      power-domain@16         2         8  ã      â      $      %      &      '      (      )      D  uvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         �                        +            a      power-domain@17         2           ã      á                    uvppsys1 vppsys1-0 vppsys1-1         �           a          power-domain@22         2            ã                              $  uwepsys-0 wepsys-1 wepsys-2 wepsys-3         �           a          power-domain@23         2           ã               uvdec0-0         �                        +            a       power-domain@24         2           ã               uvdec1-0         �           a          power-domain@25         2           ã                uvdec2-0         �           a             power-domain@26         2           ã   !            uvenc0-larb          �                        +            a       power-domain@27         2           ã   "            uvenc1-larb          �           a             power-domain@18         2            ã      ã   #       #      #         &  uvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           �                        +            a      power-domain@19         2           �           a          power-domain@20         2           �           a          power-domain@21         2           ã      Q        uhdmi_tx         a             power-domain@28         2           ã   $       $   
        uimg-0 img-1         �                        +            a      power-domain@29         2           a          power-domain@30         2           ã         $      %           uipe ipe-0 ipe-1         �           a             power-domain@31         2         (  ã   &       &      &      &      &           ucam-0 cam-1 cam-2 cam-3 cam-4           �                        +            a      power-domain@32         2            a          power-domain@33         2   !        a          power-domain@34         2   "        a                   power-domain@0          2            �           a          power-domain@1          2           �           a          power-domain@2          2           a          power-domain@3          2           a          power-domain@4          2           ã      5      7        ucsi_rx_top csi_rx_top1          a          power-domain@5          2           ã   '           uether           a          power-domain@6          2           ã      X      n        uadsp adsp1                       +            �           a      power-domain@7          2            ã      g      "      n      2        uaudio audio1 audio2 audio3          �           a                   watchdog@10007000             mediatek,mt8195-wdt          “        2     p                ¤              .      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           2     À                Ö                    timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         2    p                �      	               ã   (      pwrap@10024000            mediatek,mt8195-pwrap syscon            2    @                ±pwrap           �       ó               ã                   	  uspi wrap            «      $        »      Ë   pmic              mediatek,mt6359          †        ^           Ò           ã      Þ      adc           mediatek,mt6359-auxadc          ÷         audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            	vs1          5         0 !‘À        H             d      buck_vgpu11         	vgpu11           €        0 7        x  ˆ        H   È        �                   d      buck_vmodem         	vmodem           €        0 Èà        x  *        H   È      buck_vpu            	vpu          €        0 7        x  ˆ        H   È        �                   d      buck_vcore          	vcore            €        0 Ö         x  ˆ        H   È        �                   d      buck_vs2            	vs2          5         0 j         H             d      buck_vpa            	vpa          ¡         0 7±Ð        H  ,      buck_vproc2         	vproc2           €        0 7        x  L        H   È        �                   d      buck_vproc1         	vproc1           €        0 7        x  L        H   È        �                   d      buck_vcore_sshub            	vcore_sshub          €        0 7      buck_vgpu11_sshub           	vgpu11_sshub             €        0 7      ldo_vaud18          	vaud18           w@        0 w@        H   ð      ldo_vsim1           	vsim1            ð         0 /M`      ldo_vibr            	vibr             O€        0 2Z       ldo_vrf12           	vrf12            Èà        0 Ö          d      ldo_vusb            	vusb             -ÆÀ        0 -ÆÀ        H  À         d           B      ldo_vsram_proc2         	vsram_proc2          ¡         0 ½¶        x  L        H   ð         d      ldo_vio18           	vio18            ð         0 ýà        H  À         d      ldo_vcamio          	vcamio           ð         0 ýà      ldo_vcn18           	vcn18            w@        0 w@        H   ð      ldo_vfe28           	vfe28            *¹€        0 *¹€        H   x      ldo_vcn13           	vcn13            »         0 Ö       ldo_vcn33_1_bt          	vcn33_1_bt           *¹€        0 5gà      ldo_vcn33_1_wifi            	vcn33_1_wifi             *¹€        0 5gà      ldo_vaux18          	vaux18           w@        0 w@        H   ð         d      ldo_vsram_others            	vsram_others             ¡         0 ½¶        x  ˆ        H   ð         d      ldo_vefuse          	vefuse           ð         0 „€      ldo_vxo22           	vxo22            w@        0 !‘À         d      ldo_vrfck           	vrfck            ã`        0 ð       ldo_vrfck_1         	vrfck            ëÀ        0 j       ldo_vbif28          	vbif28           *¹€        0 *¹€        H   ð      ldo_vio28           	vio28            *¹€        0 2Z          d      ldo_vemc            	vemc             ,@         0 2Z       ldo_vemc_1          	vemc             &%         0 2Z            E      ldo_vcn33_2_bt          	vcn33_2_bt           *¹€        0 5gà      ldo_vcn33_2_wifi            	vcn33_2_wifi             *¹€        0 5gà      ldo_va12            	va12             O€        0 Ö          d      ldo_va09            	va09             5         0 O€      ldo_vrf18           	vrf18            ð         0 žP      ldo_vsram_md          	  	vsram_md             ¡         0 ½¶        x  *        H   ð         d      ldo_vufs            	vufs             ð         0 ýà           F      ldo_vm18            	vm18             ð         0 ýà         d      ldo_vbbck           	vbbck            Èà        0 O€         d      ldo_vsram_proc1         	vsram_proc1          ¡         0 ½¶        x  L        H   ð         d      ldo_vsim2           	vsim2            ð         0 /M`      ldo_vsram_others_sshub          	vsram_others_sshub           ¡         0 ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             2    p            �                ±pmif spmimst            ã                   E      (  upmif_sys_ck pmif_tmr_ck spmimst_clk_mux         «      $        »      Ë                     +       mt6315@6              mediatek,mt6315-regulator           2          regulators     vbuck1          	Vbcpu            “à        0 7        H           x  j        �                   d            mt6315@7              mediatek,mt6315-regulator           2          regulators     vbuck1          	Vgpu             	‰h        0 7        H           x  j        �                   d           o               infra-iommu@10315000              mediatek,mt8195-iommu-infra         2    1P       P       P  �                                                                         ¥              O      mailbox@10320000              mediatek,mt8195-gce         2    2        @         �       â               ²           ã                 ’      mailbox@10330000              mediatek,mt8195-gce         2    3        @         �       ä               ²           ã                 p      scp@10500000              mediatek,mt8195-scp       0  2    P             r             p        €         ±sram cfg l1tcm          �      Î                okay            ¾   )        Ìmediatek/mt8195/scp.img            q      clock-controller@10720000             mediatek,mt8195-scp_adsp            2    r                 Ö              *      dsp@10803000              mediatek,mt8195-dsp          2    €0            „               	  ±cfg sram          ,  ã      X         n      Š   *          #      K  uadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          Ú   +           èrx tx           ó   ,   -      	   disabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           ²            2    �`                �      ¾                  ,      mailbox@10817000              mediatek,mt8195-adsp-mbox           ²            2    �p                �      ¿                  -      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           2    ‰                 ú           Ú   +           �      6                  .         	  audiosys          ”  ã                     Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d      2   *          ó  uclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	   disabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                     �       �               ã               	  ubaud bus             okay            default         -   /      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                     �       Ž               ã               	  ubaud bus             okay            default         -   0         7      serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                     �       �               ã               	  ubaud bus             okay            default         -   1         7      serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                     �      Ó               ã               	  ubaud bus             okay            default         -   2      serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                     �      Ô               ã               	  ubaud bus             okay            default         -   3      serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           2                     �      Õ               ã               	  ubaud bus          	   disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           2                      ã              umain            ÷            okay               À      syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           2     0                Ö              '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2                      �       ¿               ã      ™                    uparent-clk sel-clk spi-clk           okay            default         -   4        G       tpm@0         !    infineon,slb9670 tcg,tpm_tis-spi            2            [I          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         2     °                �       ©               ã                             m   5   6      $  ylvts-calib-data-1 lvts-calib-data-2         Š              º      svs@1100bc00              mediatek,mt8195-svs         2     ¼                �       Ç               ã              umain            m   7   5      (  ysvs-calibration-data t-calibration-data                       svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           2     à                �       Ë               Ú   +                       ã      *      0        umain mm       	   disabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           2     ð                �                                 ã      +      N        umain mm       	   disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2                     �       À               ã      ™            3        uparent-clk sel-clk spi-clk           okay            default         -   8        G          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2                     �       Á               ã      ™            4        uparent-clk sel-clk spi-clk        	   disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2    0                �       Â               ã      ™            5        uparent-clk sel-clk spi-clk        	   disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2    €                �       Ã               ã      ™            <        uparent-clk sel-clk spi-clk        	   disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            2    �                �       Ä               ã      ™            =        uparent-clk sel-clk spi-clk        	   disabled          spi@1101d000              mediatek,mt8195-spi-slave           2    Ð                �       Å               ã      R        uspi         «              »      ˜      	   disabled          spi@1101e000              mediatek,mt8195-spi-slave           2    à                �       Æ               ã      S        uspi         «              »      ˜      	   disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           2           @         �      Ì               «macirq        .  uaxi apb mac_main ptp_ref rmii_internal mac_cg         0  ã   '       '         R      S      T   '           «      R      S      T        »      Â      Ã      Ä        Ú   +           »           Ì   9        Ü   :        ï   ;                                           okay          	  %rgmii-id            .   <        default sleep           -   =        9   >         C   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916            2           ã      ^           T  '        d 8€        v      ]               <         stmmac-axi-config           ‚           ’           ¢                                    9      rx-queues-config            ¬            Â           :   queue0           Ó        æ          queue1           Ó        æ          queue2           Ó        æ          queue3           Ó        æ             tx-queues-config            þ                       ;   queue0          &            Ó        2          queue1          &            Ó        2         queue2          &            Ó        2         queue3          &            Ó        2               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           2            -ÿ     >              	  ±mac ippc            L                     ?                      +           �       €               ã      /      í      B        usys_ck ref_ck mcu_ck            @   ?      @            E        S   A      g         okay            jhost            r   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          2                       ±mac         �       �               «      ,      -        »      –      –      $  ã      /      í               B      $  usys_ck ref_ck mcu_ck dma_ck xhci_ck          okay             mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          2    #             õ                 �       ƒ               ã                          usource hclk source_cg            okay            default state_uhs           -   C        9   D        €           _ëÂ         Š L         ™         «         ¼         Ë         Ú         â         è        ö   E        	   F      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          2    $             Ç                 �       ‡               ã                  $        usource hclk source_cg           «              »      ¿         okay            default state_uhs           -   G   H        9   G        	      �           €           _ëÂ          	         	)         	6         	D        ö   I        	   J      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          2    %             æ                 �       ˆ               ã                   I        usource hclk source_cg           «               »      ¿      	   disabled          ufshci@11270000           mediatek,mt8195-ufshci          2    '        #         �       ‰               @   K      @  ã      ?      @      A      6      7      8      Z      ]      X  uufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  	K                                                                         	Y      	   disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            2    '€                �       ª               ã                            m   5   6      $  ylvts-calib-data-1 lvts-calib-data-2         Š              ±      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           2    )             )>              	  ±mac ippc            �                     @   L           «      .      /        »      –      –      $  ã   '         ï            '         $  usys_ck ref_ck mcu_ck dma_ck xhci_ck         S   A      h         E         okay            r   B        	r         usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           2    *       -ÿ    *>              	  ±mac ippc            L            *        ?                      +           �                     «      0        »      –        ã   '         ñ   '           usys_ck ref_ck mcu_ck            @   M            E        S   A      i         okay            r   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          2                       ±mac         �                     «      1        »      –        ã   '           usys_ck           okay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           2    +       -ÿ    +>              	  ±mac ippc            L            +        ?                      +           �                     «      2        »      –        ã   '         ó   '   	        usys_ck ref_ck mcu_ck            @   N            E        S   A      j         okay            r   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          2                       ±mac         �                     «      3        »      –        ã   '   	        usys_ck           okay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           &pci                      +           2    /        @       	  ±pcie-mac            �                     	‡       ÿ      8  L�                           ‚                       à          	‘       O              	›          0  ã      V      #      &      +      K   '         /  upl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          «      G        »              @   P      	  	ªpcie-phy            Ú   +            ^           	´                     `  	Ç                  Q                      Q                     Q                     Q            okay            default         -   R   interrupt-controller             †                     ^              Q         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           &pci                      +           2    /€       @       	  ±pcie-mac            �                     	‡       ÿ      8  L�       $       $           ‚       $       $       à          	‘       O              	›          (  ã      W         X         Q   '         /  upl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          «      H        »              @   S         	  	ªpcie-phy            Ú   +           ^           	´                     `  	Ç                  T                      T                     T                     T            okay            default         -   U   interrupt-controller             †                     ^              T         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         2    2À                �      9               ã      o   '      '           uspi sf axi                       +             okay            default         -   V   flash@0           jedec,spi-nor           2            [u         	Õ           	æ            efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            2    Á                              +      usb3-tx-imp@184,1           2  „           	÷                  e      usb3-rx-imp@184,2           2  „           	÷                 d      usb3-intr@185           2  …           	÷                 c      usb3-tx-imp@186,1           2  †           	÷                  b      usb3-rx-imp@186,2           2  †           	÷                 a      usb3-intr@187           2  ‡           	÷                 `      usb2-intr-p0@188,1          2  ˆ           	÷             usb2-intr-p1@188,2          2  ˆ           	÷            usb2-intr-p2@189,1          2  ‰           	÷            usb2-intr-p3@189,2          2  ‰           	÷            pciephy-rx-ln1@190,1            2  �           	÷                  l      pciephy-tx-ln1-nmos@190,2           2  �           	÷                 k      pciephy-tx-ln1-pmos@191,1           2  ‘           	÷                  j      pciephy-rx-ln0@191,2            2  ‘           	÷                 i      pciephy-tx-ln0-nmos@192,1           2  ’           	÷                  h      pciephy-tx-ln0-pmos@192,2           2  ’           	÷                 g      pciephy-glb-intr@193            2  “           	÷                  f      dp-data@1ac         2  ¬              °      lvts1-calib@1bc         2  ¼              5      lvts2-calib@1d0         2  Ð   8           6      svs-calib@580           2  €   d           7      socinfo-data1@7a0           2               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           L        Ä              okay       usb-phy@0           2               ã      ò        uref         	ü              M         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           L        Å              okay       usb-phy@0           2               ã      ô        uref         	ü              N         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         2    È                 ã           ÿmipi_tx0_pll            Ö            	ü          	   disabled               Ÿ      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         2    É                 ã           ÿmipi_tx1_pll            Ö            	ü          	   disabled                      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2    Ð             "€       €        �       š               ê           ã   W          ;      	  umain dma                         +          	   disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2    Ð            "        €        �       ›               ê           ã   W         ;      	  umain dma                         +             okay            X €        -   X        default    pmic@34           mediatek,mt6360         2   4         †        ã      e           «IRQB            ^      regulator             mediatek,mt6360-regulator           
   Y        
   Y        
'   Y   buck1         	  	emi_vdd2             	'À        0 w@        �                   d      buck2         	  	emi_vddq             “à        0 Ö         �                   d      ldo1            	mt6360_ldo1          O€        0 6î€        �             ldo2            	panel1_p1v8          w@        0 w@        �             ldo3            	vmc_pmu          w@        0 2Z         �                  J      ldo5          	  	vmch_pmu             2Z         0 2Z         �                  I      ldo6            	mt6360_ldo6          ¡         0           �             ldo7            	emi_vmddr_en             w@        0 w@        �                d               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2    Ð             "€       €        �       œ               ê           ã   W         ;      	  umain dma                         +          	   disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          2    Ð0                Ö              W      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy            2    Õð                 ã      P                          upll_ref 26m pll1 pll2           ÿhdmi_txpll          Ö            	ü            
7   
        
F         	   disabled               ¯      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2    à             " €       €        �       �               ê           ã   Z          ;      	  umain dma                         +             okay            default         -   [        X †       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2    à            "        €        �       “               ê           ã   Z         ;      	  umain dma                         +             okay            default         -   \        X †       i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2    à             "€       €        �       –               ê           ã   Z         ;      	  umain dma                         +             okay            default         -   ]        X €      i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2    à0            "€       €        �       ˜               ê           ã   Z         ;      	  umain dma                         +             okay            default         -   ^        X †       i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          2    à@            "        €        �       ™               ê           ã   Z         ;      	  umain dma                         +             okay            X †         -   _        default       clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          2    àP                Ö              Z      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           L        ã             Ú   +            okay       usb-phy@0           2               ã      ð           uref da_ref          	ü              L      usb-phy@700         2              ã            ð        uref da_ref          m   `   a   b        yintr rx_imp tx_imp          	ü              S         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           L        ä              okay       usb-phy@0           2               ã      î           uref da_ref          	ü              ?      usb-phy@700         2              ã            î        uref da_ref          m   c   d   e        yintr rx_imp tx_imp          	ü              @         phy@11e80000              mediatek,mt8195-pcie-phy            2    è                 ±sif         m   f   g   h   i   j   k   l      G  yglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          Ú   +           	ü             okay               P      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           2    ú        À         ã            
  uunipro mp           	ü          	   disabled               K      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           2             @         ã   m          0  �      �             Œ             ‹               «job mmu gpu         
X   n      (  Ú   +   
   +      +      +      +           
lcore0 core1 core2 core3 core4            okay            
   o      clock-controller@13fbf000             mediatek,mt8195-mfgcfg          2    ûð                Ö              m      syscon@14000000           mediatek,mt8195-vppsys0 syscon          2                      Ö           
‹   p                            dma-controller@14001000           mediatek,mt8195-mdp3-rdma           2                     
‹   p                  
£              
·   q        Ú   +           
Ä   r   €        ã            <  ó   p         p         p         p         p              
Ë         display@14002000              mediatek,mt8195-mdp3-fg         2                      
‹   p                   ã             display@14003000              mediatek,mt8195-mdp3-stitch         2     0                
‹   p      0            ã            display@14004000              mediatek,mt8195-mdp3-hdr            2     @                
‹   p      @            ã      "      display@14005000              mediatek,mt8195-mdp3-aal            2     P                �      F               
‹   p      P            ã      
        Ú   +         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           2     `                
‹   p      `            
£    %        ã            display@14007000              mediatek,mt8195-mdp3-tdshp          2     p                
‹   p      p            ã      #      display@14008000              mediatek,mt8195-mdp3-color          2     €                �      I               
‹   p      €            ã      $        Ú   +         display@14009000              mediatek,mt8195-mdp3-ovl            2     �                �      J               
‹   p      �            ã      %        Ú   +           
Ä   r   ‚      display@1400a000              mediatek,mt8195-mdp3-padding            2                      
‹   p                   ã              Ú   +         display@1400b000              mediatek,mt8195-mdp3-tcc            2     °                
‹   p      °            ã            dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         2     À                
‹   p      À            
£    +        ã              
Ä   r   ƒ        Ú   +           
Ë         mutex@1400f000            mediatek,mt8195-vpp-mutex           2     ð                �      P               
‹   p      ð            ã              Ú   +         smi@14010000              mediatek,mt8195-smi-sub-common          2                     ã                          uapb smi gals0           
Ö   s        Ú   +              t      smi@14011000              mediatek,mt8195-smi-sub-common          2                    ã                          uapb smi gals0           
Ö   s        Ú   +              ‘      smi@14012000              mediatek,mt8195-smi-common-vpp          2                      ã                                uapb smi gals0 gals1         Ú   +              s      larb@14013000             mediatek,mt8195-smi-larb            2    0                
ã           
Ö   t        ã                    uapb smi         Ú   +              w      iommu@14018000            mediatek,mt8195-iommu-vpp           2    €              8  
ô   u   v   w   x   y   z   {   |   }   ~      €   �   ‚        �      R               ã              ubclk            ¥           Ú   +              r      clock-controller@14e00000             mediatek,mt8195-wpesys          2    à                 Ö                    clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         2    à                 Ö         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         2    à0                Ö         larb@14e04000             mediatek,mt8195-smi-larb            2    à@                
ã           
Ö   ƒ        ã                    uapb smi         Ú   +              ¤      larb@14e05000             mediatek,mt8195-smi-larb            2    àP                
ã           
Ö   s        ã                          uapb smi gals            Ú   +              y      syscon@14f00000           mediatek,mt8195-vppsys1 syscon          2    ð                 Ö           
‹   p   	                        mutex@14f01000            mediatek,mt8195-vpp-mutex           2    ð                �      {               
‹   p   	              ã      '        Ú   +         larb@14f02000             mediatek,mt8195-smi-larb            2    ð                 
ã           
Ö   ƒ        ã                          uapb smi gals            Ú   +              £      larb@14f03000             mediatek,mt8195-smi-larb            2    ð0                
ã           
Ö   t        ã                          uapb smi gals            Ú   +              x      display@14f06000              mediatek,mt8195-mdp3-split          2    ð`                
‹   p   	  `            ã            +      ,        Ú   +         display@14f07000              mediatek,mt8195-mdp3-tcc            2    ðp                
‹   p   	  p            ã            dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           2    ð€                
‹   p   	  €            
£  „  ¨        ã              
Ä   „            Ú   +           
Ë         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           2    ð�                
‹   p   	  �            
£  …  ©        ã      
        
Ä   „   ¤        Ú   +           
Ë         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           2    ð                 
‹   p   	               
£  †  ª        ã              
Ä   r   À        Ú   +           
Ë         display@14f0b000              mediatek,mt8195-mdp3-fg         2    ð°                
‹   p   	  °            ã      	      display@14f0c000              mediatek,mt8195-mdp3-fg         2    ðÀ                
‹   p   	  À            ã            display@14f0d000              mediatek,mt8195-mdp3-fg         2    ðÐ                
‹   p   	  Ð            ã            display@14f0e000              mediatek,mt8195-mdp3-hdr            2    ðà                
‹   p   	  à            ã            display@14f0f000              mediatek,mt8195-mdp3-hdr            2    ðð                
‹   p   	  ð            ã            display@14f10000              mediatek,mt8195-mdp3-hdr            2    ñ                 
‹   p   
               ã             display@14f11000              mediatek,mt8195-mdp3-aal            2    ñ                �      i               
‹   p   
              ã              Ú   +         display@14f12000              mediatek,mt8195-mdp3-aal            2    ñ                 �      j               
‹   p   
               ã              Ú   +         display@14f13000              mediatek,mt8195-mdp3-aal            2    ñ0                �      k               
‹   p   
  0            ã      !        Ú   +         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           2    ñ@                
‹   p   
  @            
£  �  ¯        ã            display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           2    ñP                
‹   p   
  P            
£  ‘  °        ã      $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           2    ñ`                
‹   p   
  `            
£  ’  ±        ã      %      display@14f17000              mediatek,mt8195-mdp3-tdshp          2    ñp                
‹   p   
  p            ã            display@14f18000              mediatek,mt8195-mdp3-tdshp          2    ñ€                
‹   p   
  €            ã      (      display@14f19000              mediatek,mt8195-mdp3-tdshp          2    ñ�                
‹   p   
  �            ã      )      display@14f1a000              mediatek,mt8195-mdp3-merge          2    ñ                 
‹   p   
               ã              Ú   +         display@14f1b000              mediatek,mt8195-mdp3-merge          2    ñ°                
‹   p   
  °            ã              Ú   +         display@14f1c000              mediatek,mt8195-mdp3-color          2    ñÀ                �      t               
‹   p   
  À            ã              Ú   +         display@14f1d000              mediatek,mt8195-mdp3-color          2    ñÐ                
‹   p   
  Ð            �      u               ã              Ú   +         display@14f1e000              mediatek,mt8195-mdp3-color          2    ñà                �      v               
‹   p   
  à            ã              Ú   +         display@14f1f000              mediatek,mt8195-mdp3-ovl            2    ñð                �      w               
‹   p   
  ð            ã               Ú   +           
Ä   „   ¢      display@14f20000              mediatek,mt8195-mdp3-padding            2    ò                 
‹   p                  ã              Ú   +         display@14f21000              mediatek,mt8195-mdp3-padding            2    ò                
‹   p                 ã              Ú   +         display@14f22000              mediatek,mt8195-mdp3-padding            2    ò                 
‹   p                  ã              Ú   +         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         2    ò0                
‹   p     0            
£  Ÿ  «        ã              
Ä   „   £        Ú   +           
Ë         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         2    ò@                
‹   p     @            
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Ä   „   ¦        Ú   +           
Ë         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         2    òP                
‹   p     P            
£  ¡  ­        ã              
Ä   r   Â        Ú   +           
Ë         clock-controller@15000000             mediatek,mt8195-imgsys          2                      Ö              $      larb@15001000             mediatek,mt8195-smi-larb            2                     
ã   	        
Ö   …        ã   $       $       $   
        uapb smi gals            Ú   +              ¥      smi@15002000              mediatek,mt8195-smi-sub-common          2                      ã   $      $                 uapb smi gals0           
Ö   s        Ú   +              ˆ      smi@15003000              mediatek,mt8195-smi-sub-common          2     0                ã   $       $       $   
        uapb smi gals0           
Ö   ƒ        Ú   +              …      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         2                     Ö              †      larb@15120000             mediatek,mt8195-smi-larb            2                     
ã   
        
Ö   …        ã   $      †            uapb smi         Ú   +              ¦      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          2                     Ö         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         2    "                 Ö              ‡      larb@15230000             mediatek,mt8195-smi-larb            2    #                 
ã           
Ö   …        ã   $      ‡            uapb smi         Ú   +              §      clock-controller@15330000             mediatek,mt8195-ipesys          2    3                 Ö              %      larb@15340000             mediatek,mt8195-smi-larb            2    4                 
ã           
Ö   ˆ        ã   %      %           uapb smi         Ú   +              z      clock-controller@16000000             mediatek,mt8195-camsys          2                      Ö              &      larb@16001000             mediatek,mt8195-smi-larb            2                     
ã           
Ö   ‰        ã   &       &       &           uapb smi gals            Ú   +              ¨      larb@16002000             mediatek,mt8195-smi-larb            2                      
ã           
Ö   Š        ã   &      &           uapb smi         Ú   +              {      smi@16004000              mediatek,mt8195-smi-sub-common          2     @                ã   &       &       &           uapb smi gals0           
Ö   ƒ        Ú   +              ‰      smi@16005000              mediatek,mt8195-smi-sub-common          2     P                ã   &      &                 uapb smi gals0           
Ö   s        Ú   +              Š      larb@16012000             mediatek,mt8195-smi-larb            2                     
ã           
Ö   Š        ã   ‹       ‹            uapb smi         Ú   +               |      larb@16013000             mediatek,mt8195-smi-larb            2    0                
ã           
Ö   ‰        ã   Œ       Œ            uapb smi         Ú   +               ©      larb@16014000             mediatek,mt8195-smi-larb            2    @                
ã           
Ö   Š        ã   �       �            uapb smi         Ú   +   !           ‚      larb@16015000             mediatek,mt8195-smi-larb            2    P                
ã           
Ö   ‰        ã   Ž       Ž            uapb smi         Ú   +   !           ®      clock-controller@1604f000             mediatek,mt8195-camsys_rawa         2    ð                Ö              ‹      clock-controller@1606f000             mediatek,mt8195-camsys_yuva         2    ð                Ö              Œ      clock-controller@1608f000             mediatek,mt8195-camsys_rawb         2    ð                Ö              �      clock-controller@160af000             mediatek,mt8195-camsys_yuvb         2    
ð                Ö              Ž      clock-controller@16140000             mediatek,mt8195-camsys_mraw         2                     Ö              �      larb@16141000             mediatek,mt8195-smi-larb            2                    
ã           
Ö   ‰        ã   &       �       &           uapb smi gals            Ú   +   "           ­      larb@16142000             mediatek,mt8195-smi-larb            2                     
ã           
Ö   Š        ã   �       �            uapb smi         Ú   +   "           �      clock-controller@17200000             mediatek,mt8195-ccusys          2                      Ö              �      larb@17201000             mediatek,mt8195-smi-larb            2                     
ã           
Ö   Š        ã   �       �            uapb smi         Ú   +              }      video-codec@18000000              mediatek,mt8195-vcodec-dec          
·   q        
Ä   „                        +            2                   @                L                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         2                       
Ä   r  à   r  á         ã      A                  �        usel vdec lat top            «      A        »      �        Ú   +         video-codec@10000             mediatek,mtk-vcodec-lat         2                      �      Ä             0  
Ä   „      „     „     „     „     „           ã      A                  �        usel vdec lat top            «      A        »      �        Ú   +         video-codec@25000             mediatek,mtk-vcodec-core            2     P                �      Ã             P  
Ä   „      „  ¡   „  ¢   „  £   „  ¤   „  ¥   „  ¦   „  §   „  ¨   „  ©         ã      A                  �        usel vdec lat top            «      A        »      �        Ú   +            larb@1800d000             mediatek,mt8195-smi-larb            2     Ð                
ã           
Ö   ƒ        ã                      uapb smi         Ú   +              ¬      larb@1800e000             mediatek,mt8195-smi-larb            2     à                
ã           
Ö   ‘        ã                     uapb smi         Ú   +              €      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         2     ð                Ö                    larb@1802e000             mediatek,mt8195-smi-larb            2    à                
ã           
Ö   ƒ        ã                      uapb smi         Ú   +              «      clock-controller@1802f000             mediatek,mt8195-vdecsys         2    ð                Ö                    larb@1803e000             mediatek,mt8195-smi-larb            2    à                
ã           
Ö   ‘        ã                      uapb smi         Ú   +                    clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           2    ð                Ö                     clock-controller@190f3000             mediatek,mt8195-apusys_pll          2    0                Ö         clock-controller@1a000000             mediatek,mt8195-vencsys         2                      Ö              !      larb@1a010000             mediatek,mt8195-smi-larb            2                     
ã           
Ö   ƒ        ã   !      !           uapb smi         Ú   +              ª      video-codec@1a020000              mediatek,mt8195-vcodec-enc          2                   H  
Ä   „  `   „  a   „  b   „  c   „  d   „  v   „  w   „  x   „  y        �      U               
·   q        ã   !         	  uvenc_sel            «      @        »      �        Ú   +                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec          Ú   +         0  
Ä   „  m   „  n   „  r   „  s   „  t   „  u                     +         0  L                                            jpgdec@0,0            mediatek,mt8195-jpgdec-hw           2                     0  
Ä   „  m   „  n   „  r   „  s   „  t   „  u        �      W               ã   !           ujpgdec          Ú   +         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw           2                    0  
Ä   „  m   „  n   „  r   „  s   „  t   „  u        �      X               ã   !           ujpgdec          Ú   +         jpgdec@1,0            mediatek,mt8195-jpgdec-hw           2                    0  
Ä   r  �   r  Ž   r  ’   r  “   r  ”   r  •        �      \               ã   "           ujpgdec          Ú   +            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           2                      Ö              "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            2                     ó   ’               Ö           
‹   ’                           jpeg-encoder@1a030000             mediatek,mt8195-jpgenc          Ú   +            
Ä   r  ‡   r  ˆ   r  ‰   r  Œ                     +         0  L                                            jpgenc@0,0            mediatek,mt8195-jpgenc-hw           2                        
Ä   „  g   „  h   „  i   „  l        �      V               ã   !           ujpgenc          Ú   +         jpgenc@1,0            mediatek,mt8195-jpgenc-hw           2                       
Ä   r  ‡   r  ˆ   r  ‰   r  Œ        �      [               ã   "           ujpgenc          Ú   +            larb@1b010000             mediatek,mt8195-smi-larb            2                     
ã           
Ö   s        ã   "      "                  uapb smi gals            Ú   +              ~      ovl@1c000000              mediatek,mt8195-disp-ovl            2                      �      |               Ú   +           ã               
Ä   „           
‹   ’             ports                        +       port@0          2       endpoint             port@1          2      endpoint               “           ”               rdma@1c002000             mediatek,mt8195-disp-rdma           2                      �      ~               Ú   +           ã              
Ä   „            
‹   ’             ports                        +       port@0          2       endpoint               ”           “         port@1          2      endpoint               •           –               color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           2     0                �                     Ú   +           ã              
‹   ’     0       ports                        +       port@0          2       endpoint               –           •         port@1          2      endpoint               —           ˜               ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           2     @                �      €               Ú   +           ã              
‹   ’     @       ports                        +       port@0          2       endpoint               ˜           —         port@1          2      endpoint               ™           š               aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           2     P                �      �               Ú   +           ã              
‹   ’     P       ports                        +       port@0          2       endpoint               š           ™         port@1          2      endpoint               ›           œ               gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           2     `                �      ‚               Ú   +           ã              
‹   ’     `       ports                        +       port@0          2       endpoint               œ           ›         port@1          2      endpoint               �           ž               dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         2     p                �      ƒ               Ú   +           ã      	        
‹   ’     p       ports                        +       port@0          2       endpoint               ž           �         port@1          2      endpoint                   dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         2     €                �      „               Ú   +           ã            *   Ÿ        uengine digital hs           @   Ÿ        	ªdphy          	   disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            2     �                �      …               Ú   +           ã              
‹   ’     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         2                     �      Ž               Ú   +           ã            +            uengine digital hs           @            	ªdphy          	   disabled          merge@1c014000            mediatek,mt8195-disp-merge          2    @                �      �               Ú   +           ã              
‹   ’     @          dp-intf@1c015000              mediatek,mt8195-dp-intf         2    P                �      ‘               Ú   +           ã      ,                    upixel engine pll          	   disabled          mutex@1c016000            mediatek,mt8195-disp-mutex          2    `                �      ’               Ú   +           ã              
‹   ’     `            
£  U      larb@1c018000             mediatek,mt8195-smi-larb            2    €                
ã            
Ö   ƒ        ã      (      (              uapb smi gals            Ú   +              ¡      larb@1c019000             mediatek,mt8195-smi-larb            2    �                
ã           
Ö   s        ã      (                     uapb smi gals            Ú   +              u      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          2                     ó   ’              
‹   ’                  Ö           ¤              #      smi@1c01b000              mediatek,mt8195-smi-common-vdo          2    °                 ã      %      &      )      $        uapb smi gals0 gals1         Ú   +              ƒ      iommu@1c01f000            mediatek,mt8195-iommu-vdo           2    ð              8  
ô   ¡   ¢   £   ¤   ¥   ¦   §   ¨   ©   ª   «   ¬   ­   ®        �      �               ¥           ã      '        ubclk            Ú   +              „      mutex@1c101000            mediatek,mt8195-disp-mutex          2                    �      î               Ú   +           ã   #           
‹   ’                 
£  À      larb@1c102000             mediatek,mt8195-smi-larb            2                     
ã           
Ö   ƒ        ã   #       #       #           uapb smi gals            Ú   +              ¢      larb@1c103000             mediatek,mt8195-smi-larb            2    0                
ã           
Ö   s        ã   #      #                  uapb smi gals            Ú   +              v      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           2    @                �      ï               ã   #           Ú   +           
Ä   „   @        
‹   ’     @            
Ë         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           2    P                �      ð               ã   #           Ú   +           
Ä   r   `        
‹   ’     P            
Ë         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           2    `                �      ñ               ã   #           Ú   +           
Ä   „   A        
‹   ’     `            
Ë         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           2    p                �      ò               ã   #           Ú   +           
Ä   r   a        
‹   ’     p            
Ë         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           2    €                �      ó               ã   #           Ú   +           
Ä   „   B        
‹   ’     €            
Ë         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           2    �                �      ô               ã   #           Ú   +           
Ä   r   b        
‹   ’     �            
Ë         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           2                     �      õ               ã   #           Ú   +           
Ä   „   C        
‹   ’                  
Ë         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           2    °                �      ö               ã   #           Ú   +           
Ä   r   c        
‹   ’     °            
Ë         vpp-merge@1c10c000            mediatek,mt8195-disp-merge          2    À                �      ÷               ã   #   	   #           umerge merge_async           Ú   +           
‹   ’     À                        #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          2    Ð                �      ø               ã   #   
   #           umerge merge_async           Ú   +           
‹   ’     Ð                        #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          2    à                �      ù               ã   #      #           umerge merge_async           Ú   +           
‹   ’     à                        #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          2    ð                �      ú               ã   #      #           umerge merge_async           Ú   +           
‹   ’     ð                        #         vpp-merge@1c110000            mediatek,mt8195-disp-merge          2                     �      û               ã   #      #           umerge merge_async           Ú   +           
‹   ’                   '           #         dpi@1c112000              mediatek,mt8195-dpi         2                     ã   #   -   #      #   2        upixel engine pll            �                      Ú   +              #         	   disabled       ports                        +       port@0          2       endpoint             port@1          2      endpoint                   dp-intf@1c113000              mediatek,mt8195-dp-intf         2    0                �                     Ú   +           ã   #   /   #                 upixel engine pll          	   disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  2    @            P            p            �                         °            À              4  ±mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  
‹   ’     @       ’     P       ’     p       ’     �       ’             ’     °       ’     À          h  ã   #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *            ƒ  umixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          Ú   +           
Ä   r   d   r   e        �                   (     #   3   #   4   #   5   #   6   #   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx         Ò           2    0                  ã      Q      L      M      ,        ubus hdcp hdcp24m hdmi-split         «      L        »      “        �      ¥               Ú   +           @   ¯        	ªhdmi          	   disabled       i2c           mediatek,mt8195-hdmi-ddc            ã         ports                        +       port@0          2       endpoint             port@1          2      endpoint                   edp-tx@1c500000           mediatek,mt8195-edp-tx          2    P        €         m   °        ydp_calibration_data         Ú   +           �      ¤               >  ¤      	   disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx           2    `        €         m   °        ydp_calibration_data         Ú   +           �      Ê               >  ¤      	   disabled             thermal-zones      cpu0-thermal            O  è        ]   ú        s   ±      trips      trip-alert          ƒ L        �  Ð        -passive            ²      trip-crit           ƒ †         �  Ð      	  -critical             cooling-maps       map0            š   ²      0  Ÿ   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            O  è        ]   ú        s   ±      trips      trip-alert          ƒ L        �  Ð        -passive            ³      trip-crit           ƒ †         �  Ð      	  -critical             cooling-maps       map0            š   ³      0  Ÿ   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            O  è        ]   ú        s   ±      trips      trip-alert          ƒ L        �  Ð        -passive            ´      trip-crit           ƒ †         �  Ð      	  -critical             cooling-maps       map0            š   ´      0  Ÿ   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            O  è        ]   ú        s   ±      trips      trip-alert          ƒ L        �  Ð        -passive            µ      trip-crit           ƒ †         �  Ð      	  -critical             cooling-maps       map0            š   µ      0  Ÿ   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            O  è        ]   ú        s   ±       trips      trip-alert          ƒ L        �  Ð        -passive            ¶      trip-crit           ƒ †         �  Ð      	  -critical             cooling-maps       map0            š   ¶      0  Ÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            O  è        ]   ú        s   ±      trips      trip-alert          ƒ L        �  Ð        -passive            ·      trip-crit           ƒ †         �  Ð      	  -critical             cooling-maps       map0            š   ·      0  Ÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            O  è        ]   ú        s   ±      trips      trip-alert          ƒ L        �  Ð        -passive            ¸      trip-crit           ƒ †         �  Ð      	  -critical             cooling-maps       map0            š   ¸      0  Ÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            O  è        ]   ú        s   ±      trips      trip-alert          ƒ L        �  Ð        -passive            ¹      trip-crit           ƒ †         �  Ð      	  -critical             cooling-maps       map0            š   ¹      0  Ÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            O  è        ]   ú        s   º      trips      trip-alert          ƒ L        �  Ð        -passive       trip-crit           ƒ †         �  Ð      	  -critical                vpu1-thermal            O  è        ]   ú        s   º   	   trips      trip-alert          ƒ L        �  Ð        -passive       trip-crit           ƒ †         �  Ð      	  -critical                gpu-thermal         O  è        ]   ú        s   º   
   trips      trip-alert          ƒ L        �  Ð        -passive       trip-crit           ƒ †         �  Ð      	  -critical                gpu1-thermal            O  è        ]   ú        s   º      trips      trip-alert          ƒ L        �  Ð        -passive       trip-crit           ƒ †         �  Ð      	  -critical                vdec-thermal            O  è        ]   ú        s   º      trips      trip-alert          ƒ L        �  Ð        -passive       trip-crit           ƒ †         �  Ð      	  -critical                img-thermal         O  è        ]   ú        s   º      trips      trip-alert          ƒ L        �  Ð        -passive       trip-crit           ƒ †         �  Ð      	  -critical                infra-thermal           O  è        ]   ú        s   º      trips      trip-alert          ƒ L        �  Ð        -passive       trip-crit           ƒ †         �  Ð      	  -critical                cam0-thermal            O  è        ]   ú        s   º      trips      trip-alert          ƒ L        �  Ð        -passive       trip-crit           ƒ †         �  Ð      	  -critical                cam1-thermal            O  è        ]   ú        s   º      trips      trip-alert          ƒ L        �  Ð        -passive       trip-crit           ƒ †         �  Ð      	  -critical                cpu-thermal         O  è        ]            s   »   trips      trip-alert          ƒ L        �  Ð        -passive       trip-crit           ƒ s        �  Ð      	  -critical                pcb-top-thermal         O  è        ]            s   ¼   trips      trip-alert          ƒ $ø        �  Ð        -passive       trip-crit           ƒ L        �  Ð      	  -critical                pcb-bottom-thermal          O  è        ]            s   ½   trips      trip-alert          ƒ $ø        �  Ð        -passive       trip-crit           ƒ L        �  Ð      	  -critical                   chosen          ®serial0:115200n8          firmware       optee             linaro,optee-tz         =smc          gpio-keys         
    gpio-keys           default         -   ¾   key-0           |      j         
  ºvolume_up           À   s         E        Ë            leds          
    gpio-leds           default         -   ¿   led-0           |      k            Ýkeep            ëpower           ô            memory@40000000         &memory          2    @       €         regulator-vsys            regulator-fixed         	vsys             d         ú         LK@        0 LK@           Y      reserved-memory                      +            L   optee@43200000                   2    C        À        memory@50000000           shared-dma-pool         2    P       �                      )      memory@53000000           shared-dma-pool         2    S       @        memory@54600000                  2    T`                memory@60000000           shared-dma-pool         2    `                        memory@62000000           shared-dma-pool         2    b       @           thermal-sensor-0              generic-adc-thermal         Š               À            sensor-channel          0ÿÿžX  Âÿÿ±à  ^ÿÿÅh  ìÿÿØð  nÿÿìx  ì      j  ˆ  î  '  {  :˜    N   »  a¨  o  u0  /  ˆ¸   ú  œ@   Î  ¯È   ª  ÃP   �  ÖØ   u  ê`   a  ýè   Q p   D $ø   9 8€   0 L   ) _�   # s    †     š(    ­°    Á8    ÔÀ    èH    ûÐ   
 X   	 "à    6h    Ið              »      thermal-sensor-1              generic-adc-thermal         Š               À           sensor-channel          0ÿÿžX  Âÿÿ±à  ^ÿÿÅh  ìÿÿØð  nÿÿìx  ì      j  ˆ  î  '  {  :˜    N   »  a¨  o  u0  /  ˆ¸   ú  œ@   Î  ¯È   ª  ÃP   �  ÖØ   u  ê`   a  ýè   Q p   D $ø   9 8€   0 L   ) _�   # s    †     š(    ­°    Á8    ÔÀ    èH    ûÐ   
 X   	 "à    6h    Ið              ¼      thermal-sensor-2              generic-adc-thermal         Š               À           sensor-channel          0ÿÿžX  Âÿÿ±à  ^ÿÿÅh  ìÿÿØð  nÿÿìx  ì      j  ˆ  î  '  {  :˜    N   »  a¨  o  u0  /  ˆ¸   ú  œ@   Î  ¯È   ª  ÃP   �  ÖØ   u  ê`   a  ýè   Q p   D $ø   9 8€   0 L   ) _�   # s    †     š(    ­°    Á8    ÔÀ    èH    ûÐ   
 X   	 "à    6h    Ið              ½         	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 mmc0 mmc1 serial0 serial1 serial2 serial3 serial4 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux drive-strength input-enable output-high input-disable bias-disable bias-pull-up drive-strength-microamp bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 uart-has-rtscts mediatek,pad-select spi-max-frequency nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,mac-wol reset-assert-us reset-deassert-us reset-gpios snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup dr_mode vusb33-supply bus-width hs400-ds-delay cap-mmc-highspeed cap-mmc-hw-reset mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable vmmc-supply vqmmc-supply cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc freq-table-hz mediatek,ufs-disable-mcq mediatek,u3p-dis-msk bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-rx-bus-width spi-tx-bus-width bits #phy-cells LDO_VIN1-supply LDO_VIN2-supply LDO_VIN3-supply mediatek,ibias mediatek,ibias_up operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path label linux,code debounce-interval default-state function color regulator-boot-on no-map io-channels io-channel-names temperature-lookup-table 