Ðþí  i»   8  c°   (              cx                                  ARM Juno development board (r0)          arm,juno arm,vexpress                        "            1      clock-7372800            fixed-clock          =             J p€          Zjuno:uartclk             m   D      clock-48000000           fixed-clock          =             JÜl       	   Zclk48mhz             m   H      clock-50000000           fixed-clock          =             Júð€         Zsmc_clk          m   	      clock-100000000          fixed-clock          =             Jõá       	   Zapb_pclk             m   
      clock-400000000          fixed-clock          =             J×„       	   Zfaxi_clk             m   >      clock-24000000           fixed-clock          =             Jn6          Zjuno_mb:clk24mhz             m         clock-25000000           fixed-clock          =             J}x@         Zjuno_mb:clk25mhz             m         clock-1000000            fixed-clock          =             J B@         Zjuno_mb:refclk1mhz           m         clock-32768          fixed-clock          =             J  €          Zjuno_mb:refclk32khz          m         regulator-3v3            regulator-fixed          uMCC_SB_3V3           „ 2Z          œ 2Z           ´         m         gpio-keys         
   gpio-keys      power-button             È   2          Ú         è   t         óPOWER            ù                home-button          È   2          Ú         è   f         óHOME             ù               rlock-button             È   2          Ú         è   ˜         óRLOCK            ù               vol-up-button            È   2          Ú         è   s         óVOL+             ù               vol-down-button          È   2          Ú         è   r         óVOL-             ù               nmi-button           È   2          Ú         è   c         óNMI          ù                  bus@8000000          simple-bus           "            1            ÿ                                                       *                          D                            E                            F                                                         ¡                            ¢                            £                            ¤                            ¥              	              ¦              
              §                            ¨                            ©      motherboard-bus@8000000          arm,vexpress,v2p-p1 simple-bus           "            1         x   ÿ                                                                                                               8  R        @       flash@0          arm,vexpress-flash cfi-flash            R                   V         	  adisabled       partitions           arm,arm-firmware-suite           ethernet@200000000           smsc,lan9118 smsc,lan9115           R                  h           smii         |            ‰         ž        ±           ¸           Æ         iofpga-bus@300000000             simple-bus           "            1            ÿ                  sysctl@20000             arm,sp810 arm,primecell         R              ±                 Örefclk timclk apb_pclk           =         0   Ztimerclken0 timerclken1 timerclken2 timerclken3          â                                 ò                     m         apbregs@10000         )   arm,juno-fpga-apb-regs syscon simple-mfd            R               ÿ                   "            1      led@8,0          register-bit-led            R              	           %            óvexpress:0        
  heartbeat           &on        led@8,1          register-bit-led            R              	           %            óvexpress:1          mmc0            &off       led@8,2          register-bit-led            R              	           %            óvexpress:2          cpu0            &off       led@8,3          register-bit-led            R              	           %            óvexpress:3          cpu1            &off       led@8,4          register-bit-led            R              	           %            óvexpress:4          cpu2            &off       led@8,5          register-bit-led            R              	           %             óvexpress:5          cpu3            &off       led@8,6          register-bit-led            R              	           %   @         óvexpress:6          &off       led@8,7          register-bit-led            R              	           %   €         óvexpress:7          &off          mmc@50000            arm,pl180 arm,primecell         R              h           4 ·         B           ±      	        Ömclk apb_pclk         kmi@60000            arm,pl050 arm,primecell         R              h           ±      	        ÖKMIREFCLK apb_pclk        kmi@70000            arm,pl050 arm,primecell         R              h           ±      	        ÖKMIREFCLK apb_pclk        watchdog@f0000           arm,sp805 arm,primecell         R              h           ±      	        Öwdog_clk apb_pclk         timer@110000             arm,sp804 arm,primecell         R              h   	        ±                        Ötimclken1 timclken2 apb_pclk          timer@120000             arm,sp804 arm,primecell         R              h   	        ±                       Ötimclken1 timclken2 apb_pclk          rtc@170000           arm,pl031 arm,primecell         R              h            ±   	      	  Öapb_pclk          gpio@1d0000          arm,pl061 arm,primecell         R              h           ±   	      	  Öapb_pclk             N        ^            j                    m                  timer@2a810000           arm,armv7-timer-mem         R    *�                  "            1            ÿ        *‚           	  adisabled       frame@2a830000                     h       <           R               mhu@2b1f0000             arm,mhu arm,primecell           R    +               $  h       $          #          %           Œ           ±   
      	  Öapb_pclk             m   :      iommu@2b400000           arm,mmu-400 arm,smmu-v1         R    +@                 h       &          &           ˜           ¥           ¸               Æ      	  adisabled          iommu@2b500000           arm,mmu-401 arm,smmu-v1         R    +P                 h       (          (           ˜           ¥            Æ      	  adisabled             m   9      iommu@2b600000           arm,mmu-401 arm,smmu-v1         R    +`                 h       *          *           ˜           ¥            Æ        ¸                m         interrupt-controller@2c010000            arm,gic-400 arm,cortex-a15-gic        @  R    ,             ,ð             ,ð             ,ð                  "                       1            j        h      	  ?         ÿ        ,              m      v2m@0            arm,gic-v2m-frame            Ó        R                m   8      v2m@10000            arm,gic-v2m-frame            Ó        R            v2m@20000            arm,gic-v2m-frame            Ó        R            v2m@30000            arm,gic-v2m-frame            Ó        R               timer            arm,armv8-timer       0  h        ?        ?        ?      
  ?      etf@20010000              arm,coresight-tmc arm,primecell         R                      ±   	      	  Öapb_pclk            ¸                m   4   in-ports       port       endpoint            â            m               out-ports      port       endpoint            â            m                  tpiu@20030000         !   arm,coresight-tpiu arm,primecell            R                      ±   	      	  Öapb_pclk            ¸                m   6   in-ports       port       endpoint            â            m                  funnel@20040000       +   arm,coresight-dynamic-funnel arm,primecell          R                      ±   	      	  Öapb_pclk            ¸          out-ports      port       endpoint            â            m               in-ports             "            1       port@0          R       endpoint            â            m            port@1          R      endpoint            â            m   %         port@2          R      endpoint            â            m                  etr@20070000              arm,coresight-tmc arm,primecell         R                      ò               ±   	      	  Öapb_pclk            ¸                ù         m   3   in-ports       port       endpoint            â            m                  stm@20100000              arm,coresight-stm arm,primecell          R                  (                  stm-base stm-stimulus-base          ±   	      	  Öapb_pclk            ¸                m   5   out-ports      port       endpoint            â            m                  replicator@20120000       /   arm,coresight-dynamic-replicator arm,primecell          R                      ±   	      	  Öapb_pclk            ¸          out-ports            "            1       port@0          R       endpoint            â            m            port@1          R      endpoint            â            m               in-ports       port       endpoint            â            m                  cpu-debug@22010000        &   arm,coresight-cpu-debug arm,primecell           R    "                 ±   	      	  Öapb_pclk            ¸                        etm@22040000          "   arm,coresight-etm4x arm,primecell           R    "                 ±   	      	  Öapb_pclk            ¸                           m      out-ports      port       endpoint            â            m                  cti@22020000          :   arm,coresight-cti-v8-arch arm,coresight-cti arm,primecell           R    "                 ±   	      	  Öapb_pclk            ¸                                   funnel@220c0000       +   arm,coresight-dynamic-funnel arm,primecell          R    "                 ±   	      	  Öapb_pclk            ¸          out-ports      port       endpoint            â            m               in-ports             "            1       port@0          R       endpoint            â            m            port@1          R      endpoint            â            m                   cpu-debug@22110000        &   arm,coresight-cpu-debug arm,primecell           R    "                 ±   	      	  Öapb_pclk            ¸                        etm@22140000          "   arm,coresight-etm4x arm,primecell           R    "                 ±   	      	  Öapb_pclk            ¸                           m   !   out-ports      port       endpoint            â             m                  cti@22120000          :   arm,coresight-cti-v8-arch arm,coresight-cti arm,primecell           R    "                 ±   	      	  Öapb_pclk            ¸                  !                 cpu-debug@23010000        &   arm,coresight-cpu-debug arm,primecell           R    #                 ±   	      	  Öapb_pclk            ¸                  "      etm@23040000          "   arm,coresight-etm4x arm,primecell           R    #                 ±   	      	  Öapb_pclk            ¸                  "         m   $   out-ports      port       endpoint            â   #         m   &               cti@23020000          :   arm,coresight-cti-v8-arch arm,coresight-cti arm,primecell           R    #                 ±   	      	  Öapb_pclk            ¸                  $           "      funnel@230c0000       +   arm,coresight-dynamic-funnel arm,primecell          R    #                 ±   	      	  Öapb_pclk            ¸          out-ports      port       endpoint            â   %         m               in-ports             "            1       port@0          R       endpoint            â   &         m   #         port@1          R      endpoint            â   '         m   +         port@2          R      endpoint            â   (         m   .         port@3          R      endpoint            â   )         m   1               cpu-debug@23110000        &   arm,coresight-cpu-debug arm,primecell           R    #                 ±   	      	  Öapb_pclk            ¸                  *      etm@23140000          "   arm,coresight-etm4x arm,primecell           R    #                 ±   	      	  Öapb_pclk            ¸                  *         m   ,   out-ports      port       endpoint            â   +         m   '               cti@23120000          :   arm,coresight-cti-v8-arch arm,coresight-cti arm,primecell           R    #                 ±   	      	  Öapb_pclk            ¸                  ,           *      cpu-debug@23210000        &   arm,coresight-cpu-debug arm,primecell           R    #!                 ±   	      	  Öapb_pclk            ¸                  -      etm@23240000          "   arm,coresight-etm4x arm,primecell           R    #$                 ±   	      	  Öapb_pclk            ¸                  -         m   /   out-ports      port       endpoint            â   .         m   (               cti@23220000          :   arm,coresight-cti-v8-arch arm,coresight-cti arm,primecell           R    #"                 ±   	      	  Öapb_pclk            ¸                  /           -      cpu-debug@23310000        &   arm,coresight-cpu-debug arm,primecell           R    #1                 ±   	      	  Öapb_pclk            ¸                  0      etm@23340000          "   arm,coresight-etm4x arm,primecell           R    #4                 ±   	      	  Öapb_pclk            ¸                  0         m   2   out-ports      port       endpoint            â   1         m   )               cti@23320000          :   arm,coresight-cti-v8-arch arm,coresight-cti arm,primecell           R    #2                 ±   	      	  Öapb_pclk            ¸                  2           0      cti@20020000              arm,coresight-cti arm,primecell         R                      ±   	      	  Öapb_pclk            ¸                "            1       trig-conns@0            R            +              <              N               `                 3      trig-conns@1            R           +               <              N              `                 4      trig-conns@2            R           +                    <                    N              `                 5      trig-conns@3            R           N              `                 6         cti@20110000              arm,coresight-cti arm,primecell         R                      ±   	      	  Öapb_pclk            ¸                "            1       trig-conns@0            R            +            <           N            `           ssys_profiler          trig-conns@1            R           N              `            	  swatchdog          trig-conns@2            R           N              `            
  sg_counter            gpu@2d000000             arm,juno-mali arm,mali-t624         R    -                $  h       !          "                      †job mmu gpu         ±   7           ¸               Æ      sram@2e000000            arm,juno-sram-ns mmio-sram          R    .         €          "            1            ÿ        .     €    scp-sram@0           arm,juno-scp-shmem          R             scp-sram@200             arm,juno-scp-shmem          R               m   ;         pcie@40000000         <   arm,juno-r1-pcie plda,xpressrich3-axi pci-host-ecam-generic         –pci         R    @                  ¢       ÿ        ¬             "            1            Æ      T   ÿ               _€       €         P       P          B      @       @                 8  ½       €       €       €   C                                                                �  *                             ˆ                                ‰                                Š                                ‹           È   8      	  adisabled            Ó            â       9             scpi          	   arm,scpi            ì   :           ó   ;   clocks           arm,scpi-clocks    clocks-0             arm,scpi-dvfs-clocks             =           ù                   Zatlclk aplclk gpuclk             m   7      clocks-1             arm,scpi-variable-clocks             =           ù            Zpxlclk           m   @         power-controller             arm,scpi-power-domains                                 m         sensors          arm,scpi-sensors            '            m   <         thermal-zones      pmic-thermal            =  è        K   d        a   <       trips      trip0           q _�        }  Ð      	  �critical                soc-thermal         =  è        K   d        a   <      trips      trip0           q 8€        }  Ð      	  �critical                big-cl-thermal          =  è        K   d        a   <         	  adisabled          little-cl-thermal           =  è        K   d        a   <         	  adisabled          gpu0-thermal            =  è        K   d        a   <         	  adisabled          gpu1-thermal            =  è        K   d        a   <         	  adisabled             iommu@7fb00000           arm,mmu-401 arm,smmu-v1         R    °                 h       _          _           ˜           ¥            Æ         m   =      iommu@7fb10000           arm,mmu-401 arm,smmu-v1         R    ±                 h       c          c           ˜           ¥            m   ?      iommu@7fb20000           arm,mmu-401 arm,smmu-v1         R    ²                 h       a          a           ˜           ¥            m   B      iommu@7fb30000           arm,mmu-401 arm,smmu-v1         R    ³                 h       e          e           ˜           ¥            Æ         m   G      dma-controller@7ff00000          arm,pl330 arm,primecell         R    ð                 ˆ         l  h       X          Y          Z          [          \          l          m          n          o         H  ò   =       =      =      =      =      =      =      =      =           ±   >      	  Öapb_pclk          hdlcd@7ff50000        
   arm,hdlcd           R    õ                 h       ]           ò   ?            ±   @           Öpxlclk     port       endpoint            â   A         m   F            hdlcd@7ff60000        
   arm,hdlcd           R    ö                 h       U           ò   B            ±   @           Öpxlclk     port       endpoint            â   C         m   E            serial@7ff80000          arm,pl011 arm,primecell         R    ø                 h       S           ±   D   
        Öuartclk apb_pclk          i2c@7ffa0000             snps,designware-i2c         R    ú                  "            1            h       h            J €        “  ô        ±   	   hdmi-transmitter@70          nxp,tda998x         R   p   port       endpoint            â   E         m   C            hdmi-transmitter@71          nxp,tda998x         R   q   port       endpoint            â   F         m   A               usb@7ffb0000             generic-ohci            R    û                 h       t           ò   G            ±   H      usb@7ffc0000             generic-ehci            R    ü                 h       u           ò   G            ±   H      memory-controller@7ffd0000           arm,pl354 arm,primecell         R    ý                 h       V          W           ±   	      	  Öapb_pclk          memory@80000000         –memory           R    €             €      €         tlx-bus@60000000             simple-bus           "            1            ÿ        `                                         *                      ¨         aliases         ¨/serial@7ff80000          chosen          °serial0:115200n8          psci             arm,psci-0.2            ¼smc       cpus             "            1       cpu-map    cluster0       core0                    core1                       cluster1       core0              "      core1              *      core2              -      core3              0            idle-states         Ãpsci       cpu-sleep-0          arm,idle-state          Ð            ç        ø  ,        	  °          Ð         m   J      cluster-sleep-0          arm,idle-state          Ð           ç        ø  �        	  °          	Ä         m   K         cpu@0            arm,cortex-a57          R                –cpu         *psci            8  À         E   @        W           d  €         q   @        ƒ           �   I        ±   7            ¡   J   K        ±           Ä           m         cpu@1            arm,cortex-a57          R               –cpu         *psci            8  À         E   @        W           d  €         q   @        ƒ           �   I        ±   7            ¡   J   K        ±           Ä           m         cpu@100          arm,cortex-a53          R               –cpu         *psci            8  €         E   @        W           d  €         q   @        ƒ   €        �   L        ±   7           ¡   J   K        ±  B        Ä   Œ         m   "      cpu@101          arm,cortex-a53          R              –cpu         *psci            8  €         E   @        W           d  €         q   @        ƒ   €        �   L        ±   7           ¡   J   K        ±  B        Ä   Œ         m   *      cpu@102          arm,cortex-a53          R              –cpu         *psci            8  €         E   @        W           d  €         q   @        ƒ   €        �   L        ±   7           ¡   J   K        ±  B        Ä   Œ         m   -      cpu@103          arm,cortex-a53          R              –cpu         *psci            8  €         E   @        W           d  €         q   @        ƒ   €        �   L        ±   7           ¡   J   K        ±  B        Ä   Œ         m   0      l2-cache0            cache            Þ        :            G   @        Y           ì            m   I      l2-cache1            cache            Þ        :           G   @        Y           ì            m   L         pmu-a57          arm,cortex-a57-pmu          h                            ø            pmu-a53          arm,cortex-a53-pmu        0  h                                                ø   "   *   -   0         	model compatible interrupt-parent #address-cells #size-cells #clock-cells clock-frequency clock-output-names phandle regulator-name regulator-min-microvolt regulator-max-microvolt regulator-always-on debounce-interval wakeup-source linux,code label gpios ranges #interrupt-cells interrupt-map-mask interrupt-map arm,hbi arm,vexpress,site reg bank-width status interrupts phy-mode reg-io-width smsc,irq-active-high smsc,irq-push-pull clocks vdd33a-supply vddvario-supply clock-names assigned-clocks assigned-clock-parents offset linux,default-trigger default-state max-frequency vmmc-supply gpio-controller #gpio-cells interrupt-controller frame-number #mbox-cells #iommu-cells #global-interrupts power-domains dma-coherent msi-controller remote-endpoint iommus arm,scatter-gather reg-names cpu arm,cs-dev-assoc arm,trig-in-sigs arm,trig-in-types arm,trig-out-sigs arm,trig-out-types arm,trig-conn-name interrupt-names device_type bus-range linux,pci-domain dma-ranges msi-parent iommu-map-mask iommu-map mboxes shmem clock-indices num-domains #power-domain-cells #thermal-sensor-cells polling-delay polling-delay-passive thermal-sensors temperature hysteresis #dma-cells i2c-sda-hold-time-ns serial0 stdout-path method entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache cpu-idle-states capacity-dmips-mhz dynamic-power-coefficient cache-unified cache-level interrupt-affinity 