Ðþí  N   8  0   (              
ø                                                                     ,Marvell 8080 board        Z   2marvell,armada-8080-db marvell,armada-8080 marvell,armada-ap810-octa marvell,armada-ap810      aliases           =/soc/bus@e8000000/serial@512000           E/soc/bus@e8000000/serial@512100       psci             2arm,psci-0.2             Msmc       timer            2arm,armv8-timer       0   T                                 
         soc                                   2simple-bus            _   bus@e8000000                                      2simple-bus           _        è                     interrupt-controller@3000000             2arm,gic-v3           f                                      w         T      	             _      (   Œ                                        �      msi-controller@3040000           2arm,gic-v3-its            ˜         §            Œ              �            xor@400000        %   2marvell,armada-7k-xor marvell,xor-v2             Œ @      A              ²                 ½      xor@420000        %   2marvell,armada-7k-xor marvell,xor-v2             Œ B      C              ²      ¡          ½      xor@440000        %   2marvell,armada-7k-xor marvell,xor-v2             Œ D      E              ²      ¢          ½      xor@460000        %   2marvell,armada-7k-xor marvell,xor-v2             Œ F      G              ²      £          ½      serial@512000            2snps,dw-apb-uart             Œ Q              Ê            T                   Ô            áokay             è Ü       serial@512100            2snps,dw-apb-uart             Œ Q!             Ê            T                   Ô         	   ádisabled                cpus                                 cpu@0            øcpu          2arm,cortex-a72           Œ            psci          cpu@1            øcpu          2arm,cortex-a72           Œ           psci          cpu@100          øcpu          2arm,cortex-a72           Œ           psci          cpu@101          øcpu          2arm,cortex-a72           Œ          psci          cpu@200          øcpu          2arm,cortex-a72           Œ           psci          cpu@201          øcpu          2arm,cortex-a72           Œ          psci          cpu@300          øcpu          2arm,cortex-a72           Œ           psci          cpu@301          øcpu          2arm,cortex-a72           Œ          psci             chosen          serial0:115200n8          memory@0             ømemory           Œ            €            	#address-cells #size-cells interrupt-parent model compatible serial0 serial1 method interrupts ranges #interrupt-cells interrupt-controller reg phandle msi-controller #msi-cells msi-parent dma-coherent reg-shift reg-io-width status clock-frequency device_type enable-method stdout-path 