Ðþí Žj   8 @   (            *                              `    google,dojo-sku7 google,dojo-sku5 google,dojo-sku3 google,dojo-sku1 google,dojo mediatek,mt8195                                  +            7HP Dojo (sku 1, 3, 5, 7) board           =convertible    aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/dpi@1c112000            a/soc/mailbox@10320000            f/soc/mailbox@10330000            k/soc/hdmi-tx@1c300000            q/soc/hdr-engine@1c114000             x/soc/mutex@1c016000          /soc/mutex@1c101000          †/soc/vpp-merge@1c10c000          �/soc/vpp-merge@1c10d000          ”/soc/vpp-merge@1c10e000          ›/soc/vpp-merge@1c10f000          ¢/soc/vpp-merge@1c110000          ©/soc/dma-controller@1c104000             ´/soc/dma-controller@1c105000             ¿/soc/dma-controller@1c106000             Ê/soc/dma-controller@1c107000             Õ/soc/dma-controller@1c108000             à/soc/dma-controller@1c109000             ë/soc/dma-controller@1c10a000             ö/soc/dma-controller@1c10b000            /soc/i2c@11e00000           /soc/i2c@11e01000           /soc/i2c@11e02000           /soc/i2c@11e03000           /soc/i2c@11e04000           /soc/i2c@11d00000           /soc/i2c@11d02000           $/soc/mmc@11230000           )/soc/mmc@11240000           ./soc/serial@11001100          cpus                         +       cpu@0           6cpu           arm,cortex-a55          B            Fpsci            T               hec3@        x  4        ‹              ›  €         ¨   @        º   €        Ç  €         Ô   @        æ   €        ó                                          cpu@100         6cpu           arm,cortex-a55          B           Fpsci            T               hec3@        x  4        ‹              ›  €         ¨   @        º   €        Ç  €         Ô   @        æ   €        ó                                          cpu@200         6cpu           arm,cortex-a55          B           Fpsci            T               hec3@        x  4        ‹              ›  €         ¨   @        º   €        Ç  €         Ô   @        æ   €        ó                                          cpu@300         6cpu           arm,cortex-a55          B           Fpsci            T               hec3@        x  4        ‹              ›  €         ¨   @        º   €        Ç  €         Ô   @        æ   €        ó                                          cpu@400         6cpu           arm,cortex-a78          B           Fpsci            T              h�fÔÀ        x           ‹              ›           ¨   @        º           Ç           Ô   @        æ           ó   	                      
                 cpu@500         6cpu           arm,cortex-a78          B           Fpsci            T              h�fÔÀ        x           ‹              ›           ¨   @        º           Ç           Ô   @        æ           ó   	                      
                 cpu@600         6cpu           arm,cortex-a78          B           Fpsci            T              h�fÔÀ        x           ‹              ›           ¨   @        º           Ç           Ô   @        æ           ó   	                      
                 cpu@700         6cpu           arm,cortex-a78          B           Fpsci            T              h�fÔÀ        x           ‹              ›           ¨   @        º           Ç           Ô   @        æ           ó   	                      
                 cpu-map    cluster0       core0           &         core1           &         core2           &         core3           &         core4           &         core5           &         core6           &         core7           &               idle-states         *psci       cpu-retention-l           arm,idle-state          7           N        _   2        p   _        €  D                 cpu-retention-b           arm,idle-state          7           N        _   -        p   Œ        €  ä                 cpu-off-l             arm,idle-state          7          N        _   7        p   ›        €  H                 cpu-off-b             arm,idle-state          7          N        _   2        p   È        €  è                    l2-cache0             cache           ‘           �           ª   @        ¼           ó            �                 l2-cache1             cache           ‘           �           ª   @        ¼           ó            �           	      l3-cache              cache           ‘           �            ª   @        ¼            �                    dsu-pmu           arm,dsu-pmu         «                       ¶                                »fail          dmic-codec            dmic-codec          Â           Ï   2      mt8195-sound            ß           »okay            ñ         }  ÿDL10_FE DPTX_BE ETDM1_IN_BE ETDM2_IN_BE ETDM1_OUT_BE ETDM2_OUT_BE UL_SRC1_BE AFE_SOF_DL2 AFE_SOF_DL3 AFE_SOF_UL4 AFE_SOF_UL5            default                  [  )Headphone HPOL Headphone HPOR IN1P Headset Mic Right Spk Right BE_OUT Left Spk Left BE_OUT        '    mediatek,mt8195_mt6359_max98390_rt5682           7m8195_m98390_5682s     mm-dai-link         7ETDM1_IN_BE         Acpu       hs-playback-dai-link            7ETDM1_OUT_BE            Acpu    codec           W                hs-capture-dai-link         7ETDM2_IN_BE         Acpu    codec           W                spk-playback-dai-link           7ETDM2_OUT_BE            Acpu    codec           W               displayport-dai-link            7DPTX_BE    codec           W               fixed-factor-clock-13m            fixed-factor-clock          a            n           u                      Šclk13m             3      oscillator-26m            fixed-clock         a            hŒº€        Šclk26m                   oscillator-32k            fixed-clock         a            h  €         Šclk32k        performance-controller@11bc10             mediatek,cpufreq-hw          B     ¼            ½0               �                    opp-table-gpu             operating-points-v2          ·           €   opp-390000000           Â    >í€        É 	‰h      opp-410000000           Â    p€        É 	¡Ò      opp-431000000           Â    °‰À        É 	¡Ò      opp-473000000           Â    1h@        É 	º<      opp-515000000           Â    ²FÀ        É 	º<      opp-556000000           Â    !#ã         É 	Ò¦      opp-598000000           Â    #¤Á€        É 	ë      opp-640000000           Â    &%          É 	ë      opp-670000000           Â    'ïc€        É 
ä      opp-700000000           Â    )¹'         É 
L¸      opp-730000000           Â    +‚ê€        É 
}Œ      opp-760000000           Â    -L®         É 
®`      opp-790000000           Â    /q€        É 
ß4      opp-820000000           Â    0à5         É       opp-850000000           Â    2©ø€        É @Ü      opp-880000000           Â    4s¼         É q°         pmu-a55           arm,cortex-a55-pmu                      «                  pmu-a78           arm,cortex-a78-pmu                      «                  psci              arm,psci-1.0            Msmc       timer             arm,armv8-timer                   @  «                                             
             soc                      +             simple-bus           ×        Þ                          interrupt-controller@c000000              arm,gic-v3          é           ú                                 B                                    «      	                &              ppi-partitions     interrupt-partition-0           F                             interrupt-partition-1           F                                   syscon@10000000            mediatek,mt8195-topckgen syscon         B                      a              "      syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          B                     a           O              #      syscon@10003000           mediatek,mt8195-pericfg syscon          B     0                a              I      pinctrl@10005000              mediatek,mt8195-pinctrl       €  B     P            Ñ             Ó             Ô             â             ë             ô              °              B  \iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            f        v           ‚              �                 «       ë               é            Ž        default                 >  ²I2S_SPKR_MCLK I2S_SPKR_DATAIN I2S_SPKR_LRCK I2S_SPKR_BCLK EC_AP_INT_ODL AP_FLASH_WP_L TCHPAD_INT_ODL EDP_HPD_1V8 AP_I2C_CAM_SDA AP_I2C_CAM_SCL AP_I2C_TCHPAD_SDA_1V8 AP_I2C_TCHPAD_SCL_1V8 AP_I2C_AUD_SDA AP_I2C_AUD_SCL AP_I2C_TPM_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 EC_AP_HPD_OD  PCIE_NVME_RST_L PCIE_NVME_CLKREQ_ODL PCIE_RST_1V8_L PCIE_CLKREQ_1V8_ODL PCIE_WAKE_1V8_ODL CLK_24M_CAM0 CAM1_SEN_EN AP_I2C_PWR_SCL_1V8 AP_I2C_PWR_SDA_1V8 AP_I2C_MISC_SCL AP_I2C_MISC_SDA EN_PP5000_HDMI_X AP_HDMITX_HTPLG  AP_HDMITX_SCL_1V8 AP_HDMITX_SDA_1V8 AP_RTC_CLK32K AP_EC_WATCHDOG_L SRCLKENA0 SRCLKENA1 PWRAP_SPI0_CS_L PWRAP_SPI0_CK PWRAP_SPI0_MOSI PWRAP_SPI0_MISO SPMI_SCL SPMI_SDA    I2S_HP_DATAIN I2S_HP_MCLK I2S_HP_BCK I2S_HP_LRCK I2S_HP_DATAOUT SD_CD_ODL EN_PP3300_DISP_X TCHSCR_RST_1V8_L TCHSCR_REPORT_DISABLE EN_PP3300_WLAN_X BT_KILL_1V8_L I2S_SPKR_DATAOUT WIFI_KILL_1V8_L BEEP_ON SCP_I2C_SENSOR_SCL_1V8 SCP_I2C_SENSOR_SDA_1V8     AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_DAT_MISO2 SCP_VREQ_VAO AP_SPI_GSC_TPM_CLK AP_SPI_GSC_TPM_MOSI AP_SPI_GSC_TPM_CS_L AP_SPI_GSC_TPM_MISO EN_PP1000_CAM_X AP_EDP_BKLTEN  USB3_HUB_RST_L  WLAN_ALERT_ODL EC_IN_RW_ODL GSC_AP_INT_ODL HP_INT_ODL CAM0_RST_L CAM1_RST_L TCHSCR_INT_1V8_L CAM1_DET_L RST_ALC1011_L   BL_PWM_1V8 UART_AP_TX_DBG_RX UART_DBG_TX_AP_RX EN_SPKR AP_EC_WARM_RST_REQ UART_SCP_TX_DBGCON_RX UART_DBGCON_TX_SCP_RX   KPCOL0  MT6315_GPU_INT MT6315_PROC_BC_INT SD_CMD SD_CLK SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_RSTB EMMC_CMD EMMC_CLK EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 EMMC_DSL   MT6360_INT_ODL SCP_JTAG0_TRSTN AP_SPI_EC_CS_L AP_SPI_EC_CLK AP_SPI_EC_MOSI AP_SPI_EC_MISO SCP_JTAG0_TMS SCP_JTAG0_TCK SCP_JTAG0_TDO SCP_JTAG0_TDI AP_SPI_FLASH_CS_L AP_SPI_FLASH_CLK AP_SPI_FLASH_MOSI AP_SPI_FLASH_MISO                 audio-default-pins                pins-cmd-dat          D  Â  E  F  G  H  I  J  K           <  1  2  3  4  5      pins-hp-jack-int-odl            Â  Y          É        Ö   e         cr50-irq-default-pins              o   pins-gsc-ap-int-odl         Â  X          É         cros-ec-irq-default-pins               ?   pins-ec-ap-int-odl          Â           Ö   e         É         edptx-default-pins             Ò   pins-cmd-dat            Â           Ö         disp-pwm0-default-pins             C   pins-disp-pwm           Â  R   a         dptx-default-pins              Ø   pins-cmd-dat            Â           Ö         i2c0-default-pins              g   pins-bus            Â    	         ã        ð  è         i2c1-default-pins              h   pins-bus            Â  
          Ö  è        ð  è         i2c2-default-pins              k   pins-bus            Â             ã        ð  è         i2c3-default-pins              n   pins-bus            Â            Ö  è        ð  è         i2c4-default-pins              p   pins-bus            Â            Ö  è                    i2c5-default-pins              c   pins-bus            Â             ã        ð  è         i2c7-default-pins              d   pins-bus            Â             ã         mmc0-default-pins              L   pins-cmd-dat          $  Â  ~  }  |  {  w  v  u  t  y         É                   Ö   e      pins-clk            Â  z                      f      pins-rst            Â  x                   Ö   e         mmc0-uhs-pins              M   pins-cmd-dat          $  Â  ~  }  |  {  w  v  u  t  y         É                   Ö   e      pins-clk            Â  z                      f      pins-ds         Â                        f      pins-rst            Â  x                   Ö   e         mmc1-detect-pins               Q   pins-insert         Â  6          Ö         mmc1-default-pins              P   pins-cmd-dat            Â  n  p  q  r  s         É                   Ö   e      pins-clk            Â  o                      f         nor-default-pins               a   pins-ck-io          Â  Ž  �  �                          pins-cs         Â  Œ                    Ö         pcie0-default-pins             ]   pins-bus            Â               Ö         pcie1-default-pins             `   pins-bus            Â               Ö         panel-pwr-default-pins             è   pins-vreg-en            Â  7          pio-default-pins                  pins-low-power-pd         ,  Â        .   /   0   A   B   C   D   €   �          É               pins-low-power-pupd       <  Â  M   N   O   P   S   U   Z   [   ]   ^   _   `   h   i   k          É           e      pins-low-power-hdmi-disable         Â         !          É               pins-low-power-hdmi-rsel-disable            Â  "   #          É         $ø         pp3300-wlan-en-pins            é   pins-en         Â  :          rt1019p-default-pins               ë   pins-amp-sdb            Â  d          &         scp-default-pins               5   pins-vreq           Â  L         ã         É         spi0-default-pins              >   pins-cs-mosi-clk            Â  „  †  …         ã      pins-miso           Â  ‡                  subpmic-default-pins               e   pins-subpmic-int-n          Â  ‚          É         Ö         trackpad-default-pins              i   pins-int-n          Â            É         Ö         touchscreen-default-pins               q   pins-int-n          Â  \          É        Ö   e      pins-rst            Â  8          1      pins-report-sw          Â  9          &            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            B     `           power-controller          !    mediatek,mt8195-power-controller                         +            =              7   power-domain@8          B                        +            =           Q       power-domain@9          B   	        n   !      "           _mfg alt         k   #                     +            =           Q   $   power-domain@10         B   
        =          power-domain@11         B           =          power-domain@12         B           =          power-domain@13         B           =          power-domain@14         B           =                power-domain@15         B         Ø  n   "      "      "      "   	   "   @   "   A   "   K   "   à   %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %           _vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           k   #                     +            =      power-domain@16         B         8  n   "   â   &   $   &   %   &   &   &   '   &   (   &   )      D  _vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         k   #                     +            =      power-domain@17         B           n   "   á   '      '           _vppsys1 vppsys1-0 vppsys1-1         k   #        =          power-domain@22         B            n   (      (      (      (         $  _wepsys-0 wepsys-1 wepsys-2 wepsys-3         k   #        =          power-domain@23         B           n   )            _vdec0-0         k   #                     +            =       power-domain@24         B           n   *            _vdec1-0         k   #        =          power-domain@25         B           n   +            _vdec2-0         k   #        =             power-domain@26         B           n   ,            _venc0-larb          k   #                     +            =       power-domain@27         B           n   -            _venc1-larb          k   #        =             power-domain@18         B            n   "   ã   .       .      .         &  _vdosys1 vdosys1-0 vdosys1-1 vdosys1-2           k   #                     +            =      power-domain@19         B           k   #        =          power-domain@20         B           k   #        =          power-domain@21         B           n   "   Q        _hdmi_tx         =             power-domain@28         B           n   /       /   
        _img-0 img-1         k   #                     +            =      power-domain@29         B           =          power-domain@30         B           n   "      /      0           _ipe ipe-0 ipe-1         k   #        =             power-domain@31         B         (  n   1       1      1      1      1           _cam-0 cam-1 cam-2 cam-3 cam-4           k   #                     +            =      power-domain@32         B            =          power-domain@33         B   !        =          power-domain@34         B   "        =                   power-domain@0          B            k   #        =          power-domain@1          B           k   #        =          power-domain@2          B           =          power-domain@3          B           =          power-domain@4          B           n   "   5   "   7        _csi_rx_top csi_rx_top1          =          power-domain@5          B           n   2           _ether           =          power-domain@6          B           n   "   X   "   n        _adsp adsp1                       +            k   #        =      power-domain@7          B            n   "   g   "   "   "   n   #   2        _audio audio1 audio2 audio3          k   #        =                   watchdog@10007000             mediatek,mt8195-wdt          }        B     p                O              <      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           B     À                a              !      timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         B    p                «      	               n   3      pwrap@10024000            mediatek,mt8195-pwrap syscon            B    @                \pwrap           «       ó               n   #      #          	  _spi wrap            •   "   $        ¥   "   Ë   pmic              mediatek,mt6359                  é           ¼           Í      Þ      adc           mediatek,mt6359-auxadc          á         audio-codec           mediatek,mt6359-codec           ó                    regulators            mediatek,mt6359-regulator      buck_vs1            vs1         ) 5         A !‘À        Y             u      buck_vgpu11         vgpu11          ) €        A 7        ‰  ˆ        Y   È        ž                   u      buck_vmodem         vmodem          ) €        A Èà        ‰  *        Y   È      buck_vpu            vpu         ) €        A 7        ‰  ˆ        Y   È        ž                   u      buck_vcore          vcore           ) €        A Ö         ‰  ˆ        Y   È        ž                   u                 buck_vs2            vs2         ) 5         A j         Y             u      buck_vpa            vpa         ) ¡         A 7±Ð        Y  ,      buck_vproc2         vproc2          ) €        A 7        ‰  L        Y   È        ž                buck_vproc1         vproc1          ) €        A 7        ‰  L        Y   È        ž                buck_vcore_sshub            vcore_sshub         ) €        A 7      buck_vgpu11_sshub           vgpu11_sshub            ) dp        A dp         u      ldo_vaud18          vaud18          ) w@        A w@        Y   ð      ldo_vsim1           vsim1           ) ð         A /M`      ldo_vibr            vibr            ) O€        A 2Z       ldo_vrf12           vrf12           ) Èà        A Ö          u      ldo_vusb            vusb            ) -ÆÀ        A -ÆÀ        Y  À         u           J      ldo_vsram_proc2         vsram_proc2         ) ¡         A ½¶        ‰  L        Y   ð         u      ldo_vio18           vio18           ) ð         A ýà        Y  À         u           l      ldo_vcamio          vcamio          ) ð         A ýà      ldo_vcn18           vcn18           ) w@        A w@        Y   ð      ldo_vfe28           vfe28           ) *¹€        A *¹€        Y   x      ldo_vcn13           vcn13           ) »         A Ö       ldo_vcn33_1_bt          vcn33_1_bt          ) *¹€        A 5gà      ldo_vcn33_1_wifi            vcn33_1_wifi            ) *¹€        A 5gà      ldo_vaux18          vaux18          ) w@        A w@        Y   ð         u      ldo_vsram_others            vsram_others            ) q°        A q°        ‰  ˆ        Y   ð           $      ldo_vefuse          vefuse          ) ð         A „€      ldo_vxo22           vxo22           ) w@        A !‘À         u      ldo_vrfck           vrfck           ) ã`        A ð       ldo_vrfck_1         vrfck_1         ) ëÀ        A j       ldo_vbif28          vbif28          ) *¹€        A *¹€        Y   ð      ldo_vio28           vio28           ) *¹€        A 2Z          u      ldo_vemc            vemc            ) ,@         A 2Z       ldo_vemc_1          vemc_1          ) &%         A 2Z            N      ldo_vcn33_2_bt          vcn33_2_bt          ) *¹€        A 5gà      ldo_vcn33_2_wifi            vcn33_2_wifi            ) *¹€        A 5gà      ldo_va12            va12            ) O€        A Ö          u      ldo_va09            va09            ) 5         A O€      ldo_vrf18           vrf18           ) ð         A žP      ldo_vsram_md          	  vsram_md            ) ¡         A ½¶        ‰  *        Y   ð      ldo_vufs            vufs            ) ð         A ýà         u           O      ldo_vm18            vm18            ) ð         A ýà         u      ldo_vbbck           vbbck           ) Èà        A O€      ldo_vsram_proc1         vsram_proc1         ) ¡         A ½¶        ‰  L        Y   ð         u      ldo_vsim2           vsim2           ) ð         A /M`      ldo_vsram_others_sshub          vsram_others_sshub          ) ¡         A ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             B    p            �                \pmif spmimst            n   #      #       "   E      (  _pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         •   "   $        ¥   "   Ë                     +       mt6315@6              mediatek,mt6315-regulator           B          regulators     vbuck1          Vbcpu           ) €        A 7        Y           ‰  j        ž                   u           
            mt6315@7              mediatek,mt6315-regulator           B          regulators     vbuck1          Vgpu            ) €        A 7        Y           ‰  j        ž                                     infra-iommu@10315000              mediatek,mt8195-iommu-infra         B    1P       P       P  «                                                                         ¶              Z      mailbox@10320000              mediatek,mt8195-gce         B    2        @         «       â               Ã           n   #              £      mailbox@10330000              mediatek,mt8195-gce         B    3        @         «       ä               Ã           n   #              �      scp@10500000              mediatek,mt8195-scp       0  B    P             r             p        €         \sram cfg l1tcm          «      Î               »okay            Ïmediatek/mt8195/scp.img         Ý   4        default            5           ‚   cros-ec-rpmsg             google,cros-ec-rpmsg            ëcros-ec-rpmsg            clock-controller@10720000             mediatek,mt8195-scp_adsp            B    r                 a              6      dsp@10803000              mediatek,mt8195-dsp          B    €0            „               	  \cfg sram          ,  n   "   X      "   n   "   Š   6       "   #      K  _adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          ÿ   7           rx tx              8   9        »okay            Ý   :   ;                 mailbox@10816000              mediatek,mt8195-adsp-mbox           Ã            B    �`                «      ¾                  8      mailbox@10817000              mediatek,mt8195-adsp-mbox           Ã            B    �p                «      ¿                  9      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           B    ‰                    "        ÿ   7           «      6               1   <         	  8audiosys          ”  n      !      !      "   Ú   "   Û   "   Ü   "   Ý   "   ß   "   g   "   "   "   #   "   n   "   e   "   a   "   b   "   c   "   d   #   2   6          ó  _clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          »okay            D           d            Ý   =                 serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                     «       �               n      #         	  _baud bus            »okay          serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                     «       Ž               n      #         	  _baud bus          	  »disabled          serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                     «       �               n      #         	  _baud bus          	  »disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                     «      Ó               n      #         	  _baud bus          	  »disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                     «      Ô               n      #         	  _baud bus          	  »disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           B                     «      Õ               n      #         	  _baud bus          	  »disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           B                      n   #           _main            á           »okay               ê      syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           B     0                a              2      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B                      «       ¿               n   "   ™   "      #           _parent-clk sel-clk spi-clk          »okay            default            >        …       ec@0                         +              google,cros-ec-spi          B            Í                 default            ?        ™ -ÆÀ         «   i2c-tunnel            google,cros-ec-i2c-tunnel           ¹                         +       sbs-battery@b             sbs,sbs-battery         B           Ë           ß            regulator@0           google,cros-ec-regulator            B            mt_pmic_vmc_ldo         ) O€        A 6î€           S      regulator@1           google,cros-ec-regulator            B           mt_pmic_vmch_ldo            ) )2à        A 6î€           R      typec             google,cros-ec-typec                         +       connector@0           usb-c-connector         B            ôdual            ÿhost            	source        connector@1           usb-c-connector         B           ôdual            ÿhost            	source           keyboard-controller           google,cros-ec-keyb                    (            ;     P  U  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	 Ž + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i  ž ­t x c à á	 ä	 ¤  ø  q r s      4  b               	  	                        thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         B     °                «       ©               n   #           1   #            w   @   A      $  ƒlvts-calib-data-1 lvts-calib-data-2         ”              ã      svs@1100bc00              mediatek,mt8195-svs         B     ¼                «       Ç               n   #           _main            w   B   @      (  ƒsvs-calibration-data t-calibration-data         1   #           8svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           B     à                «       Ë               ÿ   7           ª           n   "   *   #   0        _main mm         »okay            default            C           æ      pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           B     ð                «                     ª           n   "   +   #   N        _main mm       	  »disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B                     «       À               n   "   ™   "      #   3        _parent-clk sel-clk spi-clk        	  »disabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B                     «       Á               n   "   ™   "      #   4        _parent-clk sel-clk spi-clk        	  »disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B    0                «       Â               n   "   ™   "      #   5        _parent-clk sel-clk spi-clk        	  »disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B    €                «       Ã               n   "   ™   "      #   <        _parent-clk sel-clk spi-clk        	  »disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            B    �                «       Ä               n   "   ™   "      #   =        _parent-clk sel-clk spi-clk        	  »disabled          spi@1101d000              mediatek,mt8195-spi-slave           B    Ð                «       Å               n   #   R        _spi         •   "           ¥   "   ˜      	  »disabled          spi@1101e000              mediatek,mt8195-spi-slave           B    à                «       Æ               n   #   S        _spi         •   "           ¥   "   ˜      	  »disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           B           @         «      Ì               µmacirq        .  _axi apb mac_main ptp_ref rmii_internal mac_cg         0  n   2       2      "   R   "   S   "   T   2           •   "   R   "   S   "   T        ¥   "   Â   "   Ã   "   Ä        ÿ   7           Å   #        Ö   D        æ   E        ù   F        	           	           	"          	  »disabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           	/           	?           	O                                    D      rx-queues-config            	Y            	o           E   queue0           	€        	“          queue1           	€        	“          queue2           	€        	“          queue3           	€        	“             tx-queues-config            	«            	Á           F   queue0          	Ó            	€        	ß          queue1          	Ó            	€        	ß         queue2          	Ó            	€        	ß         queue3          	Ó            	€        	ß               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           B            -ÿ     >              	  \mac ippc            ×                     ?                      +           «       €               n   #   /   "   í   #   B        _sys_ck ref_ck mcu_ck            	í   G      H            «        	ò   I      g        »okay            
	host            
   J   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          B                       \mac         «       �               •   "   ,   "   -        ¥   "   –   "   –      $  n   #   /   "   í   !         #   B      $  _sys_ck ref_ck mcu_ck dma_ck xhci_ck         »okay            
           
-   K         mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          B    #             õ                 «       ƒ               n   "      #      #           _source hclk source_cg           »okay            
9            
C         
U        
f L        �ëÂ          
u         
„         
“         
›         
¡        default state_uhs              L        
¯   M        
¹   N        
Å   O      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          B    $             Ç                 «       ‡               n   "      #      #   $        _source hclk source_cg           •   "           ¥   "   ¿        »okay            
9            
Ò        
ã      6           �ëÂ          
ì         
“        default state_uhs              P   Q        
¯   P         
ó                  
¹   R        
Å   S      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          B    %             æ                 «       ˆ               n   "       #      #   I        _source hclk source_cg           •   "            ¥   "   ¿      	  »disabled          ufshci@11270000           mediatek,mt8195-ufshci          B    '        #         «       ‰               	í   T      @  n   #   ?   #   @   #   A   #   6   #   7   #   8   #   Z   #   ]      X  _ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @                                                                                 	  »disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            B    '€                «       ª               n   #           1   #           w   @   A      $  ƒlvts-calib-data-1 lvts-calib-data-2         ”              Ú      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           B    )             )>              	  \mac ippc            «                     	í   U      V           •   "   .   "   /        ¥   "   –   "   –      $  n   2      "   ï   !         2         $  _sys_ck ref_ck mcu_ck dma_ck xhci_ck         	ò   I      h         «      	  »disabled          usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           B    *       -ÿ    *>              	  \mac ippc            ×            *        ?                      +           «                     •   "   0        ¥   "   –        n   2      "   ñ   2           _sys_ck ref_ck mcu_ck            	í   W            «        	ò   I      i        »okay            
	host            
   J   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          B                       \mac         «                     •   "   1        ¥   "   –        n   2           _sys_ck          »okay            
-   K         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           B    +       -ÿ    +>              	  \mac ippc            ×            +        ?                      +           «                     •   "   2        ¥   "   –        n   2      "   ó   2   	        _sys_ck ref_ck mcu_ck            	í   X            «        	ò   I      j        »okay            
	host            
   J   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          B                       \mac         «                     •   "   3        ¥   "   –        n   2   	        _sys_ck          »okay             5        
-   Y         pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           6pci                      +           B    /        @       	  \pcie-mac            «                     F       ÿ      8  ×�                           ‚                       à          P       Z              Z          0  n   #   V   #   #   #   &   #   +   #   K   2         /  _pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          •   "   G        ¥   "           	í   [      	  ipcie-phy            ÿ   7            é           s                     `  †                  \                      \                     \                     \           »okay            default            ]   interrupt-controller                                  é              \      pcie@0            pciclass,0604           B                            6pci         ”                        +            ×   port       endpoint            ž   ^           ì               pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           6pci                      +           B    /€       @       	  \pcie-mac            «                     F       ÿ      8  ×�       $       $           ‚       $       $       à          P       Z              Z          (  n   #   W      #   X      #   Q   2         /  _pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          •   "   H        ¥   "           	í   V         	  ipcie-phy            ÿ   7           é           s                     `  †                  _                      _                     _                     _           »okay            default            `   interrupt-controller                                  é              _      pcie@0            pciclass,0604           B                            6pci         ”           ®   Y                     +            ×   wifi@0          B                             «            spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         B    2À                «      9               n   "   o   2      2           _spi sf axi                       +            »okay            default            a   flash@0           jedec,spi-nor           B            ™u         ¾           Ï            efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            B    Á                              +      usb3-tx-imp@184,1           B  „           à                  w      usb3-rx-imp@184,2           B  „           à                 v      usb3-intr@185           B  …           à                 u      usb3-tx-imp@186,1           B  †           à                  t      usb3-rx-imp@186,2           B  †           à                 s      usb3-intr@187           B  ‡           à                 r      usb2-intr-p0@188,1          B  ˆ           à             usb2-intr-p1@188,2          B  ˆ           à            usb2-intr-p2@189,1          B  ‰           à            usb2-intr-p3@189,2          B  ‰           à            pciephy-rx-ln1@190,1            B  �           à                  ~      pciephy-tx-ln1-nmos@190,2           B  �           à                 }      pciephy-tx-ln1-pmos@191,1           B  ‘           à                  |      pciephy-rx-ln0@191,2            B  ‘           à                 {      pciephy-tx-ln0-nmos@192,1           B  ’           à                  z      pciephy-tx-ln0-pmos@192,2           B  ’           à                 y      pciephy-glb-intr@193            B  “           à                  x      dp-data@1ac         B  ¬              Ñ      lvts1-calib@1bc         B  ¼              @      lvts2-calib@1d0         B  Ð   8           A      svs-calib@580           B  €   d           B      socinfo-data1@7a0           B               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ×        Ä             »okay       usb-phy@0           B               n   "   ò        _ref         å              W         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ×        Å             »okay       usb-phy@0           B               n   "   ô        _ref         å              X         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         B    È                 n           Šmipi_tx0_pll            a            å          	  »disabled               ³      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         B    É                 n           Šmipi_tx1_pll            a            å          	  »disabled               ¶      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B    Ð             "€       €        «       š               u           n   b       #   ;      	  _main dma                         +            »okay            h €        default            c      i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B    Ð            "        €        «       ›               u           n   b      #   ;      	  _main dma                         +          	  »disabled          i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B    Ð             "€       €        «       œ               u           n   b      #   ;      	  _main dma                         +            »okay            h €        default            d   pmic@34         é             mediatek,mt6360         B   4                 Í      ‚           µIRQB            default            e         «         clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          B    Ð0                a              b      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy            B    Õð                 n   "   P   #      !      !           _pll_ref 26m pll1 pll2           Šhdmi_txpll          a            å            ð   
        ÿ         	  »disabled               Ð      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B    à             " €       €        «       �               u           n   f       #   ;      	  _main dma                         +            »okay            h €        default            g      i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B    à            "        €        «       “               u           n   f      #   ;      	  _main dma                         +            »okay            h €          0Ô        default            h   trackpad@15           elan,ekth3000           B           Í                 default            i        +   j         «         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B    à             "€       €        «       –               u           n   f      #   ;      	  _main dma                         +            »okay            h €        default            k   codec@1a            B           Í      Y           ¼           6           E   l        Q   l        ^   m        l   l          realtek,rt5682s         {   ú                 amplifier@38              maxim,max98390          B   8        ‘      d           �Right           ¼                     amplifier@39              maxim,max98390          B   9        �Left            ¼                        i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B    à0            "€       €        «       ˜               u           n   f      #   ;      	  _main dma                         +            »okay            h €        default            n   tpm@50            google,cr50         B   P        Í      X           default            o         i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          B    à@            "        €        «       ™               u           n   f      #   ;      	  _main dma                         +            »okay            h €        default            p   touchscreen@10            hid-over-i2c            B           ¯           Í      \           default            q        ¾   
        Õ   j      	  »disabled          touchscreen@15            hid-over-i2c            B           ¯           Í      \           default            q        ¾   
        Õ   j         clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          B    àP                a              f      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ×        ã             ÿ   7           »okay       usb-phy@0           B               n   "   ð           _ref da_ref          å              U      usb-phy@700         B              n   !      "   ð        _ref da_ref          w   r   s   t        ƒintr rx_imp tx_imp          å              V         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ×        ä             »okay       usb-phy@0           B               n   "   î           _ref da_ref          å              G      usb-phy@700         B              n   !      "   î        _ref da_ref          w   u   v   w        ƒintr rx_imp tx_imp          å              H         phy@11e80000              mediatek,mt8195-pcie-phy            B    è                 \sif         w   x   y   z   {   |   }   ~      G  ƒglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          ÿ   7           å            »okay               [      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           B    ú        À         n            
  _unipro mp           å          	  »disabled               T      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           B             @         n             0  «      �             Œ             ‹               µjob mmu gpu         à   €      (  ÿ   7   
   7      7      7      7           ôcore0 core1 core2 core3 core4           »okay                      clock-controller@13fbf000             mediatek,mt8195-mfgcfg          B    ûð                a                    syscon@14000000           mediatek,mt8195-vppsys0 syscon          B                      a              �                      %      dma-controller@14001000           mediatek,mt8195-mdp3-rdma           B                        �                  +              ?   ‚        ÿ   7           L   ƒ   €        n   %         <     �         �         �         �         �              S         display@14002000              mediatek,mt8195-mdp3-fg         B                         �                   n   %          display@14003000              mediatek,mt8195-mdp3-stitch         B     0                   �      0            n   %         display@14004000              mediatek,mt8195-mdp3-hdr            B     @                   �      @            n   %   "      display@14005000              mediatek,mt8195-mdp3-aal            B     P                «      F                  �      P            n   %   
        ÿ   7         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           B     `                   �      `            +    %        n   %         display@14007000              mediatek,mt8195-mdp3-tdshp          B     p                   �      p            n   %   #      display@14008000              mediatek,mt8195-mdp3-color          B     €                «      I                  �      €            n   %   $        ÿ   7         display@14009000              mediatek,mt8195-mdp3-ovl            B     �                «      J                  �      �            n   %   %        ÿ   7           L   ƒ   ‚      display@1400a000              mediatek,mt8195-mdp3-padding            B                         �                   n   %           ÿ   7         display@1400b000              mediatek,mt8195-mdp3-tcc            B     °                   �      °            n   %         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         B     À                   �      À            +    +        n   %           L   ƒ   ƒ        ÿ   7           S         mutex@1400f000            mediatek,mt8195-vpp-mutex           B     ð                «      P                  �      ð            n   %           ÿ   7         smi@14010000              mediatek,mt8195-smi-sub-common          B                     n   %      %      %           _apb smi gals0           ^   „        ÿ   7              …      smi@14011000              mediatek,mt8195-smi-sub-common          B                    n   %      %      %           _apb smi gals0           ^   „        ÿ   7              ¢      smi@14012000              mediatek,mt8195-smi-common-vpp          B                      n   %      %      %      %           _apb smi gals0 gals1         ÿ   7              „      larb@14013000             mediatek,mt8195-smi-larb            B    0                k           ^   …        n   %      %           _apb smi         ÿ   7              ˆ      iommu@14018000            mediatek,mt8195-iommu-vpp           B    €              8  |   †   ‡   ˆ   ‰   Š   ‹   Œ   �   Ž   �   �   ‘   ’   “        «      R               n   %           _bclk            ¶           ÿ   7              ƒ      clock-controller@14e00000             mediatek,mt8195-wpesys          B    à                 a              (      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         B    à                 a         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         B    à0                a         larb@14e04000             mediatek,mt8195-smi-larb            B    à@                k           ^   ”        n   (      (           _apb smi         ÿ   7              ¿      larb@14e05000             mediatek,mt8195-smi-larb            B    àP                k           ^   „        n   (      (      %           _apb smi gals            ÿ   7              Š      syscon@14f00000           mediatek,mt8195-vppsys1 syscon          B    ð                 a              �   	                  '      mutex@14f01000            mediatek,mt8195-vpp-mutex           B    ð                «      {                  �   	              n   '   '        ÿ   7         larb@14f02000             mediatek,mt8195-smi-larb            B    ð                 k           ^   ”        n   '      '      %           _apb smi gals            ÿ   7              ¾      larb@14f03000             mediatek,mt8195-smi-larb            B    ð0                k           ^   …        n   '      '      %           _apb smi gals            ÿ   7              ‰      display@14f06000              mediatek,mt8195-mdp3-split          B    ð`                   �   	  `            n   '      '   +   '   ,        ÿ   7         display@14f07000              mediatek,mt8195-mdp3-tcc            B    ðp                   �   	  p            n   '         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           B    ð€                   �   	  €            +  „  ¨        n   '           L   •            ÿ   7           S         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           B    ð�                   �   	  �            +  …  ©        n   '   
        L   •   ¤        ÿ   7           S         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           B    ð                    �   	               +  †  ª        n   '           L   ƒ   À        ÿ   7           S         display@14f0b000              mediatek,mt8195-mdp3-fg         B    ð°                   �   	  °            n   '   	      display@14f0c000              mediatek,mt8195-mdp3-fg         B    ðÀ                   �   	  À            n   '         display@14f0d000              mediatek,mt8195-mdp3-fg         B    ðÐ                   �   	  Ð            n   '         display@14f0e000              mediatek,mt8195-mdp3-hdr            B    ðà                   �   	  à            n   '         display@14f0f000              mediatek,mt8195-mdp3-hdr            B    ðð                   �   	  ð            n   '         display@14f10000              mediatek,mt8195-mdp3-hdr            B    ñ                    �   
               n   '          display@14f11000              mediatek,mt8195-mdp3-aal            B    ñ                «      i                  �   
              n   '           ÿ   7         display@14f12000              mediatek,mt8195-mdp3-aal            B    ñ                 «      j                  �   
               n   '           ÿ   7         display@14f13000              mediatek,mt8195-mdp3-aal            B    ñ0                «      k                  �   
  0            n   '   !        ÿ   7         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           B    ñ@                   �   
  @            +  �  ¯        n   '         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           B    ñP                   �   
  P            +  ‘  °        n   '   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           B    ñ`                   �   
  `            +  ’  ±        n   '   %      display@14f17000              mediatek,mt8195-mdp3-tdshp          B    ñp                   �   
  p            n   '         display@14f18000              mediatek,mt8195-mdp3-tdshp          B    ñ€                   �   
  €            n   '   (      display@14f19000              mediatek,mt8195-mdp3-tdshp          B    ñ�                   �   
  �            n   '   )      display@14f1a000              mediatek,mt8195-mdp3-merge          B    ñ                    �   
               n   '           ÿ   7         display@14f1b000              mediatek,mt8195-mdp3-merge          B    ñ°                   �   
  °            n   '           ÿ   7         display@14f1c000              mediatek,mt8195-mdp3-color          B    ñÀ                «      t                  �   
  À            n   '           ÿ   7         display@14f1d000              mediatek,mt8195-mdp3-color          B    ñÐ                   �   
  Ð            «      u               n   '           ÿ   7         display@14f1e000              mediatek,mt8195-mdp3-color          B    ñà                «      v                  �   
  à            n   '           ÿ   7         display@14f1f000              mediatek,mt8195-mdp3-ovl            B    ñð                «      w                  �   
  ð            n   '            ÿ   7           L   •   ¢      display@14f20000              mediatek,mt8195-mdp3-padding            B    ò                    �                  n   '           ÿ   7         display@14f21000              mediatek,mt8195-mdp3-padding            B    ò                   �                 n   '           ÿ   7         display@14f22000              mediatek,mt8195-mdp3-padding            B    ò                    �                  n   '           ÿ   7         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         B    ò0                   �     0            +  Ÿ  «        n   '           L   •   £        ÿ   7           S         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         B    ò@                   �     @            +     ¬        n   '           L   •   ¦        ÿ   7           S         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         B    òP                   �     P            +  ¡  ­        n   '           L   ƒ   Â        ÿ   7           S         clock-controller@15000000             mediatek,mt8195-imgsys          B                      a              /      larb@15001000             mediatek,mt8195-smi-larb            B                     k   	        ^   –        n   /       /       /   
        _apb smi gals            ÿ   7              À      smi@15002000              mediatek,mt8195-smi-sub-common          B                      n   /      /      %           _apb smi gals0           ^   „        ÿ   7              ™      smi@15003000              mediatek,mt8195-smi-sub-common          B     0                n   /       /       /   
        _apb smi gals0           ^   ”        ÿ   7              –      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         B                     a              —      larb@15120000             mediatek,mt8195-smi-larb            B                     k   
        ^   –        n   /      —            _apb smi         ÿ   7              Á      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          B                     a         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         B    "                 a              ˜      larb@15230000             mediatek,mt8195-smi-larb            B    #                 k           ^   –        n   /      ˜            _apb smi         ÿ   7              Â      clock-controller@15330000             mediatek,mt8195-ipesys          B    3                 a              0      larb@15340000             mediatek,mt8195-smi-larb            B    4                 k           ^   ™        n   0      0           _apb smi         ÿ   7              ‹      clock-controller@16000000             mediatek,mt8195-camsys          B                      a              1      larb@16001000             mediatek,mt8195-smi-larb            B                     k           ^   š        n   1       1       1           _apb smi gals            ÿ   7              Ã      larb@16002000             mediatek,mt8195-smi-larb            B                      k           ^   ›        n   1      1           _apb smi         ÿ   7              Œ      smi@16004000              mediatek,mt8195-smi-sub-common          B     @                n   1       1       1           _apb smi gals0           ^   ”        ÿ   7              š      smi@16005000              mediatek,mt8195-smi-sub-common          B     P                n   1      1      %           _apb smi gals0           ^   „        ÿ   7              ›      larb@16012000             mediatek,mt8195-smi-larb            B                     k           ^   ›        n   œ       œ            _apb smi         ÿ   7               �      larb@16013000             mediatek,mt8195-smi-larb            B    0                k           ^   š        n   �       �            _apb smi         ÿ   7               Ä      larb@16014000             mediatek,mt8195-smi-larb            B    @                k           ^   ›        n   ž       ž            _apb smi         ÿ   7   !           “      larb@16015000             mediatek,mt8195-smi-larb            B    P                k           ^   š        n   Ÿ       Ÿ            _apb smi         ÿ   7   !           É      clock-controller@1604f000             mediatek,mt8195-camsys_rawa         B    ð                a              œ      clock-controller@1606f000             mediatek,mt8195-camsys_yuva         B    ð                a              �      clock-controller@1608f000             mediatek,mt8195-camsys_rawb         B    ð                a              ž      clock-controller@160af000             mediatek,mt8195-camsys_yuvb         B    
ð                a              Ÿ      clock-controller@16140000             mediatek,mt8195-camsys_mraw         B                     a                     larb@16141000             mediatek,mt8195-smi-larb            B                    k           ^   š        n   1               1           _apb smi gals            ÿ   7   "           È      larb@16142000             mediatek,mt8195-smi-larb            B                     k           ^   ›        n                        _apb smi         ÿ   7   "           ’      clock-controller@17200000             mediatek,mt8195-ccusys          B                      a              ¡      larb@17201000             mediatek,mt8195-smi-larb            B                     k           ^   ›        n   ¡       ¡            _apb smi         ÿ   7              Ž      video-codec@18000000              mediatek,mt8195-vcodec-dec          ?   ‚        L   •                        +            B                   @                ×                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         B                       L   ƒ  à   ƒ  á         n   "   A   )      )      "   �        _sel vdec lat top            •   "   A        ¥   "   �        ÿ   7         video-codec@10000             mediatek,mtk-vcodec-lat         B                      «      Ä             0  L   •      •     •     •     •     •           n   "   A   )      )      "   �        _sel vdec lat top            •   "   A        ¥   "   �        ÿ   7         video-codec@25000             mediatek,mtk-vcodec-core            B     P                «      Ã             P  L   •      •  ¡   •  ¢   •  £   •  ¤   •  ¥   •  ¦   •  §   •  ¨   •  ©         n   "   A   *      *      "   �        _sel vdec lat top            •   "   A        ¥   "   �        ÿ   7            larb@1800d000             mediatek,mt8195-smi-larb            B     Ð                k           ^   ”        n   )       )            _apb smi         ÿ   7              Ç      larb@1800e000             mediatek,mt8195-smi-larb            B     à                k           ^   ¢        n   %      )            _apb smi         ÿ   7              ‘      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         B     ð                a              )      larb@1802e000             mediatek,mt8195-smi-larb            B    à                k           ^   ”        n   *       *            _apb smi         ÿ   7              Æ      clock-controller@1802f000             mediatek,mt8195-vdecsys         B    ð                a              *      larb@1803e000             mediatek,mt8195-smi-larb            B    à                k           ^   ¢        n   %      +            _apb smi         ÿ   7              �      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           B    ð                a              +      clock-controller@190f3000             mediatek,mt8195-apusys_pll          B    0                a         clock-controller@1a000000             mediatek,mt8195-vencsys         B                      a              ,      larb@1a010000             mediatek,mt8195-smi-larb            B                     k           ^   ”        n   ,      ,           _apb smi         ÿ   7              Å      video-codec@1a020000              mediatek,mt8195-vcodec-enc          B                   H  L   •  `   •  a   •  b   •  c   •  d   •  v   •  w   •  x   •  y        «      U               ?   ‚        n   ,         	  _venc_sel            •   "   @        ¥   "   �        ÿ   7                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec          ÿ   7         0  L   •  m   •  n   •  r   •  s   •  t   •  u                     +         0  ×                                            jpgdec@0,0            mediatek,mt8195-jpgdec-hw           B                     0  L   •  m   •  n   •  r   •  s   •  t   •  u        «      W               n   ,           _jpgdec          ÿ   7         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw           B                    0  L   •  m   •  n   •  r   •  s   •  t   •  u        «      X               n   ,           _jpgdec          ÿ   7         jpgdec@1,0            mediatek,mt8195-jpgdec-hw           B                    0  L   ƒ  �   ƒ  Ž   ƒ  ’   ƒ  “   ƒ  ”   ƒ  •        «      \               n   -           _jpgdec          ÿ   7            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           B                      a              -      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            B                        £               a              £                     &   port                         +       endpoint@0          B            ž   ¤           ¥            jpeg-encoder@1a030000             mediatek,mt8195-jpgenc          ÿ   7            L   ƒ  ‡   ƒ  ˆ   ƒ  ‰   ƒ  Œ                     +         0  ×                                            jpgenc@0,0            mediatek,mt8195-jpgenc-hw           B                        L   •  g   •  h   •  i   •  l        «      V               n   ,           _jpgenc          ÿ   7         jpgenc@1,0            mediatek,mt8195-jpgenc-hw           B                       L   ƒ  ‡   ƒ  ˆ   ƒ  ‰   ƒ  Œ        «      [               n   -           _jpgenc          ÿ   7            larb@1b010000             mediatek,mt8195-smi-larb            B                     k           ^   „        n   -      -      %            _apb smi gals            ÿ   7              �      ovl@1c000000              mediatek,mt8195-disp-ovl            B                      «      |               ÿ   7           n   &            L   •              £             ports                        +       port@0          B       endpoint            ž   ¥           ¤         port@1          B      endpoint            ž   ¦           §               rdma@1c002000             mediatek,mt8195-disp-rdma           B                      «      ~               ÿ   7           n   &           L   •               £             ports                        +       port@0          B       endpoint            ž   §           ¦         port@1          B      endpoint            ž   ¨           ©               color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           B     0                «                     ÿ   7           n   &              £     0       ports                        +       port@0          B       endpoint            ž   ©           ¨         port@1          B      endpoint            ž   ª           «               ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           B     @                «      €               ÿ   7           n   &              £     @       ports                        +       port@0          B       endpoint            ž   «           ª         port@1          B      endpoint            ž   ¬           ­               aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           B     P                «      �               ÿ   7           n   &              £     P       ports                        +       port@0          B       endpoint            ž   ­           ¬         port@1          B      endpoint            ž   ®           ¯               gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           B     `                «      ‚               ÿ   7           n   &              £     `       ports                        +       port@0          B       endpoint            ž   ¯           ®         port@1          B      endpoint            ž   °           ±               dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         B     p                «      ƒ               ÿ   7           n   &   	           £     p       ports                        +       port@0          B       endpoint            ž   ±           °         port@1          B      endpoint            ž   ²           ´               dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         B     €                «      „               ÿ   7           n   &      &   *   ³        _engine digital hs           	í   ³        idphy          	  »disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            B     �                «      …               ÿ   7           n   &              £     �       ports                        +       port@0          B       endpoint            ž   ´           ²         port@1          B      endpoint            ž   µ           ·               dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         B                     «      Ž               ÿ   7           n   &      &   +   ¶        _engine digital hs           	í   ¶        idphy          	  »disabled          merge@1c014000            mediatek,mt8195-disp-merge          B    @                «      �               ÿ   7           n   &              £     @       ports                        +       port@0          B       endpoint            ž   ·           µ         port@1          B      endpoint            ž   ¸           ¹               dp-intf@1c015000              mediatek,mt8195-dp-intf         B    P                «      ‘               ÿ   7           n   &   ,   &      !           _pixel engine pll            »okay       ports                        +       port@0          B       endpoint            ž   ¹           ¸         port@1          B      endpoint            ž   º           Ó               mutex@1c016000            mediatek,mt8195-disp-mutex          B    `                «      ’               ÿ   7           n   &              £     `            +  U      larb@1c018000             mediatek,mt8195-smi-larb            B    €                k            ^   ”        n   &   (   &   (   %           _apb smi gals            ÿ   7              ¼      larb@1c019000             mediatek,mt8195-smi-larb            B    �                k           ^   „        n   &   (   %       %           _apb smi gals            ÿ   7              †      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          B                        £                 £                  a           O              .   port                         +       endpoint@1          B           ž   »           Î            smi@1c01b000              mediatek,mt8195-smi-common-vdo          B    °                 n   &   %   &   &   &   )   &   $        _apb smi gals0 gals1         ÿ   7              ”      iommu@1c01f000            mediatek,mt8195-iommu-vdo           B    ð              8  |   ¼   ½   ¾   ¿   À   Á   Â   Ã   Ä   Å   Æ   Ç   È   É        «      �               ¶           n   &   '        _bclk            ÿ   7              •      mutex@1c101000            mediatek,mt8195-disp-mutex          B                    «      î               ÿ   7           n   .              £                 +  À      larb@1c102000             mediatek,mt8195-smi-larb            B                     k           ^   ”        n   .       .       .           _apb smi gals            ÿ   7              ½      larb@1c103000             mediatek,mt8195-smi-larb            B    0                k           ^   „        n   .      .      %            _apb smi gals            ÿ   7              ‡      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           B    @                «      ï               n   .           ÿ   7           L   •   @           £     @            S         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           B    P                «      ð               n   .           ÿ   7           L   ƒ   `           £     P            S         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           B    `                «      ñ               n   .           ÿ   7           L   •   A           £     `            S         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           B    p                «      ò               n   .           ÿ   7           L   ƒ   a           £     p            S         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           B    €                «      ó               n   .           ÿ   7           L   •   B           £     €            S         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           B    �                «      ô               n   .           ÿ   7           L   ƒ   b           £     �            S         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           B                     «      õ               n   .           ÿ   7           L   •   C           £                  S         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           B    °                «      ö               n   .           ÿ   7           L   ƒ   c           £     °            S         vpp-merge@1c10c000            mediatek,mt8195-disp-merge          B    À                «      ÷               n   .   	   .           _merge merge_async           ÿ   7              £     À             ‹        1   .         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          B    Ð                «      ø               n   .   
   .           _merge merge_async           ÿ   7              £     Ð             ‹        1   .         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          B    à                «      ù               n   .      .           _merge merge_async           ÿ   7              £     à             ‹        1   .         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          B    ð                «      ú               n   .      .           _merge merge_async           ÿ   7              £     ð             ‹        1   .         vpp-merge@1c110000            mediatek,mt8195-disp-merge          B                     «      û               n   .      .           _merge merge_async           ÿ   7              £                   Ÿ        1   .      ports                        +       port@0                       +            B       endpoint@1          B           ž   Ê           Ï         port@1                       +            B      endpoint@1          B           ž   Ë           Ì               dpi@1c112000              mediatek,mt8195-dpi         B                     n   .   -   .      .   2        _pixel engine pll            «                      ÿ   7           1   .         	  »disabled       ports                        +       port@0          B       endpoint             port@1          B      endpoint                   dp-intf@1c113000              mediatek,mt8195-dp-intf         B    0                «                     ÿ   7           n   .   /   .      !           _pixel engine pll            »okay       ports                        +       port@0                       +            B       endpoint@1          B           ž   Ì           Ë         port@1                       +            B      endpoint@1          B           ž   Í           Ù               hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  B    @            P            p            �                         °            À              4  \mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p     £     @       £     P       £     p       £     �       £             £     °       £     À          h  n   .   %   .       .   #   .   !   .   $   .   "   .   1   .   &   .   '   .   (   .   )   .   *   "         ƒ  _mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          ÿ   7           L   ƒ   d   ƒ   e        «                   (  1   .   3   .   4   .   5   .   6   .   7      E  8vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async       ports                        +       port@0                       +            B       endpoint@1          B           ž   Î           »         port@1                       +            B      endpoint@1          B           ž   Ï           Ê               hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx         ¼           B    0                  n   "   Q   "   L   "   M   '   ,        _bus hdcp hdcp24m hdmi-split         •   "   L        ¥   "   “        «      ¥               ÿ   7           	í   Ð        ihdmi          	  »disabled       i2c           mediatek,mt8195-hdmi-ddc            n         ports                        +       port@0          B       endpoint             port@1          B      endpoint                   edp-tx@1c500000           mediatek,mt8195-edp-tx          B    P        €         w   Ñ        ƒdp_calibration_data         ÿ   7           «      ¤               ¶  ¤        »okay            default            Ò   ports                        +       port@0          B       endpoint            ž   Ó           º         port@1          B      endpoint            Ç                     ž   Ô           ×            aux-bus    panel         
    edp-panel           Ò   Õ        ß   Ö   port       endpoint            ž   ×           Ô                  dp-tx@1c600000            mediatek,mt8195-dp-tx           B    `        €         w   Ñ        ƒdp_calibration_data         ÿ   7           «      Ê               ¶  ¤        »okay            ¼            default            Ø              ports                        +       port@0                       +            B       endpoint@1          B           ž   Ù           Í         port@1          B      endpoint            Ç                               thermal-zones      cpu0-thermal            é  è        ÷   ú           Ú      trips      trip-alert           L        )  Ð         Epassive            Û      trip-crit            †         )  Ð      	   Ecritical             cooling-maps       map0            4   Û      0  9   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            é  è        ÷   ú           Ú      trips      trip-alert           L        )  Ð         Epassive            Ü      trip-crit            †         )  Ð      	   Ecritical             cooling-maps       map0            4   Ü      0  9   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            é  è        ÷   ú           Ú      trips      trip-alert           L        )  Ð         Epassive            Ý      trip-crit            †         )  Ð      	   Ecritical             cooling-maps       map0            4   Ý      0  9   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            é  è        ÷   ú           Ú      trips      trip-alert           L        )  Ð         Epassive            Þ      trip-crit            †         )  Ð      	   Ecritical             cooling-maps       map0            4   Þ      0  9   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            é  è        ÷   ú           Ú       trips      trip-alert           L        )  Ð         Epassive            ß      trip-crit            †         )  Ð      	   Ecritical             cooling-maps       map0            4   ß      0  9   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            é  è        ÷   ú           Ú      trips      trip-alert           L        )  Ð         Epassive            à      trip-crit            †         )  Ð      	   Ecritical             cooling-maps       map0            4   à      0  9   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            é  è        ÷   ú           Ú      trips      trip-alert           L        )  Ð         Epassive            á      trip-crit            †         )  Ð      	   Ecritical             cooling-maps       map0            4   á      0  9   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            é  è        ÷   ú           Ú      trips      trip-alert           L        )  Ð         Epassive            â      trip-crit            †         )  Ð      	   Ecritical             cooling-maps       map0            4   â      0  9   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            é  è        ÷   ú           ã      trips      trip-alert           L        )  Ð         Epassive       trip-crit            †         )  Ð      	   Ecritical                vpu1-thermal            é  è        ÷   ú           ã   	   trips      trip-alert           L        )  Ð         Epassive       trip-crit            †         )  Ð      	   Ecritical                gpu-thermal         é  è        ÷   ú           ã   
   trips      trip-alert           L        )  Ð         Epassive       trip-crit            †         )  Ð      	   Ecritical                gpu1-thermal            é  è        ÷   ú           ã      trips      trip-alert           L        )  Ð         Epassive       trip-crit            †         )  Ð      	   Ecritical                vdec-thermal            é  è        ÷   ú           ã      trips      trip-alert           L        )  Ð         Epassive       trip-crit            †         )  Ð      	   Ecritical                img-thermal         é  è        ÷   ú           ã      trips      trip-alert           L        )  Ð         Epassive       trip-crit            †         )  Ð      	   Ecritical                infra-thermal           é  è        ÷   ú           ã      trips      trip-alert           L        )  Ð         Epassive       trip-crit            †         )  Ð      	   Ecritical                cam0-thermal            é  è        ÷   ú           ã      trips      trip-alert           L        )  Ð         Epassive       trip-crit            †         )  Ð      	   Ecritical                cam1-thermal            é  è        ÷   ú           ã      trips      trip-alert           L        )  Ð         Epassive       trip-crit            †         )  Ð      	   Ecritical                soc-area-thermal            é  è        ÷   ú           ä   trips      trip-crit            H         )  è      	   Ecritical                pmic-area-thermal           é  è        ÷               å   trips      trip-crit            H         )  è      	   Ecritical                   backlight-lcd0            pwm-backlight           H      ÿ        Z  @        s      R            €  ÿ        —   æ     ¡         Ò   ç           Ö      chosen          œserial0:115200n8          memory@40000000         6memory          B    @       €         regulator-pp3300-disp-x           regulator-fixed         pp3300_disp_x           ) 2Z         A 2Z         Y  	Ä         ¨        »      7            default            è        À   m           Õ      regulator-pp3300-ldo-z5           regulator-fixed         pp3300_ldo_z5            u         Ë        ) 2Z         A 2Z         À   ç      regulator-pp3300-s3           regulator-fixed       
  pp3300_s3            u         Ë        ) 2Z         A 2Z         À   m           j      regulator-pp3300-wlan             regulator-fixed         default            é        pp3300_wlan          ¨        »      :            À   m           Y      regulator-pp3300-z2           regulator-fixed       
  pp3300_z2            u         Ë        ) 2Z         A 2Z         À   ç           m      regulator-pp4200-z2           regulator-fixed       
  pp4200_z2            u         Ë        ) @@        A @@        À   ç      regulator-pp5000-s5           regulator-fixed       
  pp5000_s5            u         Ë        ) LK@        A LK@        À   ç      regulator-ppvar-sys           regulator-fixed       
  ppvar_sys            u         Ë           ç      thermal-sensor-t1             generic-adc-thermal         ”            Ý   ê            ésensor-channel        à  úÿÿØð  ÿÿìx  Í      ~  ˆ  %  '  Ã  :˜  [  N   ï  a¨  „  u0    ˆ¸  ¹  œ@  ]  ¯È    ÃP  Á  ÖØ  €  ê`  G  ýè   p   í $ø   Ê 8€   ¬ L   “ _�   } s   k †    \ š(   O ­°   D Á8   ; ÔÀ   3 èH   ,           ä      thermal-sensor-t2             generic-adc-thermal         ”            Ý   ê           ésensor-channel        à  úÿÿØð  ÿÿìx  Í      ~  ˆ  %  '  Ã  :˜  [  N   ï  a¨  „  u0    ˆ¸  ¹  œ@  ]  ¯È    ÃP  Á  ÖØ  €  ê`  G  ýè   p   í $ø   Ê 8€   ¬ L   “ _�   } s   k †    \ š(   O ­°   D Á8   ; ÔÀ   3 èH   ,           å      regulator-5v0-usb-vbus            regulator-fixed       	  usb-vbus            ) LK@        A LK@         ¨         u           K      reserved-memory                      +            ×   memory@50000000           shared-dma-pool         B    P       �                      4      memory@60000000           shared-dma-pool         B    `        Ø                      ;      memory@60d80000           shared-dma-pool         B    `Ø                             =      memory@60e80000           shared-dma-pool         B    `è       (                      :         rt1019p           realtek,rt1019p         rt1019p         ¼            default            ë               d          	  »disabled          nvme-connector            pcie-m2-m-connector         ®   m   ports                        +       port@0          B                         +       endpoint@0          B            ž   ì           ^                  	compatible interrupt-parent #address-cells #size-cells model chassis-type dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c7 mmc0 mmc1 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform mediatek,adsp mediatek,dai-link pinctrl-names pinctrl-0 audio-routing link-name mediatek,clk-provider sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit gpio-line-names pinmux input-enable bias-pull-up bias-disable drive-strength-microamp drive-strength bias-pull-down output-low output-high #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells firmware-name memory-region mediatek,rpmsg-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names mediatek,etdm-in2-cowork-source mediatek,etdm-out2-cowork-source mediatek,pad-select spi-max-frequency wakeup-source google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup dr_mode vusb33-supply rx-fifo-depth vbus-supply bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable pinctrl-1 vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 freq-table-hz mediatek,ufs-disable-mcq usb2-lpm-disable bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map num-lanes remote-endpoint vpcie3v3-supply spi-rx-bus-width spi-tx-bus-width bits #phy-cells mediatek,ibias mediatek,ibias_up i2c-scl-internal-delay-ns vcc-supply realtek,jd-src AVDD-supply DBVDD-supply MICVDD-supply LDO1-IN-supply realtek,amic-delay-ms reset-gpios sound-name-prefix hid-descr-addr post-power-on-delay-ms vdd-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz data-lanes power-supply backlight polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device brightness-levels default-brightness-level enable-gpios num-interpolated-steps pwms stdout-path enable-active-high gpio vin-supply regulator-boot-on io-channels io-channel-names temperature-lookup-table no-map label sdb-gpios 