Ðþí  ³   8  ð   (            Ã  ¸                             O    renesas,smarc2-evk renesas,rzg3l-smarcm renesas,r9a08g046l48 renesas,r9a08g046                                   &         2   7Renesas SMARC EVK version 2 based on r9a08g046l48      cpus                                cpu@0             arm,cortex-a55           =             Acpu          M            ^psci          cpu@100           arm,cortex-a55           =            Acpu          M            ^psci          cpu@200           arm,cortex-a55           =            Acpu          M            ^psci          cpu@300           arm,cortex-a55           =            Acpu          M            ^psci          cache-controller-0            cache             l         z            …            ‘            eth0-txc-tx-clk           fixed-clock          ™             ¦             ‘         eth0-rxc-rx-clk           fixed-clock          ™             ¦             ‘         eth1-txc-tx-clk           fixed-clock          ™             ¦             ‘         eth1-rxc-rx-clk           fixed-clock          ™             ¦             ‘         extal-clk             fixed-clock          ™             ¦n6          ‘         psci              arm,psci-1.0 arm,psci-0.2            esmc       soc           simple-bus                                    ¶   serial@100ac000       .    renesas,scif-r9a08g046 renesas,scif-r9a07g044            =    
À              H   ½      ‚         „         …         ƒ         †         †            Èeri rxi txi bri dri tei          Ø         r         ßfck          ë            ù      P         okay          i2c@100ae000             =    
à                                          okay             ¦ €      can@100c0000             =                      okay          clock-controller@11010000             renesas,r9a08g046-cpg            =                      Ø                     F   ßextal eth0_txc_tx_clk eth0_rxc_rx_clk eth1_txc_tx_clk eth1_rxc_rx_clk            ™                                   ‘         system-controller@11020000            renesas,r9a08g046-sysc           =                   0   ½       ,          -          .          /         1   Èlpm_int ca55stbydone_int cm33stbyr_int ca55_deny          pinctrl@11030000             =                      (        8         mmc@11c10000             =    Á                 D            N         [         okay          pcie@11e40000            =    ä                  ¶       0       0                   Apci                                  okay       pcie@0,0             =                              ¶         Apci                                  interrupt-controller@12400000             arm,gic-v3            =    @             D                 i                         z         ½      	            ‘            timer             arm,armv8-timer       <   ½                                 
                  %   Èsec-phys phys virt hyp-phys hyp-virt          memory@48000000          Amemory           =    H       x         chosen          �ignore_loglevel         ˜serial3:115200n8          can-phy0              ti,tcan1042         ¤            ¯ z       	   disabled          can-phy1              ti,tcan1042         ¤            ¯ z       	   disabled          keys          
    gpio-keys         	   disabled          aliases         »/soc/serial@100ac000             	compatible #address-cells #size-cells interrupt-parent model reg device_type next-level-cache enable-method cache-unified cache-size cache-level phandle #clock-cells clock-frequency ranges interrupts interrupt-names clocks clock-names power-domains resets status #reset-cells #power-domain-cells gpio-controller #gpio-cells bus-width sd-uhs-sdr50 sd-uhs-sdr104 #interrupt-cells interrupt-controller bootargs stdout-path #phy-cells max-bitrate serial3 