Ðþí  ˜   8  
Ð   (            È  
˜                                                                   !   ,ARM Corstone1000 FPGA MPS3 board             2arm,corstone1000-mps3      aliases          =/soc/serial@1a510000             E/soc/serial@1a520000          chosen           Mserial0:115200n8          memory@88200000          Ymemory           eˆ   wà        interrupt-controller@1c000000            2arm,gic-400          i                          z          e     ð     ð    ð              �      	           š         l2-cache0            2cache             ¢         °            ¼            Ç   @         ×            š         clock-100000000          2fixed-clock          â             ïõá       	   ÿapb_pclk             š         clock-48000000           2fixed-clock          â             ïÜl          ÿsmclk         timer            2arm,armv8-timer       0   �                              
        clock-50000000           2fixed-clock          â             ïúð€         ÿuartclk          š         psci             2arm,psci-1.0 arm,psci-0.2           smc       soc          2simple-bus                                                    timer@1a220000           2arm,armv7-timer-mem          e"                                          frame@1a230000                        �                   e#              serial@1a510000          2arm,pl011 arm,primecell          eQ              �                  -              4uartclk apb_pclk          serial@1a520000          2arm,pl011 arm,primecell          eR              �                  -              4uartclk apb_pclk          mailbox@1b820000             2arm,mhuv2-tx arm,primecell           e‚             -         	  4apb_pclk             �       -           @           L                `okay          	  gdisabled          mailbox@1b830000             2arm,mhuv2-rx arm,primecell           eƒ             -         	  4apb_pclk             �       .           @           L                `okay          	  gdisabled             cpus                                 cpu@0            Ycpu          2arm,cortex-a35           e                npsci            |            ethernet@4010000             2smsc,lan9220 smsc,lan9115            e@             �mii          �       t           –            £      usb@40200000             2nxp,usb-isp1763          e@               �       r           ¶           Àhost             	interrupt-parent #address-cells #size-cells model compatible serial0 serial1 stdout-path device_type reg #interrupt-cells interrupt-controller interrupts phandle cache-unified cache-level cache-size cache-line-size cache-sets #clock-cells clock-frequency clock-output-names method ranges frame-number clocks clock-names #mbox-cells arm,mhuv2-protocols secure-status enable-method next-level-cache phy-mode reg-io-width smsc,irq-push-pull bus-width dr_mode 