Ðþí  Z   8  P   (            
                               &    bst,c1200-cdcu1.0-adas-4c2g bst,c1200                                    &BST C1200-96 CDCU1.0 4C2G      cpus                                cpu@0            ,cpu           arm,cortex-a78           8             <psci             J         cpu@1            ,cpu           arm,cortex-a78           8            <psci             J         cpu@2            ,cpu           arm,cortex-a78           8            <psci             J         cpu@3            ,cpu           arm,cortex-a78           8            <psci             J         l2-cache              cache            [             g         u            psci              arm,psci-1.0             Csmc       soc           simple-bus            }                                 „      serial@20008000           snps,dw-apb-uart             8      €                 •}x@         ¥       Ó            °            º            Çokay          interrupt-controller@32800000             arm,gic-v3            8    2€             2ˆ                   }                                 Î             ß         ¥      	            u            timer             arm,armv8-timer           ô         „         0   ¥                                 
         chosen           þserial0:115200n8          memory@810000000             ,memory        0   8          0      À                     @            	compatible #address-cells #size-cells model device_type reg enable-method next-level-cache cache-level cache-unified phandle ranges interrupt-parent clock-frequency interrupts reg-shift reg-io-width status #interrupt-cells interrupt-controller always-on stdout-path 