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@Uinterrupt-controller@10510000 arm,gic-400 @QRTV n U dma-controller@110004002mediatek,mt2712-uart-dmamediatek,mt6577-uart-dma  nghijklmnopqr  apdmaUadc@11001000mediatek,mt2712-auxadcmainTokayserial@11002000*mediatek,mt2712-uartmediatek,mt6577-uart  n[ baudbusEJtxrxTokayserial@11003000*mediatek,mt2712-uartmediatek,mt6577-uart0 n\ baudbusEJtxrx Tdisabledserial@11004000*mediatek,mt2712-uartmediatek,mt6577-uart@ n] baudbusEJtxrx Tdisabledserial@11005000*mediatek,mt2712-uartmediatek,mt6577-uartP n^ baudbusEJtxrx Tdisabledpwm@11006000mediatek,mt2712-pwm` nMPf  1topmainpwm1pwm2pwm3pwm4pwm5pwm6pwm7pwm8 Tdisabledi2c@11007000mediatek,mt2712-i2c p nT  maindma+ Tdisabledi2c@11008000mediatek,mt2712-i2c  nU  maindma+ Tdisabledi2c@11009000mediatek,mt2712-i2c  nV  maindma+ Tdisabledspi@1100a000mediatek,mt2712-spi+ nvlparent-clksel-clkspi-clk Tdisablednand-controller@1100e000mediatek,mt2712-nfc n`nfi_clkpad_clk+ Tdisabledecc@1100f000mediatek,mt2712-ecc n_ nfiecc_clk TdisabledUi2c@11010000mediatek,mt2712-i2c  nW  maindma+ Tdisabledi2c@11011000mediatek,mt2712-i2c  nX  maindma+ Tdisabledi2c@11013000mediatek,mt2712-i2c 0 nZ  maindma+ Tdisabledspi@11015000mediatek,mt2712-spi+P nlparent-clksel-clkspi-clk Tdisabledspi@11016000mediatek,mt2712-spi+` nlparent-clksel-clkspi-clk Tdisabledspi@10012000mediatek,mt2712-spi+  nlparent-clksel-clkspi-clk Tdisabledspi@11018000mediatek,mt2712-spi+ nlparent-clksel-clkspi-clk Tdisabledserial@11019000*mediatek,mt2712-uartmediatek,mt6577-uart n~ baudbusE Jtxrx Tdisabledstmmac-axi-config Urx-queues-config$:Uqueue0K^vtx-queues-configU queue0Kvqueue1Kvqueue2Kvethernet@1101c000&mediatek,mt2712-gmacsnps,dwmac-4.20a nmacirqU{}'axiapbmac_mainptp_refrmii_internal("%[k=> )4?Tokay Lrgmii-rxidU!` u"W ''defaultsleep#$mdiosnps,dwmac-mdio+ethernet-phy@5ethernet-phy-id0243.0d90U!mmc@11230000mediatek,mt2712-mmc# nO  *&,sourcehclksource_cgbus_clk Tdisabledmmc@11240000mediatek,mt2712-mmc$ nP c'sourcehclksource_cg Tdisabledmmc@11250000mediatek,mt2712-mmc% nQc(sourcehclksource_cg Tdisabledusb@11271000#mediatek,mt2712-mtu3mediatek,mtu3 '0( macippc nz%&nsys_ck +Tokay'( otg#default)usb@11270000'mediatek,mt2712-xhcimediatek,mtk-xhci'mac n{ n*sys_ckref_ckTokay+t-phy@11290000.mediatek,mt2712-tphymediatek,generic-tphy-v2+)Tokayusb-phy@0*ref8TokayU%usb-phy@8000*ref8TokayU&usb-phy@8700 *ref8TokayU3usb@112c1000#mediatek,mt2712-mtu3mediatek,mtu3 ,0- macippc n,-.nsys_ck +Tokay/0 otgCdefault1usb@112c0000'mediatek,mt2712-xhcimediatek,mtk-xhci,mac n n*sys_ckref_ckTokayt-phy@112e0000.mediatek,mt2712-tphymediatek,generic-tphy-v2+.Tokayusb-phy@0*ref8TokayU,usb-phy@8000*ref8TokayU-usb-phy@8700 *ref8TokayU.pcie@112ff000mediatek,mt2712-pcievpci/port1U+ nu pcie_irq$sys_ck1ahb_ck1. fpcie-phy1p@@0 Tdisabledz`2222interrupt-controllerU2pcie@11700000mediatek,mt2712-pcievpcipport0U+ ns pcie_irq#sys_ck0ahb_ck03 fpcie-phy0p  Tdisabledz`4444interrupt-controllerU4syscon@13000000mediatek,mt2712-mfgcfgsysconNsyscon@14000000mediatek,mt2712-mmsyssysconNU6larb@14021000mediatek,mt2712-smi-larb566apbsmiUsmi@14022000mediatek,mt2712-smi-common 66apbsmiU5larb@14027000mediatek,mt2712-smi-larbp76,6,apbsmiUlarb@14030000mediatek,mt2712-smi-larb76.6.apbsmiUsmi@14031000mediatek,mt2712-smi-common6-6-apbsmiU7larb@14032000mediatek,mt2712-smi-larb 76868apbsmiUsyscon@15000000mediatek,mt2712-imgsyssysconNU8larb@15001000mediatek,mt2712-smi-larb588apbsmiUsyscon@15010000mediatek,mt2712-bdpsyssysconNsyscon@16000000mediatek,mt2712-vdecsyssysconNU9larb@16010000mediatek,mt2712-smi-larb599apbsmiUsyscon@18000000mediatek,mt2712-vencsyssysconNU:larb@18001000mediatek,mt2712-smi-larb5::apbsmiUlarb@18002000mediatek,mt2712-smi-larb 5::apbsmiUsyscon@19000000!mediatek,mt2712-jpgdecsyssysconNaliases/serial@11002000memory@40000000vmemory@chosenserial0:921600n8regulator-vproc-buck0regulator-fixed vproc_buck0B@B@Uregulator-vproc-buck1regulator-fixed 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compatibleinterrupt-parent#address-cells#size-cellsmodelchassis-typeopp-sharedphandleopp-hzopp-microvoltcpudevice_typeregclocksclock-namesproc-supplyoperating-points-v2cpu-idle-statesenable-methodentry-methodlocal-timer-stopentry-latency-usexit-latency-usmin-residency-usarm,psci-suspend-paramclock-frequency#clock-cellsclock-output-namesinterrupts#reset-cellsmediatek,pctl-regmapgpio-controller#gpio-cellsinterrupt-controller#interrupt-cellspinmuxdrive-strengthinput-enableinput-disablebias-disablebias-pull-up#power-domain-cellsinfracfgdmasdma-namesstatusassigned-clocksassigned-clock-parentsmediatek,infracfgmediatek,larbs#iommu-cellsdma-requests#dma-cells#io-channel-cells#pwm-cellsclock-divecc-enginesnps,wr_osr_lmtsnps,rd_osr_lmtsnps,blensnps,rx-queues-to-usesnps,rx-sched-spsnps,dcb-algorithmsnps,map-to-dma-channelsnps,prioritysnps,tx-queues-to-usesnps,tx-sched-wrrsnps,weightinterrupt-namesmac-addresspower-domainsmediatek,pericfgsnps,axi-configsnps,mtl-rx-configsnps,mtl-tx-configsnps,txpblsnps,rxpblsnps,clk-csrphy-modephy-handlemediatek,tx-delay-pssnps,reset-gpiosnps,reset-delays-uspinctrl-namespinctrl-0pinctrl-1mediatek,mac-wolreg-namesphysmediatek,syscon-wakeuprangesvbus-supplyextcondr_modewakeup-sourcemediatek,u3p-dis-msk#phy-cellsenable-manual-drdlinux,pci-domainphy-namesbus-rangeinterrupt-map-maskinterrupt-mapmediatek,smimediatek,larb-idserial0stdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltid-gpiosenable-active-highregulator-always-on