Ðþí 
   8  ô   (              óÌ                             t    google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192                                  +            7Google Spherion (rev0 - 3)           =laptop     aliases          J/soc/ovl@14005000            O/soc/ovl@14006000            W/soc/ovl@14014000            _/soc/rdma@14007000           e/soc/rdma@14015000           k/soc/i2c@11f00000            p/soc/i2c@11d20000            u/soc/i2c@11d21000            z/soc/i2c@11cb0000            /soc/i2c@11d00000            „/soc/mmc@11f60000            ‰/soc/mmc@11f70000            Ž/soc/serial@11002000          fixed-factor-clock-13m            fixed-factor-clock           –             £            ª            ´            ¿clk13m           Ò   &      oscillator0           fixed-clock          –             ÚŒº€         ¿clk26m           Ò         oscillator1           fixed-clock          –             Ú  €          ¿clk32k        cpus                         +       cpu@0            êcpu           arm,cortex-a55           ö             úpsci             Úec3@                        €         %   @        7   €        D  €         Q   @        c   €        p           �               •  «        ¨            Ò   
      cpu@100          êcpu           arm,cortex-a55           ö            úpsci             Úec3@                        €         %   @        7   €        D  €         Q   @        c   €        p           �               •  «        ¨            Ò         cpu@200          êcpu           arm,cortex-a55           ö            úpsci             Úec3@                        €         %   @        7   €        D  €         Q   @        c   €        p           �               •  «        ¨            Ò         cpu@300          êcpu           arm,cortex-a55           ö            úpsci             Úec3@                        €         %   @        7   €        D  €         Q   @        c   €        p           �               •  «        ¨            Ò         cpu@400          êcpu           arm,cortex-a76           ö            úpsci             Ú�fÔÀ                                 %   @        7           D           Q   @        c           p   	        �              •           ¨            Ò         cpu@500          êcpu           arm,cortex-a76           ö            úpsci             Ú�fÔÀ                                 %   @        7           D           Q   @        c           p   	        �              •           ¨            Ò         cpu@600          êcpu           arm,cortex-a76           ö            úpsci             Ú�fÔÀ                                 %   @        7           D           Q   @        c           p   	        �              •           ¨            Ò         cpu@700          êcpu           arm,cortex-a76           ö            úpsci             Ú�fÔÀ                                 %   @        7           D           Q   @        c           p   	        �              •           ¨            Ò         cpu-map    cluster0       core0           ·   
      core1           ·         core2           ·         core3           ·         core4           ·         core5           ·         core6           ·         core7           ·               l2-cache0             cache           »                      '   @        9           p            Ç         Ò         l2-cache1             cache           »                      '   @        9           p            Ç         Ò   	      l3-cache              cache           »                       '   @        9            Ç         Ò         idle-states         Õpsci       cpu-retention-l           arm,idle-state          â           ù        
   7           Œ        +           Ò         cpu-retention-b           arm,idle-state          â           ù        
   #           ‘        +  Ð         Ò         cpu-off-l             arm,idle-state          â          ù        
   <           ›        +  \         Ò         cpu-off-b             arm,idle-state          â          ù        
   (           ›        +           Ò               pmu-a55           arm,cortex-a55-pmu                      <                  pmu-a76           arm,cortex-a76-pmu                      <                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  <                                             
                Ú Æ]@      opp-table-0           operating-points-v2          G         Ò   ^   opp-358000000           R    V¥€        Y 	@*      opp-399000000           R    ÈAÀ        Y 	pþ      opp-440000000           R    9Þ         Y 	¡Ò      opp-482000000           R    º¼€        Y 	Ò¦      opp-523000000           R    ,XÀ        Y 
z      opp-564000000           R    !�õ         Y 
4N      opp-605000000           R    $‘@        Y 
e"      opp-647000000           R    &�oÀ        Y 
•ö      opp-688000000           R    )         Y 
ÆÊ      opp-724000000           R    +']         Y       opp-748000000           R    ,•“         Y @Ü      opp-772000000           R    .É         Y q°      opp-795000000           R    /b¼À        Y ¢„      opp-819000000           R    0ÐòÀ        Y ÓX      opp-843000000           R    2?(À        Y ,      opp-866000000           R    3ž€        Y 5          soc                      +             simple-bus          g                                k   performance-controller@11bc10             mediatek,cpufreq-hw           ö     ¼            ½0               r            Ò         interrupt-controller@c000000              arm,gic-v3          Œ           �                        ´          ö                                    <      	                É         Ò      ppi-partitions     interrupt-partition-0           é   
                  Ò         interrupt-partition-1           é                     Ò               syscon@10000000            mediatek,mt8192-topckgen syscon          ö                       –            Ò         syscon@10001000            mediatek,mt8192-infracfg syscon          ö                      –           ò            Ò         syscon@10003000           mediatek,mt8192-pericfg syscon           ö     0                 –            Ò   3      pinctrl@10005000              mediatek,mt8192-pinctrl       °   ö     P            Â             Ñ             Ó             Ô             â             ç             ê             ò             ó              °              ]  ÿiocfg0 iocfg_rm iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_lb iocfg_rt iocfg_lt iocfg_tl eint             	                   %              Ü         ´        <       Ô               Œ        	€  1I2S_DP_LRCK IS_DP_BCLK I2S_DP_MCLK I2S_DP_DATAOUT SAR0_INT_ODL EC_AP_INT_ODL EDPBRDG_INT_ODL DPBRDG_INT_ODL DPBRDG_PWREN DPBRDG_RST_ODL I2S_HP_MCLK I2S_HP_BCK I2S_HP_LRCK I2S_HP_DATAIN AP_FLASH_WP_L TRACKPAD_INT_ODL EC_AP_HPD_OD SD_CD_ODL HP_INT_ODL_ALC EN_PP1000_DPBRDG AP_GPIO20 TOUCH_INT_L_1V8 UART_BT_WAKE_ODL AP_GPIO23 AP_SPI_FLASH_CS_L AP_SPI_FLASH_CLK EN_PP3300_DPBRDG_DX AP_SPI_FLASH_MOSI AP_SPI_FLASH_MISO I2S_HP_DATAOUT AP_GPIO30 I2S_SPKR_MCLK I2S_SPKR_BCLK I2S_SPKR_LRCK I2S_SPKR_DATAIN I2S_SPKR_DATAOUT AP_SPI_H1_TPM_CLK AP_SPI_H1_TPM_CS_L AP_SPI_H1_TPM_MISO AP_SPI_H1_TPM_MOSI BL_PWM EDPBRDG_PWREN EDPBRDG_RST_ODL EN_PP3300_HUB HUB_RST_L       SD_CLK SD_CMD SD_DATA3 SD_DATA0 SD_DATA2 SD_DATA1       PCIE_WAKE_ODL PCIE_RST_L PCIE_CLKREQ_ODL                        SPMI_SCL SPMI_SDA AP_GOOD UART_DBG_TX_AP_RX UART_AP_TX_DBG_RX UART_AP_TX_BT_RX UART_BT_TX_AP_RX MIPI_DPI_D0_R MIPI_DPI_D1_R MIPI_DPI_D2_R MIPI_DPI_D3_R MIPI_DPI_D4_R MIPI_DPI_D5_R MIPI_DPI_D6_R MIPI_DPI_D7_R MIPI_DPI_D8_R MIPI_DPI_D9_R MIPI_DPI_D10_R   MIPI_DPI_DE_R MIPI_DPI_D11_R MIPI_DPI_VSYNC_R MIPI_DPI_CLK_R MIPI_DPI_HSYNC_R PCM_BT_DATAIN PCM_BT_SYNC PCM_BT_DATAOUT PCM_BT_CLK AP_I2C_AUDIO_SCL AP_I2C_AUDIO_SDA SCP_I2C_SCL SCP_I2C_SDA AP_I2C_WLAN_SCL AP_I2C_WLAN_SDA AP_I2C_DPBRDG_SCL AP_I2C_DPBRDG_SDA EN_PP1800_DPBRDG_DX EN_PP3300_EDP_DX EN_PP1800_EDPBRDG_DX EN_PP1000_EDPBRDG SCP_JTAG0_TDO SCP_JTAG0_TDI SCP_JTAG0_TMS SCP_JTAG0_TCK SCP_JTAG0_TRSTN EN_PP3000_VMC_PMU EN_PP3300_DISPLAY_DX TOUCH_RST_L_1V8 TOUCH_REPORT_DISABLE   AP_I2C_TRACKPAD_SCL_1V8 AP_I2C_TRACKPAD_SDA_1V8 EN_PP3300_WLAN BT_KILL_L WIFI_KILL_L SET_VMC_VOLT_AT_1V8 EN_SPK AP_WARM_RST_REQ   EN_PP3000_SD_S3 AP_EDP_BKLTEN    AP_SPI_EC_CLK AP_SPI_EC_CS_L AP_SPI_EC_MISO AP_SPI_EC_MOSI AP_I2C_EDPBRDG_SCL AP_I2C_EDPBRDG_SDA MT6315_PROC_INT MT6315_GPU_INT UART_SERVO_TX_SCP_RX UART_SCP_TX_SERVO_RX BT_RTS_AP_CTS AP_RTS_BT_CTS UART_AP_WAKE_BT_ODL WLAN_ALERT_ODL EC_IN_RW_ODL H1_AP_INT_ODL            MSDC0_CMD MSDC0_DAT0 MSDC0_DAT2 MSDC0_DAT4 MSDC0_DAT6 MSDC0_DAT1 MSDC0_DAT5 MSDC0_DAT7 MSDC0_DSL MSDC0_CLK MSDC0_DAT3 MSDC0_RST_L SCP_VREQ_VAO AUD_DAT_MOSI2 AUD_NLE_MOSI1 AUD_NLE_MOSI0 AUD_DAT_MISO2 AP_I2C_SAR_SDA AP_I2C_SAR_SCL AP_I2C_PWR_SCL AP_I2C_PWR_SDA AP_I2C_TS_SCL_1V8 AP_I2C_TS_SDA_1V8 SRCLKENA0 SRCLKENA1 AP_EC_WATCHDOG_L PWRAP_SPI0_MI PWRAP_SPI0_CSN PWRAP_SPI0_MO PWRAP_SPI0_CK AP_RTC_CLK32K AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1          Ò      anx7625-default-pins             Ò   @   pins-out            A  )   *          H      pins-in         A            S         `         aud-clk-mosi-off-pins            Ò   Š   pins-mosi-off           A  Ö   ×          aud-clk-mosi-on-pins             Ò   ‹   pins-mosi-on            A  Ö  ×        m   
         aud-dat-miso-ch34-off-pins           Ò       pins-miso-off           A  Ç          aud-dat-miso-ch34-on-pins            Ò   ¡   pins-miso-on            A  Ç         aud-dat-miso-off-pins            Ò   Ž   pins-miso-off           A  Ú   Û          aud-dat-miso-on-pins             Ò   �   pins-miso-on            A  Ú  Û        m   
         aud-dat-miso2-off-pins           Ò   –   pins-miso-off           A  Ç          aud-dat-miso2-on-pins            Ò   —   pins-miso-on            A  Ç         aud-dat-mosi-ch34-off-pins           Ò   ž   pins-mosi-off           A  Ä          aud-dat-mosi-ch34-on-pins            Ò   Ÿ   pins-mosi-on            A  Ä         aud-dat-mosi-off-pins            Ò   Œ   pins-mosi-off           A  Ø   Ù          aud-dat-mosi-on-pins             Ò   �   pins-mosi-on            A  Ø  Ù        m   
         aud-gpio-i2s3-off-pins           Ò   ˜   pins-i2s3-off           A      !   #          aud-gpio-i2s3-on-pins            Ò   ™   pins-i2s3-on            A     !  #         aud-gpio-i2s8-off-pins           Ò   š   pins-i2s8-off           A  
                   aud-gpio-i2s8-on-pins            Ò   ›   pins-i2s8-on            A  
               aud-gpio-i2s9-off-pins           Ò   œ   pins-i2s9-off           A            aud-gpio-i2s9-on-pins            Ò   �   pins-i2s9-on            A           aud-gpio-tdm-off-pins            Ò   ¢   pins-tdm-off            A                      aud-gpio-tdm-on-pins             Ò   £   pins-tdm-on         A                  aud-nle-mosi-off-pins            Ò   ”   pins-nle-mosi-off           A  Å   Æ          aud-nle-mosi-on-pins             Ò   •   pins-nle-mosi-on            A  Å  Æ         cr50-irq-default-pins            Ò   -   pins-gsc-ap-int-odl         A  «          S         cros-ec-irq-default-pins             Ò   +   pins-ec-ap-int-odl          A            S         `         i2c0-default-pins            Ò   S   pins-bus            A  Ì  Í        `   Ë        |  è         i2c1-default-pins            Ò   K   pins-bus            A  v  w        `   Ë        |  è         i2c2-default-pins            Ò   N   pins-bus            A  �  Ž        `   Ë         i2c3-default-pins            Ò   ?   pins-bus            A     ¡         ”        |  è         i2c7-default-pins            Ò   I   pins-bus            A  |  }         ”        |  è         mmc0-default-pins            Ò   V   pins-cmd-dat          $  A  ¸  ¼  ¹  Á  º  ½  »  ¾  ·         S        m           `   e      pins-clk            A  À        m           ¡   f      pins-rst            A  Â        m           ¡   e         mmc0-uhs-pins            Ò   W   pins-cmd-dat          $  A  ¸  ¼  ¹  Á  º  ½  »  ¾  ·         S        m   
        `   e      pins-clk            A  À        m   
        ¡   f      pins-rst            A  Â        m           ¡   e      pins-ds         A  ¿        m   
        ¡   f         mmc1-default-pins            Ò   Z   pins-cmd-dat            A  6  8  7  5  4         S        m           `   e      pins-clk            A  3        m           ¡   f      pins-insert         A            S         `         mmc1-uhs-pins            Ò   [   pins-cmd-dat            A  6  8  7  5  4         S        m           `   e      pins-clk            A  3         S        m           ¡   f         nor-flash-default-pins           Ò   =   pins-cs-io1         A             S         `        m   
      pins-io0            A           `        m   
      pins-clk            A           S         `        m   
         pcie-default-pins            Ò   ;   pins-pcie-wake          A  ?         `      pins-pcie-pereset           A  @      pins-pcie-clkreq            A  A         `      pins-wifi-kill          A  ‘          °         pp1000-dpbrdg-en-pins            Ò   €   pins-en         A            H         pp1000-mipibrdg-en-pins          Ò   ‚   pins-en         A  �          H         pp1800-dpbrdg-en-pins            Ò   ƒ   pins-en         A  ~          H         pp1800-mipibrd-en-pins           Ò   „   pins-en         A  €          H         pp3300-dpbrdg-en-pins            Ò   …   pins-en         A            H         pp3300-mipibrdg-en-pins          Ò   †   pins-en         A            H         pp3300-wlan-pins             Ò   ‡   pins-pcie-en-pp3300-wlan            A  �          °         pwm0-default-pins            Ò   )   pins-pwm            A  (      pins-inhibit            A  ˜          °         rt1015p-default-pins             Ò   ˆ   pins            A  “          H         scp-pins             Ò   /   pins-vreq-vao           A  Ã         spi1-default-pins            Ò   *   pins-cs-mosi-clk            A  �  Ÿ  œ         ”      pins-miso           A  ž         ¡         spi5-default-pins            Ò   ,   pins-bus            A  &  %   '  $         ”         trackpad-default-pins            Ò   O   pins-int-n          A            S        `   g         touchscreen-default-pins             Ò   T   pins-irq            A            S         `      pins-reset          A  ‰          °      pins-report-sw          A  Š          H         vow-clk-miso-off-pins            Ò   ’   pins-miso-off           A  Û          vow-clk-miso-on-pins             Ò   “   pins-miso-on            A  Û         vow-dat-miso-off-pins            Ò   �   pins-miso-off           A  Ú          vow-dat-miso-on-pins             Ò   ‘   pins-miso-on            A  Ú            syscon@10006000       )    mediatek,mt8192-scpsys syscon simple-mfd             ö     `           power-controller          !    mediatek,mt8192-power-controller                         +            ¼            Ò   7   power-domain@0           ö             £            :      /        Ðaudio audio1 audio2         Ü           ¼          power-domain@1           ö            £              Ðconn            Ü           ¼          power-domain@2           ö            £                    Ðmfg alt                      +            ¼           î      power-domain@3           ö           Ü                        +            ¼           î      power-domain@4           ö           ¼          power-domain@5           ö           ¼          power-domain@6           ö           ¼          power-domain@7           ö           ¼          power-domain@8           ö           ¼                power-domain@9           ö   	      (   £                                    !  Ðdisp disp-0 disp-1 disp-2 disp-3            Ü                        +            ¼      power-domain@10          ö   
      (   £                                       Ðipe ipe-0 ipe-1 ipe-2 ipe-3         Ü           ¼          power-domain@11          ö            £                           Ðisp isp-0 isp-1         Ü           ¼          power-domain@12          ö            £                           Ðisp2 isp2-0 isp2-1          Ü           ¼          power-domain@13          ö            £                  
  Ðmdp mdp-0           Ü           ¼          power-domain@14          ö            £      3              Ðvenc venc-0         Ü           ¼          power-domain@15          ö             £      4                              Ðvdec vdec-0 vdec-1 vdec-2           Ü                        +            ¼      power-domain@16          ö            £   !      !      !            Ðvdec2-0 vdec2-1 vdec2-2         ¼             power-domain@17          ö         (   £      
   "       "      "      "           Ðcam cam-0 cam-1 cam-2 cam-3         Ü                        +            ¼      power-domain@18          ö            £   #            Ðcam_rawa-0          ¼          power-domain@19          ö            £   $            Ðcam_rawb-0          ¼          power-domain@20          ö            £   %            Ðcam_rawc-0          ¼                      watchdog@10007000             mediatek,mt8192-wdt          ö     p                ò            Ò   6      syscon@1000c000       "    mediatek,mt8192-apmixedsys syscon            ö     À                 –            Ò   2      timer@10017000        ,    mediatek,mt8192-timer mediatek,mt6765-timer          ö    p                <       é                £   &      pwrap@10026000            mediatek,mt6873-pwrap            ö    `                ÿpwrap           <       Ü                £                   	  Ðspi wrap            ü                    ƒ   pmic              mediatek,mt6359          ´        Œ           #           4      Ö      adc           mediatek,mt6359-auxadc          H         audio-codec           mediatek,mt6359-codec           Z           m           �         regulators            mediatek,mt6359-regulator      buck_vs1            •vs1         ¤ 5         ¼ !‘À        Ô             ð      buck_vgpu11         •vgpu11          ¤ €        ¼ 7          ˆ        Ô   È                           ð      buck_vmodem         •vmodem          ¤ €        ¼ Èà          *        Ô   È      buck_vpu            •vpu         ¤ €        ¼ 7          ˆ        Ô   È                        buck_vcore          •vcore           ¤ €        ¼ Ö           ˆ        Ô   È                        buck_vs2            •vs2         ¤ 5         ¼ j         Ô             ð         Ò   �      buck_vpa            •vpa         ¤ ¡         ¼ 7±Ð        Ô  ,      buck_vproc2         •vproc2          ¤ €        ¼ 7          L        Ô   È                        buck_vproc1         •vproc1          ¤ €        ¼ 7          L        Ô   È                        buck_vcore_sshub            •vcore_sshub         ¤ €        ¼ 7      buck_vgpu11_sshub           •vgpu11_sshub            ¤ Æ        ¼ Æ         ð      ldo_vaud18          •vaud18          ¤ w@        ¼ w@        Ô   ð      ldo_vsim1           •vsim1           ¤ ð         ¼ /M`      ldo_vibr            •vibr            ¤ O€        ¼ 2Z       ldo_vrf12           •vrf12           ¤ Èà        ¼ Ö          ð      ldo_vusb            •vusb            ¤ -ÆÀ        ¼ -ÆÀ        Ô  À         ð      ldo_vsram_proc2         •vsram_proc2         ¤ ¡         ¼ ½¶          L        Ô   ð         ð      ldo_vio18           •vio18           ¤ ð         ¼ ýà        Ô  À         ð         Ò   L      ldo_vcamio          •vcamio          ¤ ð         ¼ ýà      ldo_vcn18           •vcn18           ¤ w@        ¼ w@        Ô   ð      ldo_vfe28           •vfe28           ¤ *¹€        ¼ *¹€        Ô   x      ldo_vcn13           •vcn13           ¤ »         ¼ Ö       ldo_vcn33_1_bt          •vcn33_1_bt          ¤ *¹€        ¼ 5gà      ldo_vcn33_1_wifi            •vcn33_1_wifi            ¤ *¹€        ¼ 5gà      ldo_vaux18          •vaux18          ¤ w@        ¼ w@        Ô   ð         ð      ldo_vsram_others            •vsram_others            ¤ q°        ¼ 5           ˆ        Ô   ð        1           H  '         Ò         ldo_vefuse          •vefuse          ¤ ð         ¼ „€      ldo_vxo22           •vxo22           ¤ w@        ¼ !‘À         ð      ldo_vrfck           •vrfck           ¤ ã`        ¼ ð       ldo_vrfck_1         •vrfck_1         ¤ ëÀ        ¼ j       ldo_vbif28          •vbif28          ¤ *¹€        ¼ *¹€        Ô   ð      ldo_vio28           •vio28           ¤ *¹€        ¼ 2Z          ð      ldo_vemc            •vemc            ¤ ,@         ¼ 2Z       ldo_vemc_1          •vemc_1          ¤ &%         ¼ 2Z          Ò   X      ldo_vcn33_2_bt          •vcn33_2_bt          ¤ *¹€        ¼ 5gà      ldo_vcn33_2_wifi            •vcn33_2_wifi            ¤ *¹€        ¼ 5gà      ldo_va12            •va12            ¤ O€        ¼ Ö          ð      ldo_va09            •va09            ¤ 5         ¼ O€      ldo_vrf18           •vrf18           ¤ ð         ¼ žP      ldo_vsram_md          	  •vsram_md            ¤ ¡         ¼ ½¶          *        Ô   ð      ldo_vufs            •vufs            ¤ ð         ¼ ýà         ð         Ò   Y      ldo_vm18            •vm18            ¤ ð         ¼ ýà         ð      ldo_vbbck           •vbbck           ¤ Èà        ¼ O€      ldo_vsram_proc1         •vsram_proc1         ¤ ¡         ¼ ½¶          L        Ô   ð         ð      ldo_vsim2           •vsim2           ¤ ð         ¼ /M`      ldo_vsram_others_sshub          •vsram_others_sshub          ¤ ¡         ¼ ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt6873-spmi              ö    p            �                ÿpmif spmimst             £                   8      (  Ðpmif_sys_ck pmif_tmr_ck spmimst_clk_mux         ü                    ƒ                     +       pmic@6            mediatek,mt6315-regulator            ö          regulators     vbuck1          •Vbcpu           ¤ €        ¼ 7        Ô                              ð      vbuck3          •Vlcpu           ¤ €        ¼ 7        Ô                              ð            pmic@7            mediatek,mt6315-regulator            ö          regulators     vbuck1          •Vgpu            ¤ €        ¼ 5         Ô                             1           H  '         Ò                  mailbox@10228000              mediatek,mt8192-gce          ö    "€       @         <       Ë               e            £              Ðgce          Ò   _      clock-controller@10720000             mediatek,mt8192-scp_adsp             ö    r                  –           qfail          serial@11002000       *    mediatek,mt8192-uart mediatek,mt6577-uart            ö                      <       m                £               	  Ðbaud bus            qokay          serial@11003000       *    mediatek,mt8192-uart mediatek,mt6577-uart            ö     0                <       n                £               	  Ðbaud bus          	  qdisabled          clock-controller@11007000             mediatek,mt8192-imp_iic_wrap_c           ö     p                 –         spi@1100a000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö                      <       Ÿ                £      M                    Ðparent-clk sel-clk spi-clk        	  qdisabled          thermal-sensor@1100b000           mediatek,mt8192-lvts-ap          ö     °                <       ©                £      	        x                  '        ‹lvts-calib-data-1           œ            Ò   }      svs@1100bc00              mediatek,mt8192-svs          ö     ¼                <       §                £      	        Ðmain               (   '      (  ‹svs-calibration-data t-calibration-data         x              ²svs_rst       pwm@1100e000              mediatek,mt8183-disp-pwm             ö     à                <       «               ¾            £      !      8        Ðmain mm         qokay            Édefault         ×   )         Ò   ~      spi@11010000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö                     <                        £      M            <        Ðparent-clk sel-clk spi-clk          qokay            á            Édefault         ×   *   ec@0              google,cros-ec-spi           ö            4                 õ -ÆÀ        Édefault         ×   +                              +       pwm           google,cros-ec-pwm          ¾           qokay             Ò   ¦      i2c-tunnel            google,cros-ec-i2c-tunnel                                    +       sbs-battery@b             sbs,sbs-battery          ö           '           ;            regulator@0           google,cros-ec-regulator             ö            ¤ w@        ¼ 2Z          Ò   ]      regulator@1           google,cros-ec-regulator             ö           ¤ 2Z         ¼ 2Z          Ò   \      typec             google,cros-ec-typec                         +       connector@0           usb-c-connector          ö            Pleft            Vdual            ahost            ksource        connector@1           usb-c-connector          ö           Pright           Vdual            ahost            ksource           keyboard-controller           google,cros-ec-keyb         z           Š            �     D  ·  ž ­t x c à á	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	 Ž + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      (  Ä               	  	                 spi@11012000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö                     <       ¡                £      M            >        Ðparent-clk sel-clk spi-clk        	  qdisabled          spi@11013000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö    0                <       ¢                £      M            ?        Ðparent-clk sel-clk spi-clk        	  qdisabled          spi@11018000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö    €                <       £                £      M            L        Ðparent-clk sel-clk spi-clk        	  qdisabled          spi@11019000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö    �                <       ¤                £      M            M        Ðparent-clk sel-clk spi-clk          qokay            Ù      %           á            Édefault         ×   ,   tpm@0             google,cr50          ö            4      «           õ B@        Édefault         ×   -         spi@1101d000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö    Ð                <       ¥                £      M            m        Ðparent-clk sel-clk spi-clk        	  qdisabled          spi@1101e000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö    à                <       ¦                £      M            n        Ðparent-clk sel-clk spi-clk        	  qdisabled          scp@10500000              mediatek,mt8192-scp       0   ö    P             r             p        €         ÿsram cfg l1tcm          <      ³                £              Ðmain            qokay            âmediatek/mt8192/scp.img         ð   .        Édefault         ×   /         Ò   s   cros-ec-rpmsg             google,cros-ec-rpmsg            þcros-ec-rpmsg            usb@11200000          '    mediatek,mt8192-xhci mediatek,mtk-xhci            ö                   >              	  ÿmac ippc            4          a               host            "   0      1           ü      "      #              ]      ]          £      7   2               R      $  Ðsys_ck ref_ck mcu_ck dma_ck xhci_ck                  '   3      f        qokay            >   4        L   5      syscon@11210000           mediatek,mt8192-audsys syscon            ö    !                   –            Ò   8   audio-controller              mediatek,mt8192-audio           <       Ê               x   6         	  ²audiosys            X   2        Ü           l           ~   7         ¼   £   8       8      8      8      8      8      8      8      8      8      8   	   8   
   8      8      8      8      8      8      8      8         /      :                  H      /      e      0      i      +      g      ,      k      ;      <      =      >      ?      @      A      B      C      D      Ž      �      �      ‘      ’      “      ”      •      –      —      ˜      7        u  Ðaud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adda6_adc_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_tdm_clk aud_tml_clk aud_nle aud_dac_hires_clk aud_adc_hires_clk aud_adc_hires_tml aud_adda6_adc_hires_clk aud_3rd_dac_clk aud_3rd_dac_predis_clk aud_3rd_dac_tml aud_3rd_dac_hires_clk aud_infra_clk aud_infra_26m_clk top_mux_audio top_mux_audio_int top_mainpll_d4_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d4 top_mux_aud_eng2 top_apll2_d4 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_i2s6_m_sel top_i2s7_m_sel top_i2s8_m_sel top_i2s9_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_apll12_div5 top_apll12_div6 top_apll12_div7 top_apll12_div8 top_apll12_div9 top_mux_audio_h top_clk26m_clk            ð   9         Ò   ‰         pcie@11230000             mediatek,mt8192-pcie             êpci          ö    #                	  ÿpcie-mac                         +         0   £      +      '      *      j      ^      \      /  Ðpl_250m tl_26m tl_96m tl_32k peri_26m top_133m          ü      )              Q        <       û               Œ       ÿ      8  k‚                      €  �       €      €       €          Œ           –                     `  ©                  :                      :                     :                     :           Édefault         ×   ;        ð   <   interrupt-controller             ´                     Œ            Ò   :      pcie@0,0             êpci          ö                            ·           Œ                           +            k   wifi@0,0          (   ö                                               spi@11234000              mediatek,mt8192-nor          ö    #@        à        <      ¯                £      :      w      ]        Ðspi sf axi          ü      :              b                     +            qokay            Édefault         ×   =   flash@0            winbond,w25q64jwm jedec,spi-nor          ö            õu         Á           Ò            thermal-sensor@11278000           mediatek,mt8192-lvts-mcu             ö    '€                <       ª                £      	        x                 '        ‹lvts-calib-data-1           œ            Ò   t      efuse@11c10000        %    mediatek,mt8192-efuse mediatek,efuse             ö    Á                              +      socinfo-data1@44             ö   D         socinfo-data2@50             ö   P         data1@1c0            ö  À   X         Ò   '      calib@580            ö  €   h         Ò   (         i2c@11cb0000              mediatek,mt8192-i2c           ö    Ë             !s        €        <       s                £   >          x      	  Ðmain dma             ª                        +            qokay             Ú €        Édefault         ×   ?   anx7625@58            analogix,anx7625             ö   X        Édefault         ×   @        ã      )            ð      *            ü   A        	   B           C   ports                        +       port@0           ö       endpoint            #   D         Ò   c         port@1           ö      endpoint            #   E         Ò   G            aux-bus    panel         
    edp-panel           3   C        @   F   port       endpoint            #   G         Ò   E                     clock-controller@11cb1000             mediatek,mt8192-imp_iic_wrap_e           ö    Ë                 –            Ò   >      i2c@11d00000              mediatek,mt8192-i2c           ö    Ð             !v       €        <       w                £   H          x      	  Ðmain dma             ª                        +            qokay             Ú €        Édefault         ×   I      i2c@11d01000              mediatek,mt8192-i2c           ö    Ð            !w€      €        <       x                £   H         x      	  Ðmain dma             ª                        +          	  qdisabled          i2c@11d02000              mediatek,mt8192-i2c           ö    Ð             !y       €        <       y                £   H         x      	  Ðmain dma             ª                        +          	  qdisabled          clock-controller@11d03000             mediatek,mt8192-imp_iic_wrap_s           ö    Ð0                 –            Ò   H      i2c@11d20000              mediatek,mt8192-i2c           ö    Ò             !q        €        <       q                £   J          x      	  Ðmain dma             ª                        +            qokay             Ú €        Édefault         ×   K   audio-codec@1a           ö           4                 J           #           Y   L        e   L        r   L        �   4          realtek,rt5682i         �           ¤   M         Ò   ¥         i2c@11d21000              mediatek,mt8192-i2c           ö    Ò            !q€      €        <       r                £   J         x      	  Ðmain dma             ª                        +            qokay             Ú €        Édefault         ×   N   trackpad@15           elan,ekth3000            ö           Édefault         ×   O        4                 °   P                 qfail-needs-probe          trackpad@2c           hid-over-i2c             ö   ,        Édefault         ×   O        »            4                          qfail-needs-probe             i2c@11d22000              mediatek,mt8192-i2c           ö    Ò             !s€      €        <       t                £   J         x      	  Ðmain dma             ª                        +          	  qdisabled          clock-controller@11d23000              mediatek,mt8192-imp_iic_wrap_ws          ö    Ò0                 –            Ò   J      i2c@11e00000              mediatek,mt8192-i2c           ö    à             !u        €        <       u                £   Q          x      	  Ðmain dma             ª                        +          	  qdisabled          clock-controller@11e01000             mediatek,mt8192-imp_iic_wrap_w           ö    à                 –            Ò   Q      t-phy@11e40000        .    mediatek,mt8192-tphy mediatek,generic-tphy-v2                        +           k        ä        usb-phy@0            ö                £           Ðref         Ê            Ò   0      usb-phy@700          ö     	          £           Ðref         Ê            Ò   1         dsi-phy@11e50000              mediatek,mt8183-mipi-tx          ö    å                  £   2   
         –            Ê             ¿mipi_tx0_pll            qokay             Ò   b      i2c@11f00000              mediatek,mt8192-i2c           ö    ð             !p€       €        <       p                £   R          x      	  Ðmain dma             ª                        +            qokay             Ú €        Édefault         ×   S   touchscreen@10           ö           4                 Édefault         ×   T          elan,ekth3500            i2c@11f01000              mediatek,mt8192-i2c           ö    ð            !u€       €        <       v                £   R         x      	  Ðmain dma             ª                        +          	  qdisabled          clock-controller@11f02000             mediatek,mt8192-imp_iic_wrap_n           ö    ð                  –            Ò   R      clock-controller@11f10000             mediatek,mt8192-msdc_top             ö    ñ                  –            Ò   U      mmc@11f60000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc           ö    ö             õ                 <       c             8   £         U   	   U      U      U      U      U         3  Ðsource hclk source_cg sys_cg pclk_cg axi_cg ahb_cg          qokay            Édefault state_uhs           ×   V        Õ   W        È           ùëÂ         ß   X        ë   Y         ø         	
         	         	(         	5         	F        	` (         	o         	w         	}      mmc@11f70000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc           ö    ÷             Ç                 <       g             8   £         U   
   U      U      U      U      U         3  Ðsource hclk source_cg sys_cg pclk_cg axi_cg ahb_cg          qokay            Édefault state_uhs           ×   Z        Õ   [        È           ùëÂ         	‹                 ß   \        ë   ]         	”         	¥         	²         	o         	À      gpu@13000000          )    mediatek,mt8192-mali arm,mali-valhall-jm             ö             @       0  <      m             l             k               job mmu gpu          £   2         (  ~   7      7      7      7      7           	Çcore0 core1 core2 core3 core4           	Ú   ^        qokay            	î         clock-controller@13fbf000             mediatek,mt8192-mfgcfg           ö    ûð                 –         syscon@14000000           mediatek,mt8192-mmsys syscon             ö                       –           ò           	ú   _          _              
   _                   Ò         mutex@14001000            mediatek,mt8192-disp-mutex           ö                     <       ü                £               
   _                 
  ²  ³        ~   7   	      smi@14002000              mediatek,mt8192-smi-common           ö                        £                                Ðapb smi gals0 gals1         ~   7   	         Ò   `      larb@14003000             mediatek,mt8192-smi-larb             ö     0                
-            
>   `         £              Ðapb smi         ~   7   	         Ò   d      larb@14004000             mediatek,mt8192-smi-larb             ö     @                
-           
>   `         £              Ðapb smi         ~   7   	         Ò   e      ovl@14005000              mediatek,mt8192-disp-ovl             ö     P                <       þ                £              
K   a      a           ~   7   	        
   _     P          ovl@14006000              mediatek,mt8192-disp-ovl-2l          ö     `                <       ÿ               ~   7   	         £              
K   a   "   a            
   _     `          rdma@14007000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma          ö     p                <                       £              
K   a           
R           ~   7   	        
   _     p          color@14009000        6    mediatek,mt8192-disp-color mediatek,mt8173-disp-color            ö     �                <                     ~   7   	         £              
   _     �          ccorr@1400a000            mediatek,mt8192-disp-ccorr           ö                      <                     ~   7   	         £      	        
   _                aal@1400b000          2    mediatek,mt8192-disp-aal mediatek,mt8183-disp-aal            ö     °                <                     ~   7   	         £              
   _     °          gamma@1400c000        6    mediatek,mt8192-disp-gamma mediatek,mt8183-disp-gamma            ö     À                <                     ~   7   	         £              
   _     À          postmask@1400d000             mediatek,mt8192-disp-postmask            ö     Ð                <                     ~   7   	         £              
   _     Ð          dither@1400e000       8    mediatek,mt8192-disp-dither mediatek,mt8183-disp-dither          ö     à                <                     ~   7   	         £      
        
   _     à          dsi@14010000              mediatek,mt8183-dsi          ö                     <      	                £                b        Ðengine digital hs           "   b        
jdphy            ~   7   	        x              qokay       port       endpoint            #   c         Ò   D            ovl@14014000              mediatek,mt8192-disp-ovl-2l          ö    @                <                     ~   7   	         £              
K   a   #   a   !        
   _     @          rdma@14015000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma          ö    P                <                     ~   7   	         £              
K   a   %        
R           
   _     P          dpi@14016000              mediatek,mt8192-dpi          ö    `                <                      £      !         2           Ðpixel engine pll          	  qdisabled          m4u@1401d000              mediatek,mt8192-m4u          ö    Ð              <  
t   d   e   f   g   h   i   j   k   l   m   n   o   p   q   r        <                      £              Ðbclk            ~   7   	        
ƒ            Ò   a      clock-controller@15020000             mediatek,mt8192-imgsys           ö                      –            Ò         larb@1502e000             mediatek,mt8192-smi-larb             ö    à                
-   	        
>   `         £                      Ðapb smi         ~   7            Ò   j      clock-controller@15820000             mediatek,mt8192-imgsys2          ö    ‚                  –            Ò         larb@1582e000             mediatek,mt8192-smi-larb             ö    ‚à                
-           
>   `         £                      Ðapb smi         ~   7            Ò   k      video-codec@16000000              mediatek,mt8192-vcodec-dec           ö                      
�   s        
K   a   €                     +           k                    `    video-codec@10000             mediatek,mtk-vcodec-lat          ö                      <      ª             @  
K   a       a   ¡   a   ¢   a   £   a   ¤   a   ¥   a   ¦   a   §      (   £      4                            F        Ðsel soc-vdec soc-lat vdec top           ü      4              F        ~   7         video-codec@25000             mediatek,mtk-vcodec-core             ö     P                <      ©             X  
K   a   €   a   �   a   ‚   a   ƒ   a   „   a   …   a   †   a   ‡   a   ˆ   a   ‰   a   Š      (   £      4   !      !      !          F        Ðsel soc-vdec soc-lat vdec top           ü      4              F        ~   7            larb@1600d000             mediatek,mt8192-smi-larb             ö     Ð                
-           
>   `         £                        Ðapb smi         ~   7            Ò   h      clock-controller@1600f000             mediatek,mt8192-vdecsys_soc          ö     ð                 –            Ò          larb@1602e000             mediatek,mt8192-smi-larb             ö    à                
-           
>   `         £   !       !            Ðapb smi         ~   7            Ò   g      clock-controller@1602f000             mediatek,mt8192-vdecsys          ö    ð                 –            Ò   !      clock-controller@17000000             mediatek,mt8192-vencsys          ö                       –            Ò         larb@17010000             mediatek,mt8192-smi-larb             ö                     
-           
>   `         £                     Ðapb smi         ~   7            Ò   i      vcodec@17020000           mediatek,mt8192-vcodec-enc           ö                    X  
K   a   à   a   á   a   â   a   ã   a   ä   a   å   a   æ   a   ç   a   è   a   í   a   î        <      5               
�   s        ~   7            £            	  Ðvenc_sel            ü      3              W      clock-controller@1a000000             mediatek,mt8192-camsys           ö                       –            Ò   "      larb@1a001000             mediatek,mt8192-smi-larb             ö                     
-           
>   `         £   "      "            Ðapb smi         ~   7            Ò   l      larb@1a002000             mediatek,mt8192-smi-larb             ö                      
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>   `         £   "      "           Ðapb smi         ~   7            Ò   m      larb@1a00f000             mediatek,mt8192-smi-larb             ö     ð                
-           
>   `         £   #      #            Ðapb smi         ~   7            Ò   n      larb@1a010000             mediatek,mt8192-smi-larb             ö                     
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>   `         £   $      $            Ðapb smi         ~   7            Ò   o      larb@1a011000             mediatek,mt8192-smi-larb             ö                    
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>   `         £   %       %           Ðapb smi         ~   7            Ò   p      clock-controller@1a04f000             mediatek,mt8192-camsys_rawa          ö    ð                 –            Ò   #      clock-controller@1a06f000             mediatek,mt8192-camsys_rawb          ö    ð                 –            Ò   $      clock-controller@1a08f000             mediatek,mt8192-camsys_rawc          ö    ð                 –            Ò   %      clock-controller@1b000000             mediatek,mt8192-ipesys           ö                       –            Ò         larb@1b00f000             mediatek,mt8192-smi-larb             ö     ð                
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>   `         £                    Ðapb smi         ~   7   
         Ò   r      larb@1b10f000             mediatek,mt8192-smi-larb             ö    ð                
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>   `         £                     Ðapb smi         ~   7   
         Ò   q      clock-controller@1f000000             mediatek,mt8192-mdpsys           ö                       –            Ò         larb@1f002000             mediatek,mt8192-smi-larb             ö                      
-           
>   `         £                    Ðapb smi         ~   7            Ò   f         thermal-zones      cpu0-thermal            
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í   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            
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í   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            
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è   {      0  
í   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            
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è   |      0  
í   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            
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   trips      trip-alert          
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Ñ †         
Ý  Ð      	   Ecritical                   chosen          
üserial0:115200n8          memory@40000000          êmemory           ö    @       €         backlight-lcd0            pwm-backlight              ~     ¡         3           ã      ˜                  ÿ          ÿ        6  @         Ò   F      dmic-codec            dmic-codec          O           \   2      regulator-1v0-dpbrdg              regulator-fixed         •pp1000_dpbrdg           Édefault         ×   €        ¤ B@        ¼ B@         l                 ‘                  –   �      regulator-1v0-mipibrdg            regulator-fixed         •pp1000_mipibrdg         Édefault         ×   ‚        ¤ B@        ¼ B@         l                 ‘      �            –   �         Ò   A      regulator-1v8-dpbrdg              regulator-fixed         •pp1800_dpbrdg           Édefault         ×   ƒ         l                 ‘      ~            –   L      regulator-1v8-g           regulator-fixed         •pp1800_ldo_g             ð                 ¤ w@        ¼ w@        –   4      regulator-1v8-mipibrdg            regulator-fixed         •pp1800_mipibrdg         Édefault         ×   „         l                 ‘      €            –   L         Ò   B      regulator-3v3-dpbrdg              regulator-fixed         •pp3300_dpbrdg           Édefault         ×   …         l                 ‘                  –   4      regulator-3v3-g           regulator-fixed       	  •pp3300_g             ð                 ¤ 2Z         ¼ 2Z         –            Ò   4      regulator-3v3-z           regulator-fixed         •pp3300_ldo_z             ð                 ¤ 2Z         ¼ 2Z         –            Ò   M      regulator-3v3-mipibrdg            regulator-fixed         •pp3300_mipibrdg         Édefault         ×   †         l                 ‘                  –   4        ¡ ¡          Ò   C      regulator-3v3-u           regulator-fixed       	  •pp3300_u             ð                 ¤ 2Z         ¼ 2Z         –   4         Ò   P      regulator-3v3-wlan            regulator-fixed         •pp3300_wlan          ð                 ¤ 2Z         ¼ 2Z         Édefault         ×   ‡         l        ‘      �          regulator-5v0-a           regulator-fixed       	  •pp5000_a             ð                 ¤ LK@        ¼ LK@        –            Ò   5      regulator-var-sys             regulator-fixed       
  •ppvar_sys            ð                  Ò         reserved-memory                      +            k   audio-dma-pool            shared-dma-pool                         ±                »         Ò   9      scp@50000000              shared-dma-pool          ö    P       �           »         Ò   .      wifi@c0000000             restricted-dma-pool          ö    À                   Ò   <         audio-codec           realtek,rt1015p         Édefault         ×   ˆ        Â      “            #             Ò   ¤      sound           Ì   ‰     É  Éaud_clk_mosi_off aud_clk_mosi_on aud_dat_mosi_off aud_dat_mosi_on aud_dat_miso_off aud_dat_miso_on vow_dat_miso_off vow_dat_miso_on vow_clk_miso_off vow_clk_miso_on aud_nle_mosi_off aud_nle_mosi_on aud_dat_miso2_off aud_dat_miso2_on aud_gpio_i2s3_off aud_gpio_i2s3_on aud_gpio_i2s8_off aud_gpio_i2s8_on aud_gpio_i2s9_off aud_gpio_i2s9_on aud_dat_mosi_ch34_off aud_dat_mosi_ch34_on aud_dat_miso_ch34_off aud_dat_miso_ch34_on aud_gpio_tdm_off aud_gpio_tdm_on            ×   Š        Õ   ‹        Þ   Œ        è   �        ò   Ž        ü   �           �           ‘           ’        $   “        .   ”        9   •        D   –        O   —        Z   ˜        e   ™        p   š        {   ›        †   œ        ‘   �        œ   ž        §   Ÿ        ²            ½   ¡        È   ¢        Ó   £      &    mediatek,mt8192_mt6359_rt1015p_rt5682      speaker-codecs          Þ   ¤      headset-codec           Þ   ¥             pwmleds       	    pwm-leds       led         èkbd_backlight           ñ               ¦            ÷  ÿ            	compatible interrupt-parent #address-cells #size-cells model chassis-type ovl0 ovl-2l0 ovl-2l2 rdma0 rdma4 i2c0 i2c1 i2c2 i2c3 i2c7 mmc0 mmc1 serial0 #clock-cells clocks clock-div clock-mult clock-output-names phandle clock-frequency device_type reg enable-method cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains capacity-dmips-mhz #cooling-cells cpu cache-level cache-unified entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts opp-shared opp-hz opp-microvolt dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux output-low input-enable bias-pull-up drive-strength drive-strength-microamp bias-disable bias-pull-down output-high #power-domain-cells clock-names mediatek,infracfg domain-supply assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread #mbox-cells status resets nvmem-cells nvmem-cell-names #thermal-sensor-cells reset-names #pwm-cells pinctrl-names pinctrl-0 mediatek,pad-select spi-max-frequency wakeup-source google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count label power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap cs-gpios firmware-name memory-region mediatek,rpmsg-name interrupt-names phys mediatek,syscon-wakeup vusb33-supply vbus-supply mediatek,apmixedsys mediatek,topckgen power-domains bus-range interrupt-map-mask interrupt-map num-lanes spi-rx-bus-width spi-tx-bus-width enable-gpios reset-gpios vdd10-supply vdd18-supply vdd33-supply remote-endpoint power-supply backlight realtek,jd-src AVDD-supply DBVDD-supply LDO1-IN-supply MICVDD-supply realtek,btndet-delay VBAT-supply vcc-supply hid-descr-addr #phy-cells pinctrl-1 vmmc-supply vqmmc-supply cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset mmc-hs400-enhanced-strobe hs400-ds-delay no-sdio no-sd non-removable cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc power-domain-names operating-points-v2 mali-supply mboxes mediatek,gce-client-reg mediatek,gce-events mediatek,larb-id mediatek,smi iommus mediatek,rdma-fifo-size phy-names mediatek,larbs #iommu-cells mediatek,scp polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path pwms brightness-levels num-interpolated-steps default-brightness-level num-channels wakeup-delay-ms enable-active-high regulator-boot-on gpio vin-supply off-on-delay-us alignment no-map sdb-gpios mediatek,platform pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 pinctrl-6 pinctrl-7 pinctrl-8 pinctrl-9 pinctrl-10 pinctrl-11 pinctrl-12 pinctrl-13 pinctrl-14 pinctrl-15 pinctrl-16 pinctrl-17 pinctrl-18 pinctrl-19 pinctrl-20 pinctrl-21 pinctrl-22 pinctrl-23 pinctrl-24 pinctrl-25 sound-dai function color max-brightness 