Ðþí QÀ   8 F¸   (             F€                             %    mediatek,mt8195-demo mediatek,mt8195                                     +            7MediaTek MT8195 demo board     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/mailbox@10320000            Y/soc/mailbox@10330000            ^/soc/hdmi-tx@1c300000            d/soc/hdr-engine@1c114000             k/soc/mutex@1c016000          r/soc/mutex@1c101000          y/soc/vpp-merge@1c10c000          €/soc/vpp-merge@1c10d000          ‡/soc/vpp-merge@1c10e000          Ž/soc/vpp-merge@1c10f000          •/soc/vpp-merge@1c110000          œ/soc/dma-controller@1c104000             §/soc/dma-controller@1c105000             ²/soc/dma-controller@1c106000             ½/soc/dma-controller@1c107000             È/soc/dma-controller@1c108000             Ó/soc/dma-controller@1c109000             Þ/soc/dma-controller@1c10a000             é/soc/dma-controller@1c10b000             ô/soc/serial@11001100          cpus                         +       cpu@0            ücpu           arm,cortex-a55                      psci                           .ec3@        >  4        Q              a  €         n   @        €   €        �  €         š   @        ¬   €        ¹           Ê           Ù   	      cpu@100          ücpu           arm,cortex-a55                     psci                           .ec3@        >  4        Q              a  €         n   @        €   €        �  €         š   @        ¬   €        ¹           Ê           Ù   
      cpu@200          ücpu           arm,cortex-a55                     psci                           .ec3@        >  4        Q              a  €         n   @        €   €        �  €         š   @        ¬   €        ¹           Ê           Ù         cpu@300          ücpu           arm,cortex-a55                     psci                           .ec3@        >  4        Q              a  €         n   @        €   €        �  €         š   @        ¬   €        ¹           Ê           Ù         cpu@400          ücpu           arm,cortex-a78                     psci                          .�fÔÀ        >           Q              a           n   @        €           �           š   @        ¬           ¹           Ê           Ù         cpu@500          ücpu           arm,cortex-a78                     psci                          .�fÔÀ        >           Q              a           n   @        €           �           š   @        ¬           ¹           Ê           Ù         cpu@600          ücpu           arm,cortex-a78                     psci                          .�fÔÀ        >           Q              a           n   @        €           �           š   @        ¬           ¹           Ê           Ù         cpu@700          ücpu           arm,cortex-a78                     psci                          .�fÔÀ        >           Q              a           n   @        €           �           š   @        ¬           ¹           Ê           Ù         cpu-map    cluster0       core0           á   	      core1           á   
      core2           á         core3           á         core4           á         core5           á         core6           á         core7           á               idle-states         åpsci       cpu-retention-l           arm,idle-state          ò           	           2        +   _        ;  D        Ù         cpu-retention-b           arm,idle-state          ò           	           -        +   Œ        ;  ä        Ù         cpu-off-l             arm,idle-state          ò          	           7        +   ›        ;  H        Ù         cpu-off-b             arm,idle-state          ò          	           2        +   È        ;  è        Ù            l2-cache0             cache           L           c           p   @        ‚           ¹            X        Ù         l2-cache1             cache           L           c           p   @        ‚           ¹            X        Ù         l3-cache              cache           L           c            p   @        ‚            X        Ù            dsu-pmu           arm,dsu-pmu         f                       q   	   
                          vfail          dmic-codec            dmic-codec          }           Š   2      mt8195-sound            š         	  vdisabled          fixed-factor-clock-13m            fixed-factor-clock          ¬            ¹           À           Ê           Õclk13m          Ù   (      oscillator-26m            fixed-clock         ¬            .Œº€        Õclk26m          Ù         oscillator-32k            fixed-clock         ¬            .  €         Õclk32k        performance-controller@11bc10             mediatek,cpufreq-hw               ¼            ½0               è           Ù         opp-table-gpu             operating-points-v2                  Ù   a   opp-390000000               >í€         	‰h      opp-410000000               p€         	¡Ò      opp-431000000               °‰À         	¡Ò      opp-473000000               1h@         	º<      opp-515000000               ²FÀ         	º<      opp-556000000               !#ã          	Ò¦      opp-598000000               #¤Á€         	ë      opp-640000000               &%           	ë      opp-670000000               'ïc€         
ä      opp-700000000               )¹'          
L¸      opp-730000000               +‚ê€         
}Œ      opp-760000000               -L®          
®`      opp-790000000               /q€         
ß4      opp-820000000               0à5                opp-850000000               2©ø€         @Ü      opp-880000000               4s¼          q°         pmu-a55           arm,cortex-a55-pmu                      f                  pmu-a78           arm,cortex-a78-pmu                      f                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  f                                             
             soc                      +             simple-bus           "        )                          interrupt-controller@c000000              arm,gic-v3          4           E                        \                                             f      	               Ù      ppi-partitions     interrupt-partition-0           q   	   
              Ù         interrupt-partition-1           q                    Ù               syscon@10000000            mediatek,mt8195-topckgen syscon                               ¬           Ù         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                               ¬           z           Ù         syscon@10003000           mediatek,mt8195-pericfg syscon               0                ¬           Ù   ;      pinctrl@10005000              mediatek,mt8195-pinctrl       €       P            Ñ             Ó             Ô             â             ë             ô              °              B  ‡iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            ‘        ¡           ­              �         \        f       ë               4           Ù      eth-default-pins            Ù   7   pins-txd            ¹  M  N  O  P        À         pins-cc         ¹  U  X  W  V        À         pins-rxd            ¹  Q  R  S  T      pins-mdio           ¹  Y  Z         Ï      pins-power          ¹  [   \          Ü         eth-sleep-pins          Ù   8   pins-txd            ¹  M   N   O   P       pins-cc         ¹  U   X   W   V       pins-rxd            ¹  Q   R   S   T       pins-mdio           ¹  Y   Z          è         ö         gpio-keys-pins          Ù   ­   pins            ¹  j          Ï         i2c6-pins           Ù   P   pins            ¹                      mmc0-default-pins           Ù   >   pins-clk            ¹  z        À              f      pins-cmd-dat          $  ¹  ~  }  |  {  w  v  u  t  y         Ï        À              e      pins-rst            ¹  x        À              e         mmc0-uhs-pins           Ù   ?   pins-clk            ¹  z        À              f      pins-cmd-dat          $  ¹  ~  }  |  {  w  v  u  t  y         Ï        À              e      pins-ds         ¹          À              f      pins-rst            ¹  x        À              e         mmc1-default-pins           Ù   B   pins-clk            ¹  o        À              f      pins-cmd-dat            ¹  n  p  q  r  s         Ï        À              e      pins-insert         ¹  �                   mmc1-uhs-pins           Ù   C   pins-clk            ¹  o        À              f      pins-cmd-dat            ¹  n  p  q  r  s         Ï        À              e         uart0-pins          Ù   .   pins            ¹  b  c         uart1-pins          Ù   /   pins            ¹  f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8195-power-controller                         +                       Ù   *   power-domain@8                                  +                  power-domain@9             	        ¹                    3mfg alt         ?                        +                  power-domain@10            
                  power-domain@11                              power-domain@12                              power-domain@13                              power-domain@14                                    power-domain@15                  Ø  ¹                        	      @      A      K      à                                                                                                                          3vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           ?                        +                  power-domain@16                  8  ¹      â      $      %      &      '      (      )      D  3vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         ?                        +                  power-domain@17                    ¹      á                    3vppsys1 vppsys1-0 vppsys1-1         ?                     power-domain@22                     ¹                              $  3wepsys-0 wepsys-1 wepsys-2 wepsys-3         ?                     power-domain@23                    ¹               3vdec0-0         ?                        +                   power-domain@24                    ¹               3vdec1-0         ?                     power-domain@25                    ¹                3vdec2-0         ?                        power-domain@26                    ¹   !            3venc0-larb          ?                        +                   power-domain@27                    ¹   "            3venc1-larb          ?                        power-domain@18                     ¹      ã   #       #      #         &  3vdosys1 vdosys1-0 vdosys1-1 vdosys1-2           ?                        +                  power-domain@19                    ?                     power-domain@20                    ?                     power-domain@21                    ¹      Q        3hdmi_tx                      power-domain@28                    ¹   $       $   
        3img-0 img-1         ?                        +                  power-domain@29                              power-domain@30                    ¹         $      %           3ipe ipe-0 ipe-1         ?                        power-domain@31                  (  ¹   &       &      &      &      &           3cam-0 cam-1 cam-2 cam-3 cam-4           ?                        +                  power-domain@32                               power-domain@33            !                  power-domain@34            "                           power-domain@0                      ?                     power-domain@1                     ?                     power-domain@2                               power-domain@3                               power-domain@4                     ¹      5      7        3csi_rx_top csi_rx_top1                    power-domain@5                     ¹   '           3ether                     power-domain@6                     ¹      X      n        3adsp adsp1                       +            ?                 power-domain@7                      ¹      g      "      n      2        3audio audio1 audio2 audio3          ?                              watchdog@10007000             mediatek,mt8195-wdt          Q             p                z           Ù   -      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                À                ¬           Ù         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer             p                f      	               ¹   (      pwrap@10024000            mediatek,mt8195-pwrap syscon                @                ‡pwrap           f       ó               ¹                   	  3spi wrap            i      $        y      Ë   pmic              mediatek,mt6359          \        4           �           ¡      Þ      adc           mediatek,mt6359-auxadc          µ         audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            Çvs1         Ö 5         î !‘À                     "      buck_vgpu11         Çvgpu11          Ö €        î 7        6  ˆ           È        K                   "      buck_vmodem         Çvmodem          Ö €        î Èà        6  *           È      buck_vpu            Çvpu         Ö €        î 7        6  ˆ           È        K                   "      buck_vcore          Çvcore           Ö €        î Ö         6  ˆ           È        K                   "      buck_vs2            Çvs2         Ö 5         î j                      "      buck_vpa            Çvpa         Ö ¡         î 7±Ð          ,      buck_vproc2         Çvproc2          Ö €        î 7        6  L           È        K                   "      buck_vproc1         Çvproc1          Ö €        î 7        6  L           È        K                   "      buck_vcore_sshub            Çvcore_sshub         Ö €        î 7      buck_vgpu11_sshub           Çvgpu11_sshub            Ö €        î 7      ldo_vaud18          Çvaud18          Ö w@        î w@           ð      ldo_vsim1           Çvsim1           Ö ð         î /M`      ldo_vibr            Çvibr            Ö O€        î 2Z       ldo_vrf12           Çvrf12           Ö Èà        î Ö          "      ldo_vusb            Çvusb            Ö -ÆÀ        î -ÆÀ          À         "        Ù   <      ldo_vsram_proc2         Çvsram_proc2         Ö ¡         î ½¶        6  L           ð         "      ldo_vio18           Çvio18           Ö ð         î ýà          À         "      ldo_vcamio          Çvcamio          Ö ð         î ýà      ldo_vcn18           Çvcn18           Ö w@        î w@           ð      ldo_vfe28           Çvfe28           Ö *¹€        î *¹€           x      ldo_vcn13           Çvcn13           Ö »         î Ö       ldo_vcn33_1_bt          Çvcn33_1_bt          Ö *¹€        î 5gà      ldo_vcn33_1_wifi            Çvcn33_1_wifi            Ö *¹€        î 5gà      ldo_vaux18          Çvaux18          Ö w@        î w@           ð         "      ldo_vsram_others            Çvsram_others            Ö ¡         î ½¶        6  ˆ           ð         "      ldo_vefuse          Çvefuse          Ö ð         î „€      ldo_vxo22           Çvxo22           Ö w@        î !‘À         "      ldo_vrfck           Çvrfck           Ö ã`        î ð       ldo_vrfck_1         Çvrfck_1         Ö ëÀ        î j       ldo_vbif28          Çvbif28          Ö *¹€        î *¹€           ð      ldo_vio28           Çvio28           Ö *¹€        î 2Z          "      ldo_vemc            Çvemc            Ö ,@         î 2Z       ldo_vemc_1          Çvemc_1          Ö &%         î 2Z         Ù   @      ldo_vcn33_2_bt          Çvcn33_2_bt          Ö *¹€        î 5gà      ldo_vcn33_2_wifi            Çvcn33_2_wifi            Ö *¹€        î 5gà      ldo_va12            Çva12            Ö O€        î Ö          "      ldo_va09            Çva09            Ö 5         î O€      ldo_vrf18           Çvrf18           Ö ð         î žP      ldo_vsram_md          	  Çvsram_md            Ö ¡         î ½¶        6  *           ð         "      ldo_vufs            Çvufs            Ö ð         î ýà        Ù   A      ldo_vm18            Çvm18            Ö ð         î ýà         "      ldo_vbbck           Çvbbck           Ö Èà        î O€         "      ldo_vsram_proc1         Çvsram_proc1         Ö ¡         î ½¶        6  L           ð         "      ldo_vsim2           Çvsim2           Ö ð         î /M`      ldo_vsram_others_sshub          Çvsram_others_sshub          Ö ¡         î ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi                 p            �                ‡pmif spmimst            ¹                   E      (  3pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         i      $        y      Ë      infra-iommu@10315000              mediatek,mt8195-iommu-infra             1P       P       P  f                                                                         c           Ù   K      mailbox@10320000              mediatek,mt8195-gce             2        @         f       â               p           ¹              Ù   „      mailbox@10330000              mediatek,mt8195-gce             3        @         f       ä               p           ¹              Ù   b      scp@10500000              mediatek,mt8195-scp       0      P             r             p        €         ‡sram cfg l1tcm          f      Î             	  vdisabled            Ù   c      clock-controller@10720000             mediatek,mt8195-scp_adsp                r                 ¬           Ù   )      dsp@10803000              mediatek,mt8195-dsp              €0            „               	  ‡cfg sram          ,  ¹      X         n      Š   )          #      K  3adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          |   *           Šrx tx           •   +   ,      	  vdisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           p                �`                f      ¾               Ù   +      mailbox@10817000              mediatek,mt8195-adsp-mbox           p                �p                f      ¿               Ù   ,      mt8195-afe-pcm@10890000           mediatek,mt8195-audio               ‰                 œ           |   *           f      6               ®   -         	  µaudiosys          ”  ¹                     Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d      2   )          ó  3clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  vdisabled            Ù         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f       �               ¹               	  3baud bus            vokay            Ádefault         Ï   .      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f       Ž               ¹               	  3baud bus            vokay            Ádefault         Ï   /      serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f       �               ¹               	  3baud bus          	  vdisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f      Ó               ¹               	  3baud bus          	  vdisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f      Ô               ¹               	  3baud bus          	  vdisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f      Õ               ¹               	  3baud bus          	  vdisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                 ¹              3main            µ         	  vdisabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                0                ¬           Ù   '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  f       ¿               ¹      ™                    3parent-clk sel-clk spi-clk        	  vdisabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap              °                f       ©               ¹              ®               Ù   0   1      $  ålvts-calib-data-1 lvts-calib-data-2         ö           Ù   ¬      svs@1100bc00              mediatek,mt8195-svs              ¼                f       Ç               ¹              3main            Ù   2   0      (  åsvs-calibration-data t-calibration-data         ®              µsvs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                à                f       Ë               |   *                      ¹      *      0        3main mm       	  vdisabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                ð                f                                ¹      +      N        3main mm       	  vdisabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 f       À               ¹      ™            3        3parent-clk sel-clk spi-clk        	  vdisabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 f       Á               ¹      ™            4        3parent-clk sel-clk spi-clk        	  vdisabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                0                f       Â               ¹      ™            5        3parent-clk sel-clk spi-clk        	  vdisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                €                f       Ã               ¹      ™            <        3parent-clk sel-clk spi-clk        	  vdisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                �                f       Ä               ¹      ™            =        3parent-clk sel-clk spi-clk        	  vdisabled          spi@1101d000              mediatek,mt8195-spi-slave               Ð                f       Å               ¹      R        3spi         i              y      ˜      	  vdisabled          spi@1101e000              mediatek,mt8195-spi-slave               à                f       Æ               ¹      S        3spi         i              y      ˜      	  vdisabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                      @         f      Ì               macirq        .  3axi apb mac_main ptp_ref rmii_internal mac_cg         0  ¹   '       '         R      S      T   '           i      R      S      T        y      Â      Ã      Ä        |   *           '           8   3        H   4        [   5        n           y           „            vokay          	  ‘rgmii-id            š   6        ¥      ]            µ      ' 8€        Ádefault sleep           Ï   7        Ê   8         Ô   mdio              snps,dwmac-mdio                      +       ethernet-phy@1                     Ù   6         stmmac-axi-config           å           õ                                            Ù   3      rx-queues-config                        %        Ù   4   queue0           6        I          queue1           6        I          queue2           6        I          queue3           6        I             tx-queues-config            a            w        Ù   5   queue0          ‰            6        •          queue1          ‰            6        •         queue2          ‰            6        •         queue3          ‰            6        •               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                       -ÿ     >              	  ‡mac ippc            "                     ?                      +           f       €               ¹      /      í      B        3sys_ck ref_ck mcu_ck            £   9      :            ¨        ¶   ;      g        vokay            Í   <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 ‡mac         f       �               i      ,      -        y      –      –      $  ¹      /      í               B      $  3sys_ck ref_ck mcu_ck dma_ck xhci_ck         vokay            Û   =         mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              #             õ                 f       ƒ               ¹                          3source hclk source_cg           vokay            Ádefault state_uhs           Ï   >        Ê   ?        ç           ñëÂ          ÿ                            /         @         H        N L        ]   @        i   A         v      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              $             Ç                 f       ‡               ¹                  $        3source hclk source_cg           i              y      ¿        vokay            Ádefault state_uhs           Ï   B        Ê   C        „      �           ç           ñëÂ          �         ž         «        ]   D        i   E      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              %             æ                 f       ˆ               ¹                   I        3source hclk source_cg           i               y      ¿      	  vdisabled          ufshci@11270000           mediatek,mt8195-ufshci              '        #         f       ‰               £   F      @  ¹      ?      @      A      6      7      8      Z      ]      X  3ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  ¹                                                                         Ç      	  vdisabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                '€                f       ª               ¹              ®              Ù   0   1      $  ålvts-calib-data-1 lvts-calib-data-2         ö           Ù   £      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci               )             )>              	  ‡mac ippc            f                     £   G      H           i      .      /        y      –      –      $  ¹   '         ï            '         $  3sys_ck ref_ck mcu_ck dma_ck xhci_ck         ¶   ;      h         ¨        vokay            Í   <      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               *       -ÿ    *>              	  ‡mac ippc            "            *        ?                      +           f                     i      0        y      –        ¹   '         ñ   '           3sys_ck ref_ck mcu_ck            £   I            ¨        ¶   ;      i        vokay            Í   <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 ‡mac         f                     i      1        y      –        ¹   '           3sys_ck          vokay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               +       -ÿ    +>              	  ‡mac ippc            "            +        ?                      +           f                     i      2        y      –        ¹   '         ó   '   	        3sys_ck ref_ck mcu_ck            £   J            ¨        ¶   ;      j        vokay            Í   <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 ‡mac         f                     i      3        y      –        ¹   '   	        3sys_ck          vokay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            üpci                      +               /        @       	  ‡pcie-mac            f                     à       ÿ      8  "�                           ‚                       à          ê       K              ô          0  ¹      V      #      &      +      K   '         /  3pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          i      G        y              £   L      	  	pcie-phy            |   *            4           	                     `  	                   M                      M                     M                     M         	  vdisabled       interrupt-controller             \                     4           Ù   M         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            üpci                      +               /€       @       	  ‡pcie-mac            f                     à       ÿ      8  "�       $       $           ‚       $       $       à          ê       K              ô          (  ¹      W         X         Q   '         /  3pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          i      H        y              £   H         	  	pcie-phy            |   *           4           	                     `  	                   N                      N                     N                     N         	  vdisabled       interrupt-controller             \                     4           Ù   N         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor             2À                f      9               ¹      o   '      '           3spi sf axi                       +          	  vdisabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                Á                              +      usb3-tx-imp@184,1             „           	.               Ù   X      usb3-rx-imp@184,2             „           	.              Ù   W      usb3-intr@185             …           	.              Ù   V      usb3-tx-imp@186,1             †           	.               Ù   U      usb3-rx-imp@186,2             †           	.              Ù   T      usb3-intr@187             ‡           	.              Ù   S      usb2-intr-p0@188,1            ˆ           	.             usb2-intr-p1@188,2            ˆ           	.            usb2-intr-p2@189,1            ‰           	.            usb2-intr-p3@189,2            ‰           	.            pciephy-rx-ln1@190,1              �           	.               Ù   _      pciephy-tx-ln1-nmos@190,2             �           	.              Ù   ^      pciephy-tx-ln1-pmos@191,1             ‘           	.               Ù   ]      pciephy-rx-ln0@191,2              ‘           	.              Ù   \      pciephy-tx-ln0-nmos@192,1             ’           	.               Ù   [      pciephy-tx-ln0-pmos@192,2             ’           	.              Ù   Z      pciephy-glb-intr@193              “           	.               Ù   Y      dp-data@1ac           ¬           Ù   ¢      lvts1-calib@1bc           ¼           Ù   0      lvts2-calib@1d0           Ð   8        Ù   1      svs-calib@580             €   d        Ù   2      socinfo-data1@7a0                          t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "        Ä             vokay       usb-phy@0                          ¹      ò        3ref         	3           Ù   I         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "        Å             vokay       usb-phy@0                          ¹      ô        3ref         	3           Ù   J         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             È                 ¹           Õmipi_tx0_pll            ¬            	3          	  vdisabled            Ù   ‘      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             É                 ¹           Õmipi_tx1_pll            ¬            	3          	  vdisabled            Ù   ’      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        f       š               À           ¹   O          ;      	  3main dma                         +          	  vdisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð            "        €        f       ›               À           ¹   O         ;      	  3main dma                         +            vokay            . €        Ï   P        Ádefault    pmic@34           mediatek,mt6360            4         \        4           ¡      e           IRQB       charger           mediatek,mt6360-chg         	> Ý@    usb-otg-vbus-regulator          Çusb-otg-vbus            Ö C…(        î Xáè        Ù   =         regulator             mediatek,mt6360-regulator           	W   Q   buck1           Çmt6360,buck1            Ö “à        î Ö         K                   "      buck2           Çmt6360,buck2            Ö “à        î Ö         K                   "        Ù   Q      ldo1            Çmt6360,ldo1         Ö O€        î 6î€        K             ldo2            Çmt6360,ldo2         Ö O€        î 6î€        K             ldo3            Çmt6360,ldo3         Ö O€        î 6î€        K               Ù   E      ldo5            Çmt6360,ldo5         Ö )2à        î 6î€        K               Ù   D      ldo6            Çmt6360,ldo6         Ö ¡         î           K             ldo7            Çmt6360,ldo7         Ö ¡         î           K                "               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        f       œ               À           ¹   O         ;      	  3main dma                         +          	  vdisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s              Ð0                ¬           Ù   O      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy                Õð                 ¹      P                          3pll_ref 26m pll1 pll2           Õhdmi_txpll          ¬            	3            	g   
        	v         	  vdisabled            Ù   ¡      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             " €       €        f       �               À           ¹   R          ;      	  3main dma                         +          	  vdisabled          i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à            "        €        f       “               À           ¹   R         ;      	  3main dma                         +          	  vdisabled          i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             "€       €        f       –               À           ¹   R         ;      	  3main dma                         +          	  vdisabled          i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à0            "€       €        f       ˜               À           ¹   R         ;      	  3main dma                         +          	  vdisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à@            "        €        f       ™               À           ¹   R         ;      	  3main dma                         +          	  vdisabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w              àP                ¬           Ù   R      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "        ã             |   *           vokay       usb-phy@0                          ¹      ð           3ref da_ref          	3           Ù   G      usb-phy@700                       ¹            ð        3ref da_ref          Ù   S   T   U        åintr rx_imp tx_imp          	3           Ù   H         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "        ä             vokay       usb-phy@0                          ¹      î           3ref da_ref          	3           Ù   9      usb-phy@700                       ¹            î        3ref da_ref          Ù   V   W   X        åintr rx_imp tx_imp          	3           Ù   :         phy@11e80000              mediatek,mt8195-pcie-phy                è                 ‡sif         Ù   Y   Z   [   \   ]   ^   _      G  åglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          |   *           	3          	  vdisabled            Ù   L      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy               ú        À         ¹            
  3unipro mp           	3          	  vdisabled            Ù   F      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                        @         ¹   `          0  f      �             Œ             ‹               job mmu gpu         	ˆ   a      (  |   *   
   *      *      *      *           	œcore0 core1 core2 core3 core4         	  vdisabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg              ûð                ¬           Ù   `      syscon@14000000           mediatek,mt8195-vppsys0 syscon                                ¬           	¯   b                   Ù         dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                	¯   b                  	Ç              	Û   c        |   *           	è   d   €        ¹            <  •   b         b         b         b         b              	ï         display@14002000              mediatek,mt8195-mdp3-fg                               	¯   b                   ¹             display@14003000              mediatek,mt8195-mdp3-stitch              0                	¯   b      0            ¹            display@14004000              mediatek,mt8195-mdp3-hdr                 @                	¯   b      @            ¹      "      display@14005000              mediatek,mt8195-mdp3-aal                 P                f      F               	¯   b      P            ¹      
        |   *         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                	¯   b      `            	Ç    %        ¹            display@14007000              mediatek,mt8195-mdp3-tdshp               p                	¯   b      p            ¹      #      display@14008000              mediatek,mt8195-mdp3-color               €                f      I               	¯   b      €            ¹      $        |   *         display@14009000              mediatek,mt8195-mdp3-ovl                 �                f      J               	¯   b      �            ¹      %        |   *           	è   d   ‚      display@1400a000              mediatek,mt8195-mdp3-padding                                  	¯   b                   ¹              |   *         display@1400b000              mediatek,mt8195-mdp3-tcc                 °                	¯   b      °            ¹            dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              À                	¯   b      À            	Ç    +        ¹              	è   d   ƒ        |   *           	ï         mutex@1400f000            mediatek,mt8195-vpp-mutex                ð                f      P               	¯   b      ð            ¹              |   *         smi@14010000              mediatek,mt8195-smi-sub-common                               ¹                          3apb smi gals0           	ú   e        |   *           Ù   f      smi@14011000              mediatek,mt8195-smi-sub-common                              ¹                          3apb smi gals0           	ú   e        |   *           Ù   ƒ      smi@14012000              mediatek,mt8195-smi-common-vpp                                ¹                                3apb smi gals0 gals1         |   *           Ù   e      larb@14013000             mediatek,mt8195-smi-larb                0                
           	ú   f        ¹                    3apb smi         |   *           Ù   i      iommu@14018000            mediatek,mt8195-iommu-vpp               €              8  
   g   h   i   j   k   l   m   n   o   p   q   r   s   t        f      R               ¹              3bclk            c           |   *           Ù   d      clock-controller@14e00000             mediatek,mt8195-wpesys              à                 ¬           Ù         clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0             à                 ¬         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1             à0                ¬         larb@14e04000             mediatek,mt8195-smi-larb                à@                
           	ú   u        ¹                    3apb smi         |   *           Ù   –      larb@14e05000             mediatek,mt8195-smi-larb                àP                
           	ú   e        ¹                          3apb smi gals            |   *           Ù   k      syscon@14f00000           mediatek,mt8195-vppsys1 syscon              ð                 ¬           	¯   b   	               Ù         mutex@14f01000            mediatek,mt8195-vpp-mutex               ð                f      {               	¯   b   	              ¹      '        |   *         larb@14f02000             mediatek,mt8195-smi-larb                ð                 
           	ú   u        ¹                          3apb smi gals            |   *           Ù   •      larb@14f03000             mediatek,mt8195-smi-larb                ð0                
           	ú   f        ¹                          3apb smi gals            |   *           Ù   j      display@14f06000              mediatek,mt8195-mdp3-split              ð`                	¯   b   	  `            ¹            +      ,        |   *         display@14f07000              mediatek,mt8195-mdp3-tcc                ðp                	¯   b   	  p            ¹            dma-controller@14f08000           mediatek,mt8195-mdp3-rdma               ð€                	¯   b   	  €            	Ç  „  ¨        ¹              	è   v            |   *           	ï         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma               ð�                	¯   b   	  �            	Ç  …  ©        ¹      
        	è   v   ¤        |   *           	ï         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma               ð                 	¯   b   	               	Ç  †  ª        ¹              	è   d   À        |   *           	ï         display@14f0b000              mediatek,mt8195-mdp3-fg             ð°                	¯   b   	  °            ¹      	      display@14f0c000              mediatek,mt8195-mdp3-fg             ðÀ                	¯   b   	  À            ¹            display@14f0d000              mediatek,mt8195-mdp3-fg             ðÐ                	¯   b   	  Ð            ¹            display@14f0e000              mediatek,mt8195-mdp3-hdr                ðà                	¯   b   	  à            ¹            display@14f0f000              mediatek,mt8195-mdp3-hdr                ðð                	¯   b   	  ð            ¹            display@14f10000              mediatek,mt8195-mdp3-hdr                ñ                 	¯   b   
               ¹             display@14f11000              mediatek,mt8195-mdp3-aal                ñ                f      i               	¯   b   
              ¹              |   *         display@14f12000              mediatek,mt8195-mdp3-aal                ñ                 f      j               	¯   b   
               ¹              |   *         display@14f13000              mediatek,mt8195-mdp3-aal                ñ0                f      k               	¯   b   
  0            ¹      !        |   *         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ@                	¯   b   
  @            	Ç  �  ¯        ¹            display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñP                	¯   b   
  P            	Ç  ‘  °        ¹      $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ`                	¯   b   
  `            	Ç  ’  ±        ¹      %      display@14f17000              mediatek,mt8195-mdp3-tdshp              ñp                	¯   b   
  p            ¹            display@14f18000              mediatek,mt8195-mdp3-tdshp              ñ€                	¯   b   
  €            ¹      (      display@14f19000              mediatek,mt8195-mdp3-tdshp              ñ�                	¯   b   
  �            ¹      )      display@14f1a000              mediatek,mt8195-mdp3-merge              ñ                 	¯   b   
               ¹              |   *         display@14f1b000              mediatek,mt8195-mdp3-merge              ñ°                	¯   b   
  °            ¹              |   *         display@14f1c000              mediatek,mt8195-mdp3-color              ñÀ                f      t               	¯   b   
  À            ¹              |   *         display@14f1d000              mediatek,mt8195-mdp3-color              ñÐ                	¯   b   
  Ð            f      u               ¹              |   *         display@14f1e000              mediatek,mt8195-mdp3-color              ñà                f      v               	¯   b   
  à            ¹              |   *         display@14f1f000              mediatek,mt8195-mdp3-ovl                ñð                f      w               	¯   b   
  ð            ¹               |   *           	è   v   ¢      display@14f20000              mediatek,mt8195-mdp3-padding                ò                 	¯   b                  ¹              |   *         display@14f21000              mediatek,mt8195-mdp3-padding                ò                	¯   b                 ¹              |   *         display@14f22000              mediatek,mt8195-mdp3-padding                ò                 	¯   b                  ¹              |   *         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò0                	¯   b     0            	Ç  Ÿ  «        ¹              	è   v   £        |   *           	ï         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò@                	¯   b     @            	Ç     ¬        ¹              	è   v   ¦        |   *           	ï         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             òP                	¯   b     P            	Ç  ¡  ­        ¹              	è   d   Â        |   *           	ï         clock-controller@15000000             mediatek,mt8195-imgsys                                ¬           Ù   $      larb@15001000             mediatek,mt8195-smi-larb                                 
   	        	ú   w        ¹   $       $       $   
        3apb smi gals            |   *           Ù   —      smi@15002000              mediatek,mt8195-smi-sub-common                                ¹   $      $                 3apb smi gals0           	ú   e        |   *           Ù   z      smi@15003000              mediatek,mt8195-smi-sub-common               0                ¹   $       $       $   
        3apb smi gals0           	ú   u        |   *           Ù   w      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                              ¬           Ù   x      larb@15120000             mediatek,mt8195-smi-larb                                 
   
        	ú   w        ¹   $      x            3apb smi         |   *           Ù   ˜      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                               ¬         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe             "                 ¬           Ù   y      larb@15230000             mediatek,mt8195-smi-larb                #                 
           	ú   w        ¹   $      y            3apb smi         |   *           Ù   ™      clock-controller@15330000             mediatek,mt8195-ipesys              3                 ¬           Ù   %      larb@15340000             mediatek,mt8195-smi-larb                4                 
           	ú   z        ¹   %      %           3apb smi         |   *           Ù   l      clock-controller@16000000             mediatek,mt8195-camsys                                ¬           Ù   &      larb@16001000             mediatek,mt8195-smi-larb                                 
           	ú   {        ¹   &       &       &           3apb smi gals            |   *           Ù   š      larb@16002000             mediatek,mt8195-smi-larb                                  
           	ú   |        ¹   &      &           3apb smi         |   *           Ù   m      smi@16004000              mediatek,mt8195-smi-sub-common               @                ¹   &       &       &           3apb smi gals0           	ú   u        |   *           Ù   {      smi@16005000              mediatek,mt8195-smi-sub-common               P                ¹   &      &                 3apb smi gals0           	ú   e        |   *           Ù   |      larb@16012000             mediatek,mt8195-smi-larb                                 
           	ú   |        ¹   }       }            3apb smi         |   *            Ù   n      larb@16013000             mediatek,mt8195-smi-larb                0                
           	ú   {        ¹   ~       ~            3apb smi         |   *            Ù   ›      larb@16014000             mediatek,mt8195-smi-larb                @                
           	ú   |        ¹                      3apb smi         |   *   !        Ù   t      larb@16015000             mediatek,mt8195-smi-larb                P                
           	ú   {        ¹   €       €            3apb smi         |   *   !        Ù          clock-controller@1604f000             mediatek,mt8195-camsys_rawa             ð                ¬           Ù   }      clock-controller@1606f000             mediatek,mt8195-camsys_yuva             ð                ¬           Ù   ~      clock-controller@1608f000             mediatek,mt8195-camsys_rawb             ð                ¬           Ù         clock-controller@160af000             mediatek,mt8195-camsys_yuvb             
ð                ¬           Ù   €      clock-controller@16140000             mediatek,mt8195-camsys_mraw                              ¬           Ù   �      larb@16141000             mediatek,mt8195-smi-larb                                
           	ú   {        ¹   &       �       &           3apb smi gals            |   *   "        Ù   Ÿ      larb@16142000             mediatek,mt8195-smi-larb                                 
           	ú   |        ¹   �       �            3apb smi         |   *   "        Ù   s      clock-controller@17200000             mediatek,mt8195-ccusys                                ¬           Ù   ‚      larb@17201000             mediatek,mt8195-smi-larb                                 
           	ú   |        ¹   ‚       ‚            3apb smi         |   *           Ù   o      video-codec@18000000              mediatek,mt8195-vcodec-dec          	Û   c        	è   v                        +                               @                "                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                	è   d  à   d  á         ¹      A                  �        3sel vdec lat top            i      A        y      �        |   *         video-codec@10000             mediatek,mtk-vcodec-lat                               f      Ä             0  	è   v      v     v     v     v     v           ¹      A                  �        3sel vdec lat top            i      A        y      �        |   *         video-codec@25000             mediatek,mtk-vcodec-core                 P                f      Ã             P  	è   v      v  ¡   v  ¢   v  £   v  ¤   v  ¥   v  ¦   v  §   v  ¨   v  ©         ¹      A                  �        3sel vdec lat top            i      A        y      �        |   *            larb@1800d000             mediatek,mt8195-smi-larb                 Ð                
           	ú   u        ¹                      3apb smi         |   *           Ù   ž      larb@1800e000             mediatek,mt8195-smi-larb                 à                
           	ú   ƒ        ¹                     3apb smi         |   *           Ù   r      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc              ð                ¬           Ù         larb@1802e000             mediatek,mt8195-smi-larb                à                
           	ú   u        ¹                      3apb smi         |   *           Ù   �      clock-controller@1802f000             mediatek,mt8195-vdecsys             ð                ¬           Ù         larb@1803e000             mediatek,mt8195-smi-larb                à                
           	ú   ƒ        ¹                      3apb smi         |   *           Ù   q      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1               ð                ¬           Ù          clock-controller@190f3000             mediatek,mt8195-apusys_pll              0                ¬         clock-controller@1a000000             mediatek,mt8195-vencsys                               ¬           Ù   !      larb@1a010000             mediatek,mt8195-smi-larb                                 
           	ú   u        ¹   !      !           3apb smi         |   *           Ù   œ      video-codec@1a020000              mediatek,mt8195-vcodec-enc                             H  	è   v  `   v  a   v  b   v  c   v  d   v  v   v  w   v  x   v  y        f      U               	Û   c        ¹   !         	  3venc_sel            i      @        y      �        |   *                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec          |   *         0  	è   v  m   v  n   v  r   v  s   v  t   v  u                     +         0  "                                            jpgdec@0,0            mediatek,mt8195-jpgdec-hw                                0  	è   v  m   v  n   v  r   v  s   v  t   v  u        f      W               ¹   !           3jpgdec          |   *         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw                               0  	è   v  m   v  n   v  r   v  s   v  t   v  u        f      X               ¹   !           3jpgdec          |   *         jpgdec@1,0            mediatek,mt8195-jpgdec-hw                               0  	è   d  �   d  Ž   d  ’   d  “   d  ”   d  •        f      \               ¹   "           3jpgdec          |   *            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                 ¬           Ù   "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                 •   „               ¬           	¯   „                  Ù         jpeg-encoder@1a030000             mediatek,mt8195-jpgenc          |   *            	è   d  ‡   d  ˆ   d  ‰   d  Œ                     +         0  "                                            jpgenc@0,0            mediatek,mt8195-jpgenc-hw                                   	è   v  g   v  h   v  i   v  l        f      V               ¹   !           3jpgenc          |   *         jpgenc@1,0            mediatek,mt8195-jpgenc-hw                                  	è   d  ‡   d  ˆ   d  ‰   d  Œ        f      [               ¹   "           3jpgenc          |   *            larb@1b010000             mediatek,mt8195-smi-larb                                 
           	ú   e        ¹   "      "                  3apb smi gals            |   *           Ù   p      ovl@1c000000              mediatek,mt8195-disp-ovl                                  f      |               |   *           ¹               	è   v           	¯   „             ports                        +       port@0                 endpoint             port@1                endpoint            
'   …        Ù   †               rdma@1c002000             mediatek,mt8195-disp-rdma                                 f      ~               |   *           ¹              	è   v            	¯   „             ports                        +       port@0                 endpoint            
'   †        Ù   …         port@1                endpoint            
'   ‡        Ù   ˆ               color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                0                f                     |   *           ¹              	¯   „     0       ports                        +       port@0                 endpoint            
'   ˆ        Ù   ‡         port@1                endpoint            
'   ‰        Ù   Š               ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                @                f      €               |   *           ¹              	¯   „     @       ports                        +       port@0                 endpoint            
'   Š        Ù   ‰         port@1                endpoint            
'   ‹        Ù   Œ               aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                P                f      �               |   *           ¹              	¯   „     P       ports                        +       port@0                 endpoint            
'   Œ        Ù   ‹         port@1                endpoint            
'   �        Ù   Ž               gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                `                f      ‚               |   *           ¹              	¯   „     `       ports                        +       port@0                 endpoint            
'   Ž        Ù   �         port@1                endpoint            
'   �        Ù   �               dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither              p                f      ƒ               |   *           ¹      	        	¯   „     p       ports                        +       port@0                 endpoint            
'   �        Ù   �         port@1                endpoint                   dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi              €                f      „               |   *           ¹            *   ‘        3engine digital hs           £   ‘        	dphy          	  vdisabled          dsc@1c009000              mediatek,mt8195-disp-dsc                 �                f      …               |   *           ¹              	¯   „     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              f      Ž               |   *           ¹            +   ’        3engine digital hs           £   ’        	dphy          	  vdisabled          merge@1c014000            mediatek,mt8195-disp-merge              @                f      �               |   *           ¹              	¯   „     @          dp-intf@1c015000              mediatek,mt8195-dp-intf             P                f      ‘               |   *           ¹      ,                    3pixel engine pll          	  vdisabled          mutex@1c016000            mediatek,mt8195-disp-mutex              `                f      ’               |   *           ¹              	¯   „     `            	Ç  U      larb@1c018000             mediatek,mt8195-smi-larb                €                
            	ú   u        ¹      (      (              3apb smi gals            |   *           Ù   “      larb@1c019000             mediatek,mt8195-smi-larb                �                
           	ú   e        ¹      (                     3apb smi gals            |   *           Ù   g      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                               •   „              	¯   „                  ¬           z           Ù   #      smi@1c01b000              mediatek,mt8195-smi-common-vdo              °                 ¹      %      &      )      $        3apb smi gals0 gals1         |   *           Ù   u      iommu@1c01f000            mediatek,mt8195-iommu-vdo               ð              8  
   “   ”   •   –   —   ˜   ™   š   ›   œ   �   ž   Ÿ            f      �               c           ¹      '        3bclk            |   *           Ù   v      mutex@1c101000            mediatek,mt8195-disp-mutex                              f      î               |   *           ¹   #           	¯   „                 	Ç  À      larb@1c102000             mediatek,mt8195-smi-larb                                 
           	ú   u        ¹   #       #       #           3apb smi gals            |   *           Ù   ”      larb@1c103000             mediatek,mt8195-smi-larb                0                
           	ú   e        ¹   #      #                  3apb smi gals            |   *           Ù   h      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma               @                f      ï               ¹   #           |   *           	è   v   @        	¯   „     @            	ï         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma               P                f      ð               ¹   #           |   *           	è   d   `        	¯   „     P            	ï         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma               `                f      ñ               ¹   #           |   *           	è   v   A        	¯   „     `            	ï         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma               p                f      ò               ¹   #           |   *           	è   d   a        	¯   „     p            	ï         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma               €                f      ó               ¹   #           |   *           	è   v   B        	¯   „     €            	ï         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma               �                f      ô               ¹   #           |   *           	è   d   b        	¯   „     �            	ï         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma                                f      õ               ¹   #           |   *           	è   v   C        	¯   „                  	ï         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma               °                f      ö               ¹   #           |   *           	è   d   c        	¯   „     °            	ï         vpp-merge@1c10c000            mediatek,mt8195-disp-merge              À                f      ÷               ¹   #   	   #           3merge merge_async           |   *           	¯   „     À             
7        ®   #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge              Ð                f      ø               ¹   #   
   #           3merge merge_async           |   *           	¯   „     Ð             
7        ®   #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge              à                f      ù               ¹   #      #           3merge merge_async           |   *           	¯   „     à             
7        ®   #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge              ð                f      ú               ¹   #      #           3merge merge_async           |   *           	¯   „     ð             
7        ®   #         vpp-merge@1c110000            mediatek,mt8195-disp-merge                               f      û               ¹   #      #           3merge merge_async           |   *           	¯   „                   
K        ®   #         dpi@1c112000              mediatek,mt8195-dpi                              ¹   #   -   #      #   2        3pixel engine pll            f                      |   *           ®   #         	  vdisabled       ports                        +       port@0                 endpoint             port@1                endpoint                   dp-intf@1c113000              mediatek,mt8195-dp-intf             0                f                     |   *           ¹   #   /   #                 3pixel engine pll          	  vdisabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p      @            P            p            �                         °            À              4  ‡mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  	¯   „     @       „     P       „     p       „     �       „             „     °       „     À          h  ¹   #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *            ƒ  3mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          |   *           	è   d   d   d   e        f                   (  ®   #   3   #   4   #   5   #   6   #   7      E  µvdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx         �               0                  ¹      Q      L      M      ,        3bus hdcp hdcp24m hdmi-split         i      L        y      “        f      ¥               |   *           £   ¡        	hdmi          	  vdisabled       i2c           mediatek,mt8195-hdmi-ddc            ¹         ports                        +       port@0                 endpoint             port@1                endpoint                   edp-tx@1c500000           mediatek,mt8195-edp-tx              P        €         Ù   ¢        ådp_calibration_data         |   *           f      ¤               
b  ¤      	  vdisabled          dp-tx@1c600000            mediatek,mt8195-dp-tx               `        €         Ù   ¢        ådp_calibration_data         |   *           f      Ê               
b  ¤      	  vdisabled             thermal-zones      cpu0-thermal            
s  è        
�   ú        
—   £      trips      trip-alert          
§ L        
³  Ð        passive         Ù   ¤      trip-crit           
§ †         
³  Ð      	  critical             cooling-maps       map0            
¾   ¤      0  
Ã   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            
s  è        
�   ú        
—   £      trips      trip-alert          
§ L        
³  Ð        passive         Ù   ¥      trip-crit           
§ †         
³  Ð      	  critical             cooling-maps       map0            
¾   ¥      0  
Ã   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            
s  è        
�   ú        
—   £      trips      trip-alert          
§ L        
³  Ð        passive         Ù   ¦      trip-crit           
§ †         
³  Ð      	  critical             cooling-maps       map0            
¾   ¦      0  
Ã   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            
s  è        
�   ú        
—   £      trips      trip-alert          
§ L        
³  Ð        passive         Ù   §      trip-crit           
§ †         
³  Ð      	  critical             cooling-maps       map0            
¾   §      0  
Ã   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            
s  è        
�   ú        
—   £       trips      trip-alert          
§ L        
³  Ð        passive         Ù   ¨      trip-crit           
§ †         
³  Ð      	  critical             cooling-maps       map0            
¾   ¨      0  
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s  è        
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—   £      trips      trip-alert          
§ L        
³  Ð        passive         Ù   ©      trip-crit           
§ †         
³  Ð      	  critical             cooling-maps       map0            
¾   ©      0  
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s  è        
�   ú        
—   £      trips      trip-alert          
§ L        
³  Ð        passive         Ù   ª      trip-crit           
§ †         
³  Ð      	  critical             cooling-maps       map0            
¾   ª      0  
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s  è        
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³  Ð        passive         Ù   «      trip-crit           
§ †         
³  Ð      	  critical             cooling-maps       map0            
¾   «      0  
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s  è        
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§ L        
³  Ð        passive       trip-crit           
§ †         
³  Ð      	  critical                vpu1-thermal            
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³  Ð      	  critical                gpu-thermal         
s  è        
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—   ¬   
   trips      trip-alert          
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³  Ð        passive       trip-crit           
§ †         
³  Ð      	  critical                gpu1-thermal            
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³  Ð        passive       trip-crit           
§ †         
³  Ð      	  critical                vdec-thermal            
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—   ¬      trips      trip-alert          
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§ †         
³  Ð      	  critical                img-thermal         
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§ †         
³  Ð      	  critical                infra-thermal           
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—   ¬      trips      trip-alert          
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³  Ð        passive       trip-crit           
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³  Ð      	  critical                cam0-thermal            
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³  Ð        passive       trip-crit           
§ †         
³  Ð      	  critical                cam1-thermal            
s  è        
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—   ¬      trips      trip-alert          
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³  Ð        passive       trip-crit           
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³  Ð      	  critical                   chosen          
Òserial0:921600n8          firmware       optee             linaro,optee-tz         smc          gpio-keys         
    gpio-keys           Ádefault         Ï   ­   key-0           ‡      j         
  
Þvolume_up           
ä   s         ¨        
ï            memory@40000000          ümemory              @                reserved-memory                      +            "   optee@43200000                       C        À        memory@50000000           shared-dma-pool             P       �                 memory@53000000           shared-dma-pool             S       @        memory@54600000                      T`                memory@60000000           shared-dma-pool             `                        memory@62000000           shared-dma-pool             b       @              	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux drive-strength input-enable output-high input-disable bias-disable bias-pull-up bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us pinctrl-1 mediatek,mac-wol snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup vusb33-supply vbus-supply bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 freq-table-hz mediatek,ufs-disable-mcq bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply mediatek,ibias mediatek,ibias_up operating-points-v2 power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path label linux,code debounce-interval no-map 