Ðþí .D   8 !Ü   (            h !¤                             4    grinn,genio-510-sbc mediatek,mt8370 mediatek,mt8188                                  +         	   7embedded             DGrinn GenioSBC-510     aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/dpi@1c112000            a/soc/dsc@1c009000            f/soc/ethdr@1c114000          m/soc/mailbox@10320000            r/soc/mailbox@10330000            w/soc/merge0@1c014000             ~/soc/merge@1c10c000          …/soc/merge@1c10d000          Œ/soc/merge@1c10e000          “/soc/merge@1c10f000          š/soc/merge@1c110000          ¡/soc/mutex@1c016000          ¨/soc/mutex@1c101000          ¯/soc/padding@1c11d000            ¸/soc/padding@1c11e000            Á/soc/padding@1c11f000            Ê/soc/padding@1c120000            Ó/soc/padding@1c121000            Ü/soc/padding@1c122000            å/soc/padding@1c123000            î/soc/padding@1c124000            ÷/soc/rdma@1c104000          /soc/rdma@1c105000          /soc/rdma@1c106000          /soc/rdma@1c107000          #/soc/rdma@1c108000          ./soc/rdma@1c109000          9/soc/rdma@1c10a000          D/soc/rdma@1c10b000          O/soc/i2c@11e00000           T/soc/mmc@11230000           Y/soc/ethernet@11021000          c/soc/i2c@11280000           h/soc/i2c@11281000           m/soc/i2c@11282000           r/soc/i2c@11ec0000           w/soc/i2c@11ec1000           |/soc/serial@11001100          cpus                         +       cpu@0           „cpu           arm,cortex-a55          �            ”psci            ¢w5”         ²          Å              Õ  €         â   @        ô   €          €            @            €        -           >               R           a   	      cpu@100         „cpu           arm,cortex-a55          �           ”psci            ¢w5”         ²          Å              Õ  €         â   @        ô   €          €            @            €        -           >               R           a   
      cpu@200         „cpu           arm,cortex-a55          �           ”psci            ¢w5”         ²          Å              Õ  €         â   @        ô   €          €            @            €        -           >               R           a         cpu@300         „cpu           arm,cortex-a55          �           ”psci            ¢w5”         ²          Å              Õ  €         â   @        ô   €          €            @            €        -           >               R           a         cpu@600         „cpu           arm,cortex-a78          �           ”psci            ¢ƒ!V         ²           Å              Õ           â   @        ô                         @                    -           >              R           a         cpu@700         „cpu           arm,cortex-a78          �           ”psci            ¢ƒ!V         ²           Å              Õ           â   @        ô                         @                    -           >              R           a         cpu-map    cluster0       core0           i   	      core1           i   
      core2           i         core3           i         core6           i         core7           i               idle-states         mpsci       cpu-off-l             arm,idle-state          z            ‘        ¢   2        ³   _        Ã  D        a         cpu-off-b             arm,idle-state          z            ‘        ¢   -        ³   Œ        Ã  ä        a         cluster-off-l             arm,idle-state          z          ‘        ¢   7        ³   ›        Ã  H        a         cluster-off-b             arm,idle-state          z          ‘        ¢   2        ³   È        Ã  è        a            l2-cache0             cache           Ô           ×           ä   @        ö           -            à        a         l2-cache1             cache           Ô           ×           ä   @        ö           -            à        a         l3-cache              cache           Ô           ×            ä   @        ö            à        a            oscillator-13m            fixed-clock         î            ¢ Æ]@        ûclk13m          a   5      oscillator-26m            fixed-clock         î            ¢Œº€        ûclk26m          a   7      oscillator-32k            fixed-clock         î            ¢  €         ûclk32k        opp-table-gpu             operating-points-v2                  a   g   opp-390000000               >í€          Æ        .   ÿ      opp-431000000               °‰À          öì        .   ÿ      opp-473000000               1h@          	'À        .   ÿ      opp-515000000               ²FÀ          	X”        .   ÿ      opp-556000000               !#ã           	‰h        .   ÿ      opp-598000000               #¤Á€          	º<        .   ÿ      opp-640000000               &%            	ë        .   ÿ      opp-670000000               'ïc€          
ä        .   ÿ      opp-700000000               )¹'           
L¸        .   ÿ      opp-730000000               +‚ê€          
}Œ        .   ÿ      opp-760000000               -L®           
®`        .   ÿ      opp-790000000               /q€          
ß4        .   ÿ      opp-835000000               1ÅÀ          (r        .   ÿ      opp-880000000               4s¼           q°        .   ÿ      opp-915000000               6‰ÊÀ          ÓX        .   �      opp-915000000-5             6‰ÊÀ          ¢„        .   0      opp-915000000-6             6‰ÊÀ          q°        .   p      opp-950000000               8ŸÙ€          5         .   �      opp-950000000-5             8ŸÙ€          ÓX        .   0      opp-950000000-6             8ŸÙ€          q°        .   p         pmu-a55           arm,cortex-a55-pmu                      ?                  pmu-a78           arm,cortex-a78-pmu                      ?                  psci              arm,psci-1.0            ›smc       sound           J           \okay          6    mediatek,mt8390-mt6359-evk mediatek,mt8188-mt6359-evb            Dmt8390-evk          cdefault         q         t  {Headphone Headphone L Headphone Headphone R AP DMIC AUDGLB AP DMIC MIC_BIAS_0 AP DMIC MIC_BIAS_2 DMIC_INPUT AP DMIC         ‰         thermal-zones      cpu-little0-thermal         —  è        ¥   –        »          trips      trip-alert0         Ë L        ×  Ð         ?passive         a         trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical             cooling-maps       map0            â         0  ç   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little1-thermal         —  è        ¥   –        »         trips      trip-alert0         Ë L        ×  Ð         ?passive         a         trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical             cooling-maps       map0            â         0  ç   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little2-thermal         —  è        ¥   –        »         trips      trip-alert0         Ë L        ×  Ð         ?passive         a         trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical             cooling-maps       map0            â         0  ç   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little3-thermal         —  è        ¥   –        »         trips      trip-alert0         Ë L        ×  Ð         ?passive         a         trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical             cooling-maps       map0            â         0  ç   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-big0-thermal            —  è        ¥   d        »         trips      trip-alert0         Ë L        ×  Ð         ?passive         a         trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical             cooling-maps       map0            â           ç   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-big1-thermal            —  è        ¥   d        »         trips      trip-alert0         Ë L        ×  Ð         ?passive         a         trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical             cooling-maps       map0            â           ç   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            apu-thermal         —  è        ¥   ú        »          trips      trip-alert0         Ë L        ×  Ð         ?passive       trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical                gpu-thermal         —  è        ¥   ú        »         trips      trip-alert0         Ë L        ×  Ð         ?passive         a         trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical             cooling-maps       map0            â           ç   ÿÿÿÿÿÿÿÿ            gpu1-thermal            —  è        ¥   ú        »         trips      trip-alert0         Ë L        ×  Ð         ?passive         a         trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical             cooling-maps       map0            â           ç   ÿÿÿÿÿÿÿÿ            adsp-thermal            —  è        ¥   ú        »         trips      trip-alert0         Ë L        ×  Ð         ?passive       trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical                vdo-thermal         —  è        ¥   ú        »         trips      trip-alert0         Ë L        ×  Ð         ?passive       trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical                infra-thermal           —  è        ¥   ú        »         trips      trip-alert0         Ë L        ×  Ð         ?passive       trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical                cam1-thermal            —  è        ¥   ú        »         trips      trip-alert0         Ë L        ×  Ð         ?passive       trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical                cam2-thermal            —  è        ¥   ú        »         trips      trip-alert0         Ë L        ×  Ð         ?passive       trip-alert1         Ë s        ×  Ð         ?hot       trip-crit           Ë †         ×          	   ?critical                   timer             arm,armv8-timer                   @  ?                                             
               ¢ Æ]@      soc                      +             simple-bus          ö                                ú   performance-controller@11bc10             mediatek,cpufreq-hw          �     ¼            ½0                          a         interrupt-controller@c000000              arm,gic-v3                     ,                        C         �                                    ?      	               a      ppi-partitions     interrupt-partition-0           X   	   
              a         interrupt-partition-1           X              a               syscon@10000000            mediatek,mt8188-topckgen syscon         �                      î           a   #      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon          �                     î           a           a   $      syscon@10003000           mediatek,mt8188-pericfg syscon          �     0                î           a   F      pinctrl@10005000              mediatek,mt8188-pinctrl       `  �     P            À             á             â             ê              °              0  niocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint          x        ˆ           ”               °         C        ?       ë                       ”   RPI_GPIO0 RPI_GPIO1   RPI_GPIO4  RPI_GPIO6   RPI_GPIO9 RPI_GPIO10 RPI_GPIO11          RPI_GPIO21  RPI_GPIO23       RPI_GPIO30     RPI_GPIO35 RPI_GPIO36                   RPI_GPIO55 RPI_GPIO56   RPI_GPIO59 RPI_GPIO60         RPI_GPIO69   RPI_GPIO72 RPI_GPIO73 RPI_GPIO74     RPI_GPIO79 RPI_GPIO80 RPI_GPIO81 RPI_GPIO82                                       RPI_GPIO121 RPI_GPIO122 RPI_GPIO123 RPI_GPIO124         a       i2c1-pins           a   a   pins            °  :  9        ·   Ë        Ä  è         mmc0-default-pins           a   Q   pins-clk            °  �        Ü           ë   f      pins-cmd-dat          $  °  ¡     Ÿ  ž  š  ™  ˜  —  œ         ú        Ü           ·   e      pins-rst            °  ›        Ü           ·   e         mmc0-uhs-pins           a   R   pins-clk            °  �        Ü           ë   f      pins-cmd-dat          $  °  ¡     Ÿ  ž  š  ™  ˜  —  œ         ú        Ü           ·   e      pins-ds         °  ¢        Ü           ë   f      pins-rst            °  ›        Ü           ·   e         i2c0-pins           a   V   pins            °  8  7        ·   Ë        Ä  è         i2c2-pins           a   W   pins            °  <  ;        ·   Ë        Ä  è         i2c3-pins           a   X   pins            °  >  =        ·   Ë        Ä  è         i2c5-pins           a   c   pins            °  B  A        ·   Ë        Ä  è         i2c6-pins           a   d   pins            °  D  C        ·   Ë        Ä  è         uart0-pins          a   ?   pins            °              ·         uart1-pins          a   @   pins            °  V  W         ·         uart2-pins          a   A   pins            °  #  $         ·         pcie-default            a   _   mux         °  /  0  1         ·         eth-default-pins            a   O   pins-cc         °  ‹  Œ  �  Ž        Ü         pins-mdio           °  �  �        Ü            ú      pins-power          °  ‘   ’                pins-rxd            °  ‡  ˆ  ‰  Š        Ü         pins-txd            °  ƒ  „  …  †        Ü            eth-sleep-pins          a   P   pins-cc         °  ‹   Œ   �   Ž       pins-mdio           °  �   �                   !      pins-rxd            °  ‡   ˆ   ‰   Š       pins-txd            °  ƒ   „   …   †          spi2-pins           a   C   pins-spi            °  O  P  Q  R         !         audio-default-pins          a      pins-cmd-dat            °  y  z  {  |         usb-default-pins            a   [   pins-valid          °  U         ú            syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd            �     `           power-controller          !    mediatek,mt8188-power-controller                         +            .           a   8   power-domain@0          �                         +            .           B   !   power-domain@1          �           P   "      #           Wmfg alt         c   $                     +            .           B   %   power-domain@2          �           .          power-domain@3          �           .          power-domain@4          �           .                power-domain@15         �         à  P   #      #      #      #   
   #   3   #   4   #   =   #   ¹   #   ¾   &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &          û  Wtop cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1          c   $                     +            .      power-domain@16         �         H  P   #   »   #   À   '      '      '      '      '      '      '         A  Wcfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus            c   $                     +            .      power-domain@20         �         0  P   #   º   #   ¿   (      (      (      (         8  Wcfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6         c   $        .          power-domain@22         �           P   )            Wss-vdec1-soc-l1         c   $                     +            .      power-domain@23         �           P   *            Wss-vdec2-l1         c   $        .             power-domain@29         �            P   #      #      #   	   #   ½        Wcam ccu bus cfgck           c   $                     +            .      power-domain@30         �         (  P   +       +      +      +      +         6  Wss-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys           c   $                     +            .      power-domain@32         �            P   +      ,       -          $  Wss-camb-sub ss-camb-raw ss-camb-yuv         .          power-domain@31         �           P   +      .       /          $  Wss-cama-sub ss-cama-raw ss-cama-yuv         .                power-domain@17         �         (  P   #   ¼   #   Á   0       0      0         &  Wcfgck cfgxo ss-larb2 ss-larb3 ss-gals           c   $                     +            .      power-domain@9          �   	        P   #   @   #   ?      	  Wbus hdcp            c   $        .          power-domain@18         �           c   $        .          power-domain@19         �           c   $        .             power-domain@24         �            P   1       1      1      1         0  Wss-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram         c   $        .          power-domain@21         �           P   2      2           Wss-wpe-l7 ss-wpe-l7pce          c   $        .                power-domain@5          �           c   $        P   3           Wss-pextp-fmem           .          power-domain@7          �           P   #   0   #   1        Wseninf0 seninf1         .          power-domain@6          �           .          power-domain@10         �   
        P   #   E   #   D      	  Wbus main            c   $                     +            .      power-domain@11         �           c   $                     +            .      power-domain@14         �           P   #   F        Wasm         c   $        .          power-domain@13         �           P   #   S   #      4            Wa1sys intbus adspck         c   $        .          power-domain@12         �           c   $        .                power-domain@8          �           P   3         	  Wethermac            c   $        .                watchdog@10007000             mediatek,mt8188-wdt         �     p                 u        a           a   9      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon           �     À                î           a   "      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer         �    p                ?      	               P   5      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon          �    @                npwrap           ?       ó               P   $      $          	  Wspi wrap       pmic              mediatek,mt6359          C                   �                        ?   Þ           ž       Þ      adc           mediatek,mt6359-auxadc          ²         audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            Ävs1         Ó 5         ë !‘À                           buck_vgpu11       
  Ädvdd_core           Ó €        ë 7        3  ˆ           È        H                         buck_vmodem         Ävmodem          Ó €        ë Èà        3  *           È      buck_vpu          
  Ädvdd_adsp           Ó €        ë 7        3  ˆ           È        H                         buck_vcore          Ädvdd_proc_l         Ó €        ë Ö         3  ˆ           È        H                         buck_vs2            Ävs2         Ó 5         ë j                            buck_vpa            Ävpa_pmu         Ó ¡         ë /M`          ,      buck_vproc2         Ävgpu            Ó dp        ë 5         3  L           È        H                  `   %        w  j        a   !      buck_vproc1         Ävproc1          Ó €        ë 7        3  L           È        H                buck_vcore_sshub            Ävcore_sshub         Ó €        ë 7      buck_vgpu11_sshub           Ävgpu11_sshub            Ó €        ë 7      ldo_vaud18          Ävaud18          Ó w@        ë w@           ð      ldo_vsim1         
  Ävsim1_pmu           Ó ð         ë /M`          à      ldo_vibr            Ävibr            Ó O€        ë 2Z       ldo_vrf12           Äva12_abb2_pmu           Ó Èà        ë Ö                ldo_vusb            Ävusb            Ó -ÆÀ        ë -ÆÀ          À                 a   G      ldo_vsram_proc2         Ävsram_proc2         Ó ¡         ë ½¶        3  L           ð               ldo_vio18           Ävio18           Ó ð         ë ýà          À               ldo_vcamio          Ävcamio          Ó ð         ë ýà      ldo_vcn18         
  Ävcn18_pmu           Ó w@        ë w@           ð               ldo_vfe28           Ävfe28           Ó *¹€        ë *¹€           x      ldo_vcn13           Ävcn13           Ó »         ë Ö       ldo_vcn33_1_bt          Ävcn33_1_bt          Ó *¹€        ë 5gà      ldo_vcn33_1_wifi            Ävcn33_1_wifi            Ó *¹€        ë 5gà      ldo_vaux18          Ävaux18          Ó w@        ë w@           ð               ldo_vsram_others          
  Ävsram_gpu           Ó q°        ë 5         3  ˆ           ð        `   !        w  j        a   %      ldo_vefuse          Ävefuse          Ó ð         ë „€      ldo_vxo22           Ävxo22           Ó w@        ë !‘À               ldo_vrfck           Ävrfck           Ó ã`        ë ð       ldo_vrfck_1         Ävrfck_1         Ó ëÀ        ë j       ldo_vbif28          Ävbif28          Ó *¹€        ë *¹€           ð      ldo_vio28           Ävio28           Ó *¹€        ë 2Z                ldo_vemc            Ävemc            Ó ,@         ë 2Z       ldo_vemc_1          Ävemc_1          Ó &%         ë 2Z         a   S      ldo_vcn33_2_bt          Ävcn33_2_pmu         Ó *¹€        ë 5gà               ldo_vcn33_2_wifi            Ävcn33_2_wifi            Ó *¹€        ë 5gà      ldo_va12            Äva12            Ó O€        ë Ö                ldo_va09            Äva09            Ó 5         ë O€      ldo_vrf18           Ävrf18           Ó ð         ë žP      ldo_vsram_md          	  Ävsram_md            Ó ¡         ë ½¶        3  *           ð      ldo_vufs            Ävufs18_pmu          Ó ð         ë ýà                 a   T      ldo_vm18            Ävm18            Ó ð         ë ýà               ldo_vbbck           Ävbbck           Ó Èà        ë O€               ldo_vsram_proc1         Ävsram_proc1         Ó ¡         ë ½¶        3  L           ð               ldo_vsim2           Ävsim2           Ó ð         ë /M`      ldo_vsram_others_sshub          Ävsram_others_sshub          Ó ¡         ë ½¶         rtc           mediatek,mt6358-rtc       keys              mediatek,mt6359-keys            ”           ­       power-key           À   t         Ï               spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi            �    p            �                npmif spmimst            Ý   #   8        í   #   ¬        P   $      $       #   8      (  Wpmif_sys_ck pmif_tmr_ck spmimst_clk_mux       iommu@10315000            mediatek,mt8188-iommu-infra         �    1P                ?                                a   ]      mailbox@10320000              mediatek,mt8188-gce         �    2        @         ?       â                          P   $           a   h      mailbox@10330000              mediatek,mt8188-gce         �    3        @         ?       ä                          P   $           a   j      scp@10720000              mediatek,mt8188-scp-dual            �    r                 ncfg                      +           ú        P             \okay       scp@0             mediatek,scp-core           �               nsram            ?      Î               \okay               6        a   k      scp@d0000             mediatek,scp-core           �    ð         nsram            ?      Ï             	  \disabled             audio-controller@10b10000             mediatek,mt8188-afe         �    ±                 Ý   #   S        í   #   „      ´  P   7   "   	   "   
   #   ³   #   ´   #   µ   #   ¶   #   ¸   #   S   #      #       #   E   #   Q   #   M   #   N   #   O   #   P   4       #   „   #   †   #   ·   #   T   #   R      ÿ  Wclk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          ?      6               +   8           9   9         	  @audiosys            c   $        L   #        \okay               :        a         adsp@10b80000             mediatek,mt8188-dsp       @  �    ¸              Ð             ¸°            ¸ð                ncfg sram sec bus            Ý   #   D        P   #   D   #   E        Waudiodsp adsp_bus           ^   ;   <        erx tx           +   8           \okay               =   >        a         mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         �    ¸a                ?      Þ                           a   ;      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         �    ¸q                ?      ß                           a   <      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m           �    ¹                î           a   4      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart           �                     ?       �               P   7   $         	  Wbaud bus            \okay            cdefault         q   ?      serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart           �                     ?       Ž               P   7   $         	  Wbaud bus            \okay            cdefault         q   @      serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart           �                     ?       �               P   7   $         	  Wbaud bus            \okay            cdefault         q   A      serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart           �                     ?      Ó               P   7   $         	  Wbaud bus          	  \disabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc           �                      P   $           Wmain            ²         	  \disabled          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon           �     0                î           a   3      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            �                      ?       ¿               P   #   y   #      $           Wparent-clk sel-clk spi-clk        	  \disabled          thermal-sensor@1100b000           mediatek,mt8188-lvts-ap         �     °                ?       È               P   $           9   $           p   B        |lvts-calib-data-1           �           a         pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           �     à                P   #   '   $   /        Wmain mm         ?       Ë               £         	  \disabled          pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           �     ð                P   #   (   $   F        Wmain mm         ?                     £         	  \disabled          spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            �                     ?       À               P   #   y   #      $   2        Wparent-clk sel-clk spi-clk        	  \disabled          spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            �                     ?       Á               P   #   y   #      $   3        Wparent-clk sel-clk spi-clk          \okay            cdefault         q   C        ®          spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            �    0                ?       Â               P   #   y   #      $   4        Wparent-clk sel-clk spi-clk        	  \disabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            �    €                ?       Ã               P   #   y   #      $   8        Wparent-clk sel-clk spi-clk        	  \disabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            �    �                ?       Ä               P   #   y   #      $   9        Wparent-clk sel-clk spi-clk        	  \disabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3           �            -ÿ     >              	  nmac ippc            ú                     ?                      +           ?       €               Ý   #   )        í   #   v        P   3   	   #   Å   3   
        Wsys_ck ref_ck mcu_ck            Â   D      E            Ï        Ç   F  h           \okay            Þhost            æsuper-speed         ô   G   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          �                       nmac         ?       �               Ý   #   *        í   #   v        P   3   
        Wsys_ck          \okay                         +            ô   G   hub@1             usb451,8027         �              H                              I        a   J      hub@2             usb451,8025         �              J                              I        a   H            ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a          �           @         ?      Ì               "macirq        0  P   3       3      #   A   #   B   #   C   3         .  Waxi apb mac_main ptp_ref rmii_internal mac_cg           Ý   #   A   #   B   #   C        í   #       #   ¢   #   £        +   8           2   $        C   K        S   L        f   M        y           „           �            \okay          	  œrgmii-id            ¥   N        cdefault sleep           q   O        °   P         º        Ë            à        ö      *ø @        	       “      mdio              snps,dwmac-mdio                      +       ethernet-phy@3            ethernet-phy-ieee802.3-c22          �           ž       ”            	        a   N         stmmac-axi-config           	,                                 	6           	F           a   K      rx-queues-config            	V            	l        a   L   queue0           	}        	�          queue1           	}        	�          queue2           	}        	�          queue3           	}        	�             tx-queues-config            	¨            	¾        a   M   queue0           	}        	Ð            	Þ         queue1           	}        	Ð           	Þ         queue2           	}        	Ð           	Þ         queue3           	}        	Ð           	Þ               mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          �    #             õ                 ž          ƒ                P   #      $      $      $   M      !  Wsource hclk source_cg crypto_clk            \okay            cdefault state_uhs           q   Q        °   R        	ê           	ôëÂ          
         
         
#         
2         
?         
P         
X        
^ H        
m   S        
y   T         
†      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          �    $             ë                 ž          ‡               P   #      $      $   $        Wsource hclk source_cg           Ý   #           í   #   �      	  \disabled          mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          �    %             æ                 ž          ˆ               P   #      $      $   A        Wsource hclk source_cg           Ý   #           í   #   �      	  \disabled          thermal-sensor@11278000           mediatek,mt8188-lvts-mcu            �    '€                ?       Ê               P   $           9   $            p   B        |lvts-calib-data-1           �           a         i2c@11280000              mediatek,mt8188-i2c          �    (             " €       €        ?       —               
”           P   U       $   7      	  Wmain dma                         +            \okay            cdefault         q   V        ¢ €      i2c@11281000              mediatek,mt8188-i2c          �    (            "€       €        ?       ’               
”           P   U      $   7      	  Wmain dma                         +            \okay            cdefault         q   W        ¢ €      i2c@11282000              mediatek,mt8188-i2c          �    (             "€       €        ?       “               
”           P   U      $   7      	  Wmain dma                         +            \okay            cdefault         q   X        ¢ €      clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c          �    (0                î           a   U      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           �    *       -ÿ    *>              	  nmac ippc            ú            *        ?                      +           ?                     Ý   #   -        í   #   v        P   3      #   Ë   3           Wsys_ck ref_ck mcu_ck            Â   Y            Ï        Ç   F  p           \okay            Þhost            æhigh-speed          ô   G   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          �                       nmac         ?                     Ý   #   .        í   #   v        P   3           Wsys_ck          \okay                         +            ô   G   hub@1             microchip,usb2513bi         �              I            usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           �    +       -ÿ    +>              	  nmac ippc            ú            +        ?                      +           ?                     Ý   #   ,        í   #   v        P   3      #   É   3           Wsys_ck ref_ck mcu_ck            Â   Z            Ï        Ç   F  `           \okay            Þperipheral          cdefault         q   [        ô   G   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          �                       nmac         ?                     Ý   #   +        í   #   v        P   3           Wsys_ck        	  \disabled             pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie           �    /                	  npcie-mac            ú‚                                  
ž       ÿ        „pci         
¨                         +         0  P   $   L   $   #   $   &   $   +   $   C   3         /  Wpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                     ?                   `  
¹                  \                      \                     \                     \           
Ç                       
Ú       ]      ÿÿ        
ä            Â   ^         	  
ópcie-phy            +   8           9   9           @mac         \okay            cdefault         q   _   interrupt-controller                                     C        a   \         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor         �    2À                P   #   X   3      3           Wspi sf axi          Ý   #   X        ?      9                            +          	  \disabled          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3           ú        Â                         +           +   8           \okay       pcie-phy@0          �               P   #   Ä        Wref         
ý           a   ^         hdmi-phy@11d5f000         2    mediatek,mt8188-hdmi-phy mediatek,mt8195-hdmi-phy           �    Õð                P   $           Wpll_ref         ûhdmi_txpll          î            
ý               
                 	  \disabled            a   †      dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         �    È                 P   7        ûmipi_tx0_pll            î            
ý          	  \disabled            a         dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         �    É                 P   7        ûmipi_tx0_pll            î            
ý          	  \disabled            a   €      i2c@11e00000              mediatek,mt8188-i2c          �    à             "        €        ?       ˜               
”           P   `       $   7      	  Wmain dma                         +            \okay            cdefault         q   a        ¢ €      i2c@11e01000              mediatek,mt8188-i2c          �    à            "€       €        ?       ”               
”           P   `      $   7      	  Wmain dma                         +          	  \disabled          clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w          �    à                 î           a   `      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           ú        ã             \okay       usb-phy@0           �               P   #   Ê   "           Wref da_ref          
ý           a   Z         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           ú        ä             \okay       usb-phy@0           �               P   #   Æ   "           Wref da_ref          
ý           a   D      usb-phy@700         �              P   "      7        Wref da_ref          
ý           a   E         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           ú        è             \okay       usb-phy@0           �               P   #   Ì   "           Wref da_ref          
ý           a   Y         i2c@11ec0000              mediatek,mt8188-i2c          �    ì             "€       €        ?       •               
”           P   b       $   7      	  Wmain dma                         +            \okay            cdefault         q   c        ¢ €      i2c@11ec1000              mediatek,mt8188-i2c          �    ì            "        €        ?       –               
”           P   b      $   7      	  Wmain dma                         +            \okay            cdefault         q   d        ¢ €      clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en         �    ì                 î           a   b      efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse         �    ò                              +      dp-calib@1a0            �              a   ‡      lvts1-calib@1ac         �  ¬   @        a   B      gpu-speedbin@581            �  �           )               a   f      socinfo-data1@7a0           �            socinfo-data2@7e0           �  à            gpu@13000000          )    mediatek,mt8370-mali arm,mali-valhall-jm            �             @         P   e          0  ?                   ~             }               "job mmu gpu         p   f      
  |speed-bin           .   g        +   8      8           Bcore0 core1         R           \okay            U   !        a         clock-controller@13fbf000             mediatek,mt8188-mfgcfg          �    ûð                î           a   e      syscon@14000000           mediatek,mt8188-vppsys0 syscon          �                      î           a   &      dma-controller@14001000           mediatek,mt8188-mdp3-rdma           �                     a           P   &         <  ^   h         h         h         h         h              l   i   €        +   8           s   j                  ‹              Ÿ   k      display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         �                      P   &            s   j                 display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           �     @                P   &   "        s   j      @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           �     P                ?      F               P   &   
        +   8           s   j      P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           �     `                P   &           s   j      `            ‹    %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           �     p                P   &   #        s   j      p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           �     €                ?      I               P   &   $        +   8           s   j      €          display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl           �     �                ?      J               P   &   %        +   8           s   j      �            l   i   ‚      display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           �                      P   &           +   8           s   j                 display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc           �     °                P   &           s   j      °          display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         �     À                a           P   &           l   i   ƒ        +   8           s   j      À            ‹    +      mutex@1400f000            mediatek,mt8188-vpp-mutex           �     ð                ?      P               P   &           +   8           s   j      ð          smi@14012000              mediatek,mt8188-smi-common-vpp          �                     P   &      &           Wapb smi         +   8           a   l      smi@14013000              mediatek,mt8188-smi-larb            �    0                P   &      &           Wapb smi         +   8           ¬           ½   l        a   o      iommu@14018000            mediatek,mt8188-iommu-vpp           �    €       P         P   &           Wbclk            ?      R               +   8                      Ê   m   n   o   p   q   r        a   i      dma-controller@14f09000           mediatek,mt8188-mdp3-rdma           �    ð�                a           P   (   
        l   s   ¤        +   8           s   j   	  �            ‹  …  ©      dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma           �    ð                 a           P   (           l   i   À        +   8           s   j   	               ‹  †  ª      display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         �    ðÀ                P   (           s   j   	  À          display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         �    ðÐ                P   (           s   j   	  Ð          display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           �    ðð                P   (   "        s   j   	  ð          display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           �    ñ                 P   (   $        s   j   
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           �    ñ                 ?      j               P   (   #        +   8           s   j   
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           �    ñ0                ?      k               P   (   %        +   8           s   j   
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           �    ñP                P   (           s   j   
  P            ‹  ‘  °      display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           �    ñ`                P   (           s   j   
  `            ‹  ’  ±      display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           �    ñ€                P   (           s   j   
  €          display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           �    ñ�                P   (           s   j   
  �          display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           �    ñ                 P   (           +   8           s   j   
             display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           �    ñ°                P   (           +   8           s   j   
  °          display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           �    ñÐ                ?      u               P   (           +   8           s   j   
  Ð          display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           �    ñà                ?      v               P   (           +   8           s   j   
  à          display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           �    ò                P   (           +   8           s   j               display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           �    ò                 P   (           +   8           s   j                display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         �    ò@                a           P   (           l   s   ¦        +   8           s   j     @            ‹     ¬      display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         �    òP                a           P   (           l   i   Â        +   8           s   j     P            ‹  ¡  ­      clock-controller@14e00000             mediatek,mt8188-wpesys          �    à                 î           a   2      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0         �    à                 î         smi@14e04000              mediatek,mt8188-smi-larb            �    à@                P   2      2           Wapb smi         +   8           ¬           ½   l        a   q      syscon@14f00000           mediatek,mt8188-vppsys1 syscon          �    ð                 î           a   (      mutex@14f01000            mediatek,mt8188-vpp-mutex           �    ð                ?      {               P   (   &        +   8           s   j   	            smi@14f02000              mediatek,mt8188-smi-larb            �    ð                 P   (      (           Wapb smi         +   8           ¬           ½   t        a   ƒ      smi@14f03000              mediatek,mt8188-smi-larb            �    ð0                P   (      (           Wapb smi         +   8           ¬           ½   l        a   p      clock-controller@15000000             mediatek,mt8188-imgsys          �                      î         clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top         �                     î           a         clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr          �                     î           a         clock-controller@15220000             mediatek,mt8188-imgsys-wpe1         �    "                 î           a         clock-controller@15330000             mediatek,mt8188-ipesys          �    3                 î           a         clock-controller@15520000             mediatek,mt8188-imgsys-wpe2         �    R                 î           a         clock-controller@15620000             mediatek,mt8188-imgsys-wpe3         �    b                 î           a         clock-controller@16000000             mediatek,mt8188-camsys          �                      î           a   +      clock-controller@1604f000             mediatek,mt8188-camsys-rawa         �    ð                î           a           a   .      clock-controller@1606f000             mediatek,mt8188-camsys-yuva         �    ð                î           a           a   /      clock-controller@1608f000             mediatek,mt8188-camsys-rawb         �    ð                î           a           a   ,      clock-controller@160af000             mediatek,mt8188-camsys-yuvb         �    
ð                î           a           a   -      clock-controller@17200000             mediatek,mt8188-ccusys          �                      î         video-decoder@18000000            mediatek,mt8188-vcodec-dec           �                   @                ú                    `         l   i  æ                     +           Ÿ   k   video-codec@10000             mediatek,mtk-vcodec-lat         �                      Ý   #   4        í   #   x         P   #   4   )      )      #   x        Wsel vdec lat top            ?      Ä             H  l   i  à   i  á   i  â   i  ã   i  ä   i  å   i  æ   i  ç   i  è        +   8         video-codec@25000             mediatek,mtk-vcodec-core            �     P                Ý   #   4        í   #   x         P   #   4   *      *      #   x        Wsel vdec lat top            ?      Ã             X  l   s  À   s  Á   s  Â   s  Ã   s  Ä   s  Å   s  Æ   s  Ç   s  È   s  É   s  Ê        +   8            smi@1800d000              mediatek,mt8188-smi-larb            �     Ð                P   )       )            Wapb smi         +   8           ¬           ½   l        a   r      clock-controller@1800f000             mediatek,mt8188-vdecsys-soc         �     ð                î           a   )      smi@1802e000              mediatek,mt8188-smi-larb            �    à                P   *       *            Wapb smi         +   8           ¬           ½   t        a   …      clock-controller@1802f000             mediatek,mt8188-vdecsys         �    ð                î           a   *      clock-controller@1a000000             mediatek,mt8188-vencsys         �                      î           a   1      smi@1a010000              mediatek,mt8188-smi-larb            �                     P   1      1           Wapb smi         +   8           ¬           ½   t        a   „      video-encoder@1a020000            mediatek,mt8188-vcodec-enc          �                                  +           Ý   #   3        í   #   p        P   1         	  Wvenc_sel            ?      a             X  l   s      s  ¡   s  ¢   s  £   s  ¤   s  ¶   s  ·   s  ¸   s  ¹   s  ª   s  º        +   8           Ÿ   k      jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc          �                     P   1           Wjpgenc          ?      b                l   s  §   s  ¨   s  ©   s  ¬        +   8         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec           �                     P   1       1           Wjpgdec-smi jpgdec           ?      c             0  l   s  ­   s  ®   s  ²   s  ³   s  ´   s  µ        +   8         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl           �                      P   '            ?      |               l   s           +   8           s   h             ports                        +       port@0          �       endpoint             port@1          �      endpoint            Ù   u        a   v               rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma         �                      P   '           ?      ~               l   i            +   8           s   h             ports                        +       port@0          �       endpoint            Ù   v        a   u         port@1          �      endpoint            Ù   w        a   x               color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color           �     0                P   '           ?                     +   8           s   h     0       ports                        +       port@0          �       endpoint            Ù   x        a   w         port@1          �      endpoint            Ù   y        a   z               ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr           �     @                P   '           ?      €               +   8           s   h     @       ports                        +       port@0          �       endpoint            Ù   z        a   y         port@1          �      endpoint            Ù   {        a   |               aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal           �     P                P   '           ?      �               +   8           s   h     P       ports                        +       port@0          �       endpoint            Ù   |        a   {         port@1          �      endpoint            Ù   }        a   ~               gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma           �     `                P   '           ?      ‚               +   8           s   h     `       ports                        +       port@0          �       endpoint            Ù   ~        a   }         port@1          �      endpoint                   dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither         �     p                P   '           ?      ƒ               +   8           s   h     p       ports                        +       port@0          �       endpoint             port@1          �      endpoint                   dsi@1c008000              mediatek,mt8188-dsi         �     €                P   '      '              Wengine digital hs           ?      „               Â           
ódphy            +   8           9   '         	  \disabled          dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc           �     �                P   '   
        ?      …               +   8           s   h     �          dsi@1c012000              mediatek,mt8188-dsi         �                     P   '   	   '      €        Wengine digital hs           ?      Ž               Â   €        
ódphy            +   8           9   '   	      	  \disabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           �    @                P   '      0           Wmerge merge_async           ?      �               +   8           s   h     @          dp-intf@1c015000              mediatek,mt8188-dp-intf         �    P                P   '       '      "           Wpixel engine pll            ?      ‘               +   8         	  \disabled          mutex@1c016000            mediatek,mt8188-disp-mutex          �    `                P   '           ?      ’               +   8           s   h     `            ‹  >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask         �                     P   '           ?      •               +   8           s   h             ports                        +       port@0          �       endpoint             port@1          �      endpoint                   syscon@1c01d000           mediatek,mt8188-vdosys0 syscon          �    Ð                î           a           ^   h               s   h     Ð            a   '      smi@1c022000              mediatek,mt8188-smi-larb            �                     P   '      '           Wapb smi         +   8           ¬            ½   t        a   �      smi@1c023000              mediatek,mt8188-smi-larb            �    0                P   '      '           Wapb smi         +   8           ¬           ½   l        a   m      smi@1c024000              mediatek,mt8188-smi-common-vdo          �    @                P   '      '           Wapb smi         +   8           a   t      iommu@1c028000            mediatek,mt8188-iommu-vdo           �    €       P         P   '           Wbclk            ?      ¡               +   8                      Ê   �   ‚   ƒ   „   …        a   s      syscon@1c100000           mediatek,mt8188-vdosys1 syscon          �                     î           a           ^   h              s   h                  a   0      mutex@1c101000            mediatek,mt8188-disp-mutex          �                    P   0           ?      î               +   8           s   h                 ‹  Å      smi@1c102000              mediatek,mt8188-smi-larb            �                     P   0       0            Wapb smi         +   8           ¬           ½   t        a   ‚      smi@1c103000              mediatek,mt8188-smi-larb            �    0                P   0      0           Wapb smi         +   8           ¬           ½   l        a   n      rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         �    @                P   0           ?      ï               l   s   @        +   8           a           s   h     @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         �    P                P   0           ?      ð               l   i   `        +   8           a           s   h     P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         �    `                P   0           ?      ñ               l   s   A        +   8           a           s   h     `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         �    p                P   0           ?      ò               l   i   a        +   8           a           s   h     p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         �    €                P   0           ?      ó               l   s   B        +   8           a           s   h     €          rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         �    �                P   0           ?      ô               l   i   b        +   8           a           s   h     �          rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         �                     P   0           ?      õ               l   s   C        +   8           a           s   h                rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         �    °                P   0           ?      ö               l   i   c        +   8           a           s   h     °          merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           �    À                P   0   	   0           Wmerge merge_async           ?      ÷               +   8           9   0           s   h     À             é      merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           �    Ð                P   0   
   0           Wmerge merge_async           ?      ø               +   8           9   0           s   h     Ð             é      merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           �    à                P   0      0           Wmerge merge_async           ?      ù               +   8           9   0           s   h     à             é      merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           �    ð                P   0      0           Wmerge merge_async           ?      ú               +   8           9   0           s   h     ð             é      merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           �                     P   0      0           Wmerge merge_async           ?      û               +   8           9   0           s   h                   ý      dpi@1c112000          (    mediatek,mt8188-dpi mediatek,mt8195-dpi         �                     P   0   8   0      0   =        Wpixel engine pll            ?                     +   8           9   0         	  \disabled       ports                        +       port@0          �       endpoint             port@1          �      endpoint                   dp-intf@1c113000              mediatek,mt8188-dp-intf         �    0                P   0   :   0      "           Wpixel engine pll            ?                     +   8         	  \disabled          ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p  �    @            P            p            �                         °            À              4  nmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h  P   0   0   0   +   0   .   0   ,   0   /   0   -   0   <   0   1   0   2   0   3   0   4   0   5   #         ƒ  Wmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          ?      6               l   i   d   i   e        +   8         (  9   0   1   0   2   0   3   0   4   0   5      p  s   h     @       h     P       h     p       h     �       h             h     °       h     À          padding@1c11d000              mediatek,mt8188-disp-padding            �    Ð                P   0           +   8           s   h     Ð          padding@1c11e000              mediatek,mt8188-disp-padding            �    à                P   0            +   8           s   h     à          padding@1c11f000              mediatek,mt8188-disp-padding            �    ð                P   0   !        +   8           s   h     ð          padding@1c120000              mediatek,mt8188-disp-padding            �                     P   0   "        +   8           s   h                padding@1c121000              mediatek,mt8188-disp-padding            �                    P   0   #        +   8           s   h               padding@1c122000              mediatek,mt8188-disp-padding            �                     P   0   $        +   8           s   h                padding@1c123000              mediatek,mt8188-disp-padding            �    0                P   0   %        +   8           s   h     0          padding@1c124000              mediatek,mt8188-disp-padding            �    @                P   0   &        +   8           s   h     @          hdmi@1c300000             mediatek,mt8188-hdmi-tx         �           �    0                  P   #   @   #   >   #   ?   (   .        Wbus hdcp hdcp24m hdmi-split         Ý   #   >        í   #   s        ?      ®               +   8   	        Â   †        
óhdmi          	  \disabled       i2c       2    mediatek,mt8188-hdmi-ddc mediatek,mt8195-hdmi-ddc           P   7      ports                        +       port@0          �       endpoint             port@1          �      endpoint                   edp-tx@1c500000           mediatek,mt8188-edp-tx          �    P        €         ?      ¤               p   ‡        |dp_calibration_data         +   8             ¤      	  \disabled          dp-tx@1c600000            mediatek,mt8188-dp-tx           �    `        €         ?      Ê               p   ‡        |dp_calibration_data         +   8                   	  \disabled             chosen          %serial0:921600n8          firmware       optee             linaro,optee-tz         ›smc          reserved-memory                      +            ú   optee@43200000           1        �    C        À        memory@50000000           shared-dma-pool         �    P       �           1        a   6      memory@54600000          1        �    T`                memory@55000000           shared-dma-pool         �    U       @        memory@57000000           shared-dma-pool         �    W       @        memory@60000000           shared-dma-pool         �    `        ð           1        a   >      memory@60f00000           shared-dma-pool         �    `ð                  1        a   :      memory@61000000           shared-dma-pool         �    a                   1        a   =         regulator-vsys            regulator-fixed         Ävsys                      8        a   ˆ      regulator-0           regulator-fixed       
  Äfixed-5v0           Ó LK@        ë LK@         J                 ]   ˆ      regulator-1           regulator-fixed       
  Äfixed-4v2           Ó @@        ë @@         J                 ]   ˆ      regulator-2           regulator-fixed       
  Äfixed-3v3           Ó 2Z         ë 2Z          J                 ]   ˆ        a   I      memory@40000000         „memory          �    @                   	compatible interrupt-parent #address-cells #size-cells chassis-type model dp-intf0 dp-intf1 dpi1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c1 mmc0 ethernet0 i2c0 i2c2 i2c3 i2c5 i2c6 serial0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status pinctrl-names pinctrl-0 audio-routing mediatek,adsp polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux bias-pull-up drive-strength-microamp drive-strength bias-pull-down input-enable output-high input-disable bias-disable #power-domain-cells domain-supply clocks clock-names mediatek,infracfg mediatek,disable-extrst #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells memory-region power-domains resets reset-names mediatek,topckgen mboxes mbox-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select phys mediatek,syscon-wakeup dr_mode maximum-speed vusb33-supply peer-hub reset-gpios vdd-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,mac-wol mediatek,tx-delay-ps snps,reset-active-low snps,reset-delays-us snps,reset-gpio eee-broken-1000t snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable clock-div bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names #phy-cells mediatek,ibias mediatek,ibias_up bits operating-points-v2 power-domain-names mali-supply #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz stdout-path no-map regulator-boot-on enable-active-high vin-supply 