Ðþí wO   8 iT   (            û i                             4    mediatek,mt8395-evk mediatek,mt8395 mediatek,mt8195                                  +         "   7MediaTek Genio 1200 EVK-P1V2-EMMC      aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/mailbox@10320000            Y/soc/mailbox@10330000            ^/soc/hdmi-tx@1c300000            d/soc/hdr-engine@1c114000             k/soc/mutex@1c016000          r/soc/mutex@1c101000          y/soc/vpp-merge@1c10c000          €/soc/vpp-merge@1c10d000          ‡/soc/vpp-merge@1c10e000          Ž/soc/vpp-merge@1c10f000          •/soc/vpp-merge@1c110000          œ/soc/dma-controller@1c104000             §/soc/dma-controller@1c105000             ²/soc/dma-controller@1c106000             ½/soc/dma-controller@1c107000             È/soc/dma-controller@1c108000             Ó/soc/dma-controller@1c109000             Þ/soc/dma-controller@1c10a000             é/soc/dma-controller@1c10b000             ô/soc/ethernet@11021000           þ/soc/mmc@11230000           /soc/mmc@11240000           /soc/serial@11001100          cpus                         +       cpu@0           cpu           arm,cortex-a55                       psci            .               Bec3@        R  4        e              u  €         ‚   @        ”   €        ¡  €         ®   @        À   €        Í           Þ           í           ø         cpu@100         cpu           arm,cortex-a55                      psci            .               Bec3@        R  4        e              u  €         ‚   @        ”   €        ¡  €         ®   @        À   €        Í           Þ           í           ø         cpu@200         cpu           arm,cortex-a55                      psci            .               Bec3@        R  4        e              u  €         ‚   @        ”   €        ¡  €         ®   @        À   €        Í           Þ           í           ø         cpu@300         cpu           arm,cortex-a55                      psci            .               Bec3@        R  4        e              u  €         ‚   @        ”   €        ¡  €         ®   @        À   €        Í           Þ           í           ø         cpu@400         cpu           arm,cortex-a78                      psci            .              B�fÔÀ        R           e              u           ‚   @        ”           ¡           ®   @        À           Í   	        Þ           í   
        ø         cpu@500         cpu           arm,cortex-a78                      psci            .              B�fÔÀ        R           e              u           ‚   @        ”           ¡           ®   @        À           Í   	        Þ           í   
        ø         cpu@600         cpu           arm,cortex-a78                      psci            .              B�fÔÀ        R           e              u           ‚   @        ”           ¡           ®   @        À           Í   	        Þ           í   
        ø         cpu@700         cpu           arm,cortex-a78                      psci            .              B�fÔÀ        R           e              u           ‚   @        ”           ¡           ®   @        À           Í   	        Þ           í   
        ø         cpu-map    cluster0       core0                     core1                     core2                     core3                     core4                     core5                     core6                     core7                           idle-states         psci       cpu-retention-l           arm,idle-state                     (        9   2        J   _        Z  D        ø         cpu-retention-b           arm,idle-state                     (        9   -        J   Œ        Z  ä        ø         cpu-off-l             arm,idle-state                    (        9   7        J   ›        Z  H        ø         cpu-off-b             arm,idle-state                    (        9   2        J   È        Z  è        ø            l2-cache0             cache           k           w           „   @        –           Í            w        ø         l2-cache1             cache           k           w           „   @        –           Í            w        ø   	      l3-cache              cache           k           w            „   @        –            w        ø            dsu-pmu           arm,dsu-pmu         …                       �                                •fail          dmic-codec            dmic-codec          œ           ©   È      mt8195-sound            ¹           •okay              mediatek,mt8195_mt6359           7mt8395-evk          Ëdefault         Ù         ,  ãHeadphone Headphone L Headphone Headphone R         ñ      headphone-dai-link        
  ÿDL_SRC_BE      codec           	                hdmi-dai-link           ÿETDM3_OUT_BE       codec           	                   fixed-factor-clock-13m            fixed-factor-clock                                  '           1           <clk13m          ø   0      oscillator-26m            fixed-clock                     BŒº€        <clk26m          ø         oscillator-32k            fixed-clock                     B  €         <clk32k        performance-controller@11bc10             mediatek,cpufreq-hw               ¼            ½0               O           ø         opp-table-gpu             operating-points-v2          i        ø   ƒ   opp-390000000           t    >í€        { 	‰h      opp-410000000           t    p€        { 	¡Ò      opp-431000000           t    °‰À        { 	¡Ò      opp-473000000           t    1h@        { 	º<      opp-515000000           t    ²FÀ        { 	º<      opp-556000000           t    !#ã         { 	Ò¦      opp-598000000           t    #¤Á€        { 	ë      opp-640000000           t    &%          { 	ë      opp-670000000           t    'ïc€        { 
ä      opp-700000000           t    )¹'         { 
L¸      opp-730000000           t    +‚ê€        { 
}Œ      opp-760000000           t    -L®         { 
®`      opp-790000000           t    /q€        { 
ß4      opp-820000000           t    0à5         {       opp-850000000           t    2©ø€        { @Ü      opp-880000000           t    4s¼         { q°         pmu-a55           arm,cortex-a55-pmu                      …                  pmu-a78           arm,cortex-a78-pmu                      …                  psci              arm,psci-1.0            'smc       timer             arm,armv8-timer                   @  …                                             
             soc                      +             simple-bus           ‰        �                          interrupt-controller@c000000              arm,gic-v3          ›           ¬                        Ã                                             …      	               ø      ppi-partitions     interrupt-partition-0           Ø                    ø         interrupt-partition-1           Ø                    ø               syscon@10000000            mediatek,mt8195-topckgen syscon                                          ø         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                                          á           ø          syscon@10003000           mediatek,mt8195-pericfg syscon               0                           ø   L      pinctrl@10005000              mediatek,mt8195-pinctrl       €       P            Ñ             Ó             Ô             â             ë             ô              °              B  îiocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            ø                                 �         Ã        …       ë               ›           ø      audio-default-pins          ø      pins-cmd-dat          4     =  >  A  B  C  D  E  F  G  H  I  J  K         disp-pwm1-default-pins     pins1              h         edp-panel-12v-en-pins           ø   è   pins1              `          '         edp-panel-3v3-en-pins           ø   ç   pins1                        '         eth-default-pins            ø   H   pins-cc            U  V  W  X        3         pins-mdio              Y  Z         B      pins-power             [   \          '      pins-rxd               Q  R  S  T      pins-txd               M  N  O  P        3            eth-sleep-pins          ø   I   pins-cc            U   V   W   X       pins-mdio              Y   Z          O         ]      pins-rxd               Q   R   S   T       pins-txd               M   N   O   P          gpio-keys-pins     pins               j          j         B         hdmi-vreg-pins          ø   l   pins-pwr                        ]         hdmi-pins           ø   Õ   pins-hotplug                         w      pins-ddc               "  #        3   
      pins-cec               !         ]         i2c0-pins           ø   n   pins                 	        j   Ï        †  è         i2c1-pins           ø   o   pins               
          j   Ï        †  è         i2c2-pins           ø   r   pins                         j   Ï        3            i2c6-pins           ø   f   pins                          j         mmc0-default-pins           ø   Q   pins-clk               z        3           w   f      pins-cmd-dat          $     ~  }  |  {  w  v  u  t  y         B        3           j   e      pins-rst               x        3           j   e         mmc0-uhs-pins           ø   R   pins-clk               z        3           w   f      pins-cmd-dat          $     ~  }  |  {  w  v  u  t  y         B        3           j   e      pins-ds                    3           w   f      pins-rst               x        3           j   e         mmc1-default-pins           ø   U   pins-clk               o        3           w   f      pins-cmd-dat               n  p  q  r  s         B        3           j   e         mmc1-uhs-pins           ø   V   pins-clk               o        3           w   f      pins-cmd-dat               n  p  q  r  s         B        3           j   e         mt6360-pins         ø   g   pins                  €          B         j         dsi0-vreg-en-pins           ø   é   pins-pwr-en            /          ž         panel-default-pins          ø   º   pins-rst               l          '      pins-en            0          ž         pcie0-default-pins          ø   a   pins                            j         pcie0-idle-pins         ø   b   pins                         ]         ž         pcie1-default-pins          ø   d   pins                            j         disp-pwm0-pins          ø   ?   pins-disp-pwm              a         spi1-pins           ø   @   pins               ˆ  ‰  Š  ‹         ]         spi-pins            ø   C   pins               Œ  �  Ž  �         ]         touch-pins          ø   q   pins-irq               „          B         ]      pins-reset             …          '         u3-p0-vbus-default-pins         ø   M   pins-vbus              ?         B         uart0-pins          ø   :   pins               b  c         uart1-pins          ø   ;   pins               d  e  f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8195-power-controller                         +            ©           ø   3   power-domain@8                                  +            ©           ½      power-domain@9             	                             Ëmfg alt         ×                         +            ©           ½   !   power-domain@10            
        ©          power-domain@11                    ©          power-domain@12                    ©          power-domain@13                    ©          power-domain@14                    ©                power-domain@15                  Ø                           	      @      A      K      à   "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "           Ëvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           ×                         +            ©      power-domain@16                  8         â   #   $   #   %   #   &   #   '   #   (   #   )      D  Ëvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         ×                         +            ©      power-domain@17                           á   $      $           Ëvppsys1 vppsys1-0 vppsys1-1         ×            ©          power-domain@22                         %      %      %      %         $  Ëwepsys-0 wepsys-1 wepsys-2 wepsys-3         ×            ©          power-domain@23                        &            Ëvdec0-0         ×                         +            ©       power-domain@24                        '            Ëvdec1-0         ×            ©          power-domain@25                        (            Ëvdec2-0         ×            ©             power-domain@26                        )            Ëvenc0-larb          ×                         +            ©       power-domain@27                        *            Ëvenc1-larb          ×            ©             power-domain@18                            ã   +       +      +         &  Ëvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           ×                         +            ©      power-domain@19                    ×            ©          power-domain@20                    ×            ©          power-domain@21                           Q        Ëhdmi_tx         ©             power-domain@28                        ,       ,   
        Ëimg-0 img-1         ×                         +            ©      power-domain@29                    ©          power-domain@30                              ,      -           Ëipe ipe-0 ipe-1         ×            ©             power-domain@31                  (      .       .      .      .      .           Ëcam-0 cam-1 cam-2 cam-3 cam-4           ×                         +            ©      power-domain@32                     ©          power-domain@33            !        ©          power-domain@34            "        ©                   power-domain@0                      ×            ©          power-domain@1                     ×            ©          power-domain@2                     ©          power-domain@3                     ©          power-domain@4                            5      7        Ëcsi_rx_top csi_rx_top1          ©          power-domain@5                         /           Ëether           ©          power-domain@6                            X      n        Ëadsp adsp1                       +            ×            ©      power-domain@7                             g      "      n       2        Ëaudio audio1 audio2 audio3          ×            ©                   watchdog@10007000             mediatek,mt8195-wdt          é             p                á           ø   8      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                À                           ø         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer             p                …      	                   0      pwrap@10024000            mediatek,mt8195-pwrap syscon                @                îpwrap           …       ó                                     	  Ëspi wrap                  $              Ë   pmic              mediatek,mt6359          Ã        ›           (           9      Þ           ø      adc           mediatek,mt6359-auxadc          M         audio-codec           mediatek,mt6359-codec           _           s           ‡         regulators            mediatek,mt6359-regulator      buck_vs1            ›vs1         ª 5         Â !‘À        Ú             ö      buck_vgpu11         ›vgpu11          ª €        Â 7        
  ˆ        Ú   È                           ö      buck_vmodem         ›vmodem          ª €        Â Èà        
  *        Ú   È      buck_vpu            ›vpu         ª €        Â 7        
  ˆ        Ú   È                           ö      buck_vcore          ›vcore           ª €        Â Ö         
  ˆ        Ú   È                           ö        ø         buck_vs2            ›vs2         ª 5         Â j         Ú             ö      buck_vpa            ›vpa         ª ¡         Â 7±Ð        Ú  ,      buck_vproc2         ›vproc2          ª €        Â 7        
  L        Ú   È                        buck_vproc1         ›vproc1          ª €        Â 7        
  L        Ú   È                        buck_vcore_sshub            ›vcore_sshub         ª €        Â 7      buck_vgpu11_sshub           ›vgpu11_sshub            ª €        Â 7      ldo_vaud18          ›vaud18          ª w@        Â w@        Ú   ð         ö      ldo_vsim1           ›vsim1           ª ð         Â /M`      ldo_vibr            ›vibr            ª O€        Â 2Z         ø   s      ldo_vrf12           ›vrf12           ª Èà        Â Ö          ö      ldo_vusb            ›vusb            ª -ÆÀ        Â -ÆÀ        Ú  À         ö        ø   N      ldo_vsram_proc2         ›vsram_proc2         ª ¡         Â ½¶        
  L        Ú   ð         ö      ldo_vio18           ›vio18           ª ð         Â ýà        Ú  À         ö      ldo_vcamio          ›vcamio          ª ð         Â ýà         ö      ldo_vcn18           ›vcn18           ª w@        Â w@        Ú   ð      ldo_vfe28           ›vfe28           ª *¹€        Â *¹€        Ú   x      ldo_vcn13           ›vcn13           ª »         Â Ö       ldo_vcn33_1_bt          ›vcn33_1_bt          ª *¹€        Â 5gà      ldo_vcn33_1_wifi            ›vcn33_1_wifi            ª *¹€        Â 5gà      ldo_vaux18          ›vaux18          ª w@        Â w@        Ú   ð         ö      ldo_vsram_others            ›vsram_others            ª q°        Â q°        
  ˆ        Ú   ð        ø   !      ldo_vefuse          ›vefuse          ª ð         Â „€      ldo_vxo22           ›vxo22           ª w@        Â !‘À         ö      ldo_vrfck           ›vrfck           ª ã`        Â ð       ldo_vrfck_1         ›vrfck_1         ª ëÀ        Â j       ldo_vbif28          ›vbif28          ª *¹€        Â *¹€        Ú   ð      ldo_vio28           ›vio28           ª *¹€        Â 2Z          ö      ldo_vemc            ›vemc            ª ,@         Â 2Z       ldo_vemc_1          ›vemc_1          ª &%         Â 2Z         ø   S      ldo_vcn33_2_bt          ›vcn33_2_bt          ª 2Z         Â 2Z         ø   B      ldo_vcn33_2_wifi            ›vcn33_2_wifi            ª *¹€        Â 5gà      ldo_va12            ›va12            ª O€        Â Ö          ö      ldo_va09            ›va09            ª 5         Â O€      ldo_vrf18           ›vrf18           ª ð         Â žP      ldo_vsram_md          	  ›vsram_md            ª ¡         Â ½¶        
  *        Ú   ð      ldo_vufs            ›vufs            ª ð         Â ýà        ø   T      ldo_vm18            ›vm18            ª ð         Â ýà         ö      ldo_vbbck           ›vbbck           ª Èà        Â O€         ö      ldo_vsram_proc1         ›vsram_proc1         ª ¡         Â ½¶        
  L        Ú   ð         ö      ldo_vsim2           ›vsim2           ª ð         Â /M`      ldo_vsram_others_sshub          ›vsram_others_sshub          ª ¡         Â ½¶         rtc           mediatek,mt6358-rtc       keys              mediatek,mt6359-keys            7           P       power-key           c   t         r      home            c   f               spmi@10027000             mediatek,mt8195-spmi                 p            �                îpmif spmimst                                  E      (  Ëpmif_sys_ck pmif_tmr_ck spmimst_clk_mux               $              Ë                     +       pmic@6            mediatek,mt6315-regulator                     regulators     vbuck1          ›Vbcpu           ª “à        Â 7        Ú                              ö        ø   
            pmic@7            mediatek,mt6315-regulator                     regulators     vbuck1          ›Vgpu            ª TÐ        Â 8        Ú                             ø                  infra-iommu@10315000              mediatek,mt8195-iommu-infra             1P       P       P  …                                                                         €           ø   ^      mailbox@10320000              mediatek,mt8195-gce             2        @         …       â               �                           ø   ¦      mailbox@10330000              mediatek,mt8195-gce             3        @         …       ä               �                           ø   „      scp@10500000              mediatek,mt8195-scp       0      P             r             p        €         îsram cfg l1tcm          …      Î               •okay            ™   1        §mediatek/mt8195/scp.img         ø   …      clock-controller@10720000             mediatek,mt8195-scp_adsp                r                            ø   2      dsp@10803000              mediatek,mt8195-dsp              €0            „               	  îcfg sram          ,         X         n      Š   2          #      K  Ëadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          µ   3           Ãrx tx           Î   4   5        •okay            ™   6   7        ø         mailbox@10816000              mediatek,mt8195-adsp-mbox           �                �`                …      ¾               ø   4      mailbox@10817000              mediatek,mt8195-adsp-mbox           �                �p                …      ¿               ø   5      mt8195-afe-pcm@10890000           mediatek,mt8195-audio               ‰                 Õ           µ   3           …      6               ç   8         	  îaudiosys          ”                        Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d       2   2          ó  Ëclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          •okay            ™   9        ø         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                …       �                                	  Ëbaud bus            •okay            Ù   :        Ëdefault       serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                …       Ž                                	  Ëbaud bus            •okay            Ù   ;        Ëdefault       serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                …       �                                	  Ëbaud bus          	  •disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                …      Ó                                	  Ëbaud bus          	  •disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                …      Ô                                	  Ëbaud bus          	  •disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                …      Õ                                	  Ëbaud bus          	  •disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                                 Ëmain            M         	  •disabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                0                           ø   /      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  …       ¿                      ™                     Ëparent-clk sel-clk spi-clk        	  •disabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap              °                …       ©                               ç                ú   <   =      $  lvts-calib-data-1 lvts-calib-data-2                    ø   â      svs@1100bc00              mediatek,mt8195-svs              ¼                …       Ç                               Ëmain            ú   >   <      (  svs-calibration-data t-calibration-data         ç               îsvs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                à                …       Ë               µ   3           -                  *       0        Ëmain mm         •okay            Ëdefault         Ù   ?        ø   å      pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                ð                …                     -                  +       N        Ëmain mm       	  •disabled            ø   æ      spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 …       À                      ™             3        Ëparent-clk sel-clk spi-clk          •okay            Ù   @        Ëdefault         8            L      @      can@0             microchip,mcp2518fd                         A        U1-         9                 g   B        r   B         spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 …       Á                      ™             4        Ëparent-clk sel-clk spi-clk          •okay            Ù   C        Ëdefault         8          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                0                …       Â                      ™             5        Ëparent-clk sel-clk spi-clk        	  •disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                €                …       Ã                      ™             <        Ëparent-clk sel-clk spi-clk        	  •disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                �                …       Ä                      ™             =        Ëparent-clk sel-clk spi-clk        	  •disabled          spi@1101d000              mediatek,mt8195-spi-slave               Ð                …       Å                       R        Ëspi                             ˜      	  •disabled          spi@1101e000              mediatek,mt8195-spi-slave               à                …       Æ                       S        Ëspi                             ˜      	  •disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                      @         …      Ì               �macirq        .  Ëaxi apb mac_main ptp_ref rmii_internal mac_cg         0      /       /         R      S      T   /                 R      S      T              Â      Ã      Ä        µ   3           ‘            ¢   D        ²   E        Å   F        Ø           ã           î            •okay            ûrgmii-rxid             G              ]                  '  '        4  î         I        Ëdefault sleep           Ù   H        Z   I   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916                       ø   G         stmmac-axi-config           d           t           „                                 ø   D      rx-queues-config            Ž            ¤        ø   E   queue0           µ        È          queue1           µ        È          queue2           µ        È          queue3           µ        È             tx-queues-config            à            ö        ø   F   queue0          	            µ        	          queue1          	            µ        	         queue2          	            µ        	         queue3          	            µ        	               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                       -ÿ     >              	  îmac ippc            ‰                     ?                      +           …       €                       /      í       B        Ësys_ck ref_ck mcu_ck            	"   J      K            r        	'   L      g        •okay            	>otg         Ëdefault         Ù   M         	F        	V   N   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 îmac         …       �                     ,      -              –      –      $          /      í                B      $  Ësys_ck ref_ck mcu_ck dma_ck xhci_ck         •okay          ports                        +       port@0                 endpoint            	d   O        ø   i         port@1                endpoint            	d   P        ø   j               mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              #             õ                 …       ƒ                                            Ësource hclk source_cg           •okay            Ëdefault state_uhs           Ù   Q        Z   R        	t           YëÂ          	~         	�         	Ÿ         	®         	¿         	Ç        	Í L        	Ü   S        	è   T         	õ      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              $             Ç                 …       ‡                                    $        Ësource hclk source_cg                               ¿        •okay            Ëdefault state_uhs           Ù   U        Z   V        	t           YëÂ          
         
         
!         
/         	¿        	Ü   W        	è   X         	õ      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              %             æ                 …       ˆ                                     I        Ësource hclk source_cg                                ¿      	  •disabled          ufshci@11270000           mediatek,mt8195-ufshci              '        #         …       ‰               	"   Y      @          ?       @       A       6       7       8       Z       ]      X  Ëufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  
6                                                                         
D      	  •disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                '€                …       ª                               ç               ú   <   =      $  lvts-calib-data-1 lvts-calib-data-2                    ø   Ù      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci               )             )>              	  îmac ippc            …                     	"   Z      [                 .      /              –      –      $      /         ï            /         $  Ësys_ck ref_ck mcu_ck dma_ck xhci_ck         	'   L      h         r        •okay            	V   N      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               *       -ÿ    *>              	  îmac ippc            ‰            *        ?                      +           …                           0              –            /         ñ   /           Ësys_ck ref_ck mcu_ck            	"   \            r        	'   L      i        •okay            	V   N   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 îmac         …                           1              –            /           Ësys_ck          •okay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               +       -ÿ    +>              	  îmac ippc            ‰            +        ?                      +           …                           2              –            /         ó   /   	        Ësys_ck ref_ck mcu_ck            	"   ]            r        	'   L      j        •okay            	V   N   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 îmac         …                           3              –            /   	        Ësys_ck          •okay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +               /        @       	  îpcie-mac            …                     
]       ÿ      8  ‰�                           ‚                       à          
g       ^              
q          0          V       #       &       +       K   /         /  Ëpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                G                      	"   _      	  
€pcie-phy            µ   3            ›           
Š                     `  
�                  `                      `                     `                     `           •okay            Ëdefault idle            Ù   a        Z   b   interrupt-controller             Ã                     ›           ø   `         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +               /€       @       	  îpcie-mac            …                     
]       ÿ      8  ‰�       $       $           ‚       $       $       à          
g       ^              
q          (          W          X          Q   /         /  Ëpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                H                      	"   [         	  
€pcie-phy            µ   3           ›           
Š                     `  
�                  c                      c                     c                     c         	  •disabled            Ëdefault         Ù   d   interrupt-controller             Ã                     ›           ø   c         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor             2À                …      9                      o   /      /           Ëspi sf axi                       +          	  •disabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                Á                              +      usb3-tx-imp@184,1             „           
«               ø   z      usb3-rx-imp@184,2             „           
«              ø   y      usb3-intr@185             …           
«              ø   x      usb3-tx-imp@186,1             †           
«               ø   w      usb3-rx-imp@186,2             †           
«              ø   v      usb3-intr@187             ‡           
«              ø   u      usb2-intr-p0@188,1            ˆ           
«             usb2-intr-p1@188,2            ˆ           
«            usb2-intr-p2@189,1            ‰           
«            usb2-intr-p3@189,2            ‰           
«            pciephy-rx-ln1@190,1              �           
«               ø   �      pciephy-tx-ln1-nmos@190,2             �           
«              ø   €      pciephy-tx-ln1-pmos@191,1             ‘           
«               ø         pciephy-rx-ln0@191,2              ‘           
«              ø   ~      pciephy-tx-ln0-nmos@192,1             ’           
«               ø   }      pciephy-tx-ln0-pmos@192,2             ’           
«              ø   |      pciephy-glb-intr@193              “           
«               ø   {      dp-data@1ac           ¬           ø   Ø      lvts1-calib@1bc           ¼           ø   <      lvts2-calib@1d0           Ð   8        ø   =      svs-calib@580             €   d        ø   >      socinfo-data1@7a0                          t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ‰        Ä             •okay       usb-phy@0                                 ò        Ëref         
°           ø   \         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ‰        Å             •okay       usb-phy@0                                 ô        Ëref         
°           ø   ]         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             È                             <mipi_tx0_pll                        
°            •okay            ø   ¶      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             É                             <mipi_tx1_pll                        
°          	  •disabled            ø   ¾      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        …       š               '               e           ;      	  Ëmain dma                         +          	  •disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð            "        €        …       ›               '               e          ;      	  Ëmain dma                         +            •okay            B €        Ù   f        Ëdefault    pmic@34           mediatek,mt6360            4                    …   €           �IRQB             Ã        ›           Ù   g   charger           mediatek,mt6360-chg         
» Ý@    usb-otg-vbus-regulator          ›usb-otg-vbus            ª C…(        Â Xáè         regulator             mediatek,mt6360-regulator           
Ô   h   buck1         	  ›emi_vdd2            ª “à        Â Ö                            ö      buck2         	  ›emi_vddq            ª “à        Â Ö                            ö        ø   h      ldo1          	  ›tp1_p3v0            ª 2Z         Â 2Z                         ö        ø   p      ldo2            ›panel1_p1v8         ª w@        Â w@                       ø   ê      ldo3            ›vmc_pmu         ª O€        Â 6î€                       ø   X      ldo5          	  ›vmch_pmu            ª )2à        Â 6î€                       ø   W      ldo6            ›mt6360_ldo1         ª ¡         Â                        ldo7            ›emi_vmddr_en            ª ¡         Â                           ö         tcpc              mediatek,mt6360-tcpc            9                 �PD_IRQB    connector             usb-c-connector         
äUSB-C           
êdual            
ô ˜–€        dual            sink             "�d        ,"�È        6   altmodes       displayport         Bÿ          G  F         ports                        +       port@0                 endpoint            	d   i        ø   O         port@1                endpoint            	d   j        ø   P         port@2                endpoint            	d   k        ø   t                        i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        …       œ               '               e          ;      	  Ëmain dma                         +          	  •disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s              Ð0                           ø   e      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy                Õð                        P                           Ëpll_ref 26m pll1 pll2           <hdmi_txpll                      
°            K   
        Z           •okay            Ëdefault         Ù   l        ø   Ô      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             " €       €        …       �               '               m           ;      	  Ëmain dma                         +            •okay            B €        Ù   n        Ëdefault       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à            "        €        …       “               '               m          ;      	  Ëmain dma                         +            •okay            B €        Ù   o        Ëdefault    touchscreen@5d            goodix,gt9271              ]        9      „           l      „            v      …            ‚   p        Ëdefault         Ù   q         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             "€       €        …       –               '               m          ;      	  Ëmain dma                         +            •okay            B €        Ù   r        Ëdefault    typec-mux@48              ite,it5205             H        �   s         ›         §        •okay       port       endpoint            	d   t        ø   k               i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à0            "€       €        …       ˜               '               m          ;      	  Ëmain dma                         +          	  •disabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à@            "        €        …       ™               '               m          ;      	  Ëmain dma                         +          	  •disabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w              àP                           ø   m      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ‰        ã             µ   3           •okay       usb-phy@0                                 ð           Ëref da_ref          
°           ø   Z      usb-phy@700                                    ð        Ëref da_ref          ú   u   v   w        intr rx_imp tx_imp          
°            º        ø   [         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ‰        ä             •okay       usb-phy@0                                 î           Ëref da_ref          
°           ø   J      usb-phy@700                                    î        Ëref da_ref          ú   x   y   z        intr rx_imp tx_imp          
°           ø   K         phy@11e80000              mediatek,mt8195-pcie-phy                è                 îsif         ú   {   |   }   ~      €   �      G  glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          µ   3           
°            •okay            ø   _      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy               ú        À                      
  Ëunipro mp           
°          	  •disabled            ø   Y      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                        @             ‚          0  …      �             Œ             ‹               �job mmu gpu         Î   ƒ      (  µ   3   
   3      3      3      3           âcore0 core1 core2 core3 core4           •okay            õ         clock-controller@13fbf000             mediatek,mt8195-mfgcfg              ûð                           ø   ‚      syscon@14000000           mediatek,mt8195-vppsys0 syscon                                              „                   ø   "      dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                   „                                -   …        µ   3           :   †   €            "         <  Î   „         „         „         „         „              A         display@14002000              mediatek,mt8195-mdp3-fg                                  „                       "          display@14003000              mediatek,mt8195-mdp3-stitch              0                   „      0                "         display@14004000              mediatek,mt8195-mdp3-hdr                 @                   „      @                "   "      display@14005000              mediatek,mt8195-mdp3-aal                 P                …      F                  „      P                "   
        µ   3         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                   „      `                %            "         display@14007000              mediatek,mt8195-mdp3-tdshp               p                   „      p                "   #      display@14008000              mediatek,mt8195-mdp3-color               €                …      I                  „      €                "   $        µ   3         display@14009000              mediatek,mt8195-mdp3-ovl                 �                …      J                  „      �                "   %        µ   3           :   †   ‚      display@1400a000              mediatek,mt8195-mdp3-padding                                     „                       "           µ   3         display@1400b000              mediatek,mt8195-mdp3-tcc                 °                   „      °                "         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              À                   „      À                +            "           :   †   ƒ        µ   3           A         mutex@1400f000            mediatek,mt8195-vpp-mutex                ð                …      P                  „      ð                "           µ   3         smi@14010000              mediatek,mt8195-smi-sub-common                                   "      "      "           Ëapb smi gals0           L   ‡        µ   3           ø   ˆ      smi@14011000              mediatek,mt8195-smi-sub-common                                  "      "      "           Ëapb smi gals0           L   ‡        µ   3           ø   ¥      smi@14012000              mediatek,mt8195-smi-common-vpp                                    "      "      "      "           Ëapb smi gals0 gals1         µ   3           ø   ‡      larb@14013000             mediatek,mt8195-smi-larb                0                Y           L   ˆ            "      "           Ëapb smi         µ   3           ø   ‹      iommu@14018000            mediatek,mt8195-iommu-vpp               €              8  j   ‰   Š   ‹   Œ   �   Ž   �   �   ‘   ’   “   ”   •   –        …      R                   "           Ëbclk            €           µ   3           ø   †      clock-controller@14e00000             mediatek,mt8195-wpesys              à                            ø   %      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0             à                          clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1             à0                         larb@14e04000             mediatek,mt8195-smi-larb                à@                Y           L   —            %      %           Ëapb smi         µ   3           ø   Ã      larb@14e05000             mediatek,mt8195-smi-larb                àP                Y           L   ‡            %      %      "           Ëapb smi gals            µ   3           ø   �      syscon@14f00000           mediatek,mt8195-vppsys1 syscon              ð                               „   	               ø   $      mutex@14f01000            mediatek,mt8195-vpp-mutex               ð                …      {                  „   	                  $   '        µ   3         larb@14f02000             mediatek,mt8195-smi-larb                ð                 Y           L   —            $      $      "           Ëapb smi gals            µ   3           ø   Â      larb@14f03000             mediatek,mt8195-smi-larb                ð0                Y           L   ˆ            $      $      "           Ëapb smi gals            µ   3           ø   Œ      display@14f06000              mediatek,mt8195-mdp3-split              ð`                   „   	  `                $      $   +   $   ,        µ   3         display@14f07000              mediatek,mt8195-mdp3-tcc                ðp                   „   	  p                $         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma               ð€                   „   	  €              „  ¨            $           :   ˜            µ   3           A         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma               ð�                   „   	  �              …  ©            $   
        :   ˜   ¤        µ   3           A         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma               ð                    „   	                 †  ª            $           :   †   À        µ   3           A         display@14f0b000              mediatek,mt8195-mdp3-fg             ð°                   „   	  °                $   	      display@14f0c000              mediatek,mt8195-mdp3-fg             ðÀ                   „   	  À                $         display@14f0d000              mediatek,mt8195-mdp3-fg             ðÐ                   „   	  Ð                $         display@14f0e000              mediatek,mt8195-mdp3-hdr                ðà                   „   	  à                $         display@14f0f000              mediatek,mt8195-mdp3-hdr                ðð                   „   	  ð                $         display@14f10000              mediatek,mt8195-mdp3-hdr                ñ                    „   
                   $          display@14f11000              mediatek,mt8195-mdp3-aal                ñ                …      i                  „   
                  $           µ   3         display@14f12000              mediatek,mt8195-mdp3-aal                ñ                 …      j                  „   
                   $           µ   3         display@14f13000              mediatek,mt8195-mdp3-aal                ñ0                …      k                  „   
  0                $   !        µ   3         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ@                   „   
  @              �  ¯            $         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñP                   „   
  P              ‘  °            $   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ`                   „   
  `              ’  ±            $   %      display@14f17000              mediatek,mt8195-mdp3-tdshp              ñp                   „   
  p                $         display@14f18000              mediatek,mt8195-mdp3-tdshp              ñ€                   „   
  €                $   (      display@14f19000              mediatek,mt8195-mdp3-tdshp              ñ�                   „   
  �                $   )      display@14f1a000              mediatek,mt8195-mdp3-merge              ñ                    „   
                   $           µ   3         display@14f1b000              mediatek,mt8195-mdp3-merge              ñ°                   „   
  °                $           µ   3         display@14f1c000              mediatek,mt8195-mdp3-color              ñÀ                …      t                  „   
  À                $           µ   3         display@14f1d000              mediatek,mt8195-mdp3-color              ñÐ                   „   
  Ð            …      u                   $           µ   3         display@14f1e000              mediatek,mt8195-mdp3-color              ñà                …      v                  „   
  à                $           µ   3         display@14f1f000              mediatek,mt8195-mdp3-ovl                ñð                …      w                  „   
  ð                $            µ   3           :   ˜   ¢      display@14f20000              mediatek,mt8195-mdp3-padding                ò                    „                      $           µ   3         display@14f21000              mediatek,mt8195-mdp3-padding                ò                   „                     $           µ   3         display@14f22000              mediatek,mt8195-mdp3-padding                ò                    „                      $           µ   3         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò0                   „     0              Ÿ  «            $           :   ˜   £        µ   3           A         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò@                   „     @                 ¬            $           :   ˜   ¦        µ   3           A         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             òP                   „     P              ¡  ­            $           :   †   Â        µ   3           A         clock-controller@15000000             mediatek,mt8195-imgsys                                           ø   ,      larb@15001000             mediatek,mt8195-smi-larb                                 Y   	        L   ™            ,       ,       ,   
        Ëapb smi gals            µ   3           ø   Ä      smi@15002000              mediatek,mt8195-smi-sub-common                                    ,      ,      "           Ëapb smi gals0           L   ‡        µ   3           ø   œ      smi@15003000              mediatek,mt8195-smi-sub-common               0                    ,       ,       ,   
        Ëapb smi gals0           L   —        µ   3           ø   ™      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                                         ø   š      larb@15120000             mediatek,mt8195-smi-larb                                 Y   
        L   ™            ,      š            Ëapb smi         µ   3           ø   Å      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                                        clock-controller@15220000             mediatek,mt8195-imgsys1_wpe             "                            ø   ›      larb@15230000             mediatek,mt8195-smi-larb                #                 Y           L   ™            ,      ›            Ëapb smi         µ   3           ø   Æ      clock-controller@15330000             mediatek,mt8195-ipesys              3                            ø   -      larb@15340000             mediatek,mt8195-smi-larb                4                 Y           L   œ            -      -           Ëapb smi         µ   3           ø   Ž      clock-controller@16000000             mediatek,mt8195-camsys                                           ø   .      larb@16001000             mediatek,mt8195-smi-larb                                 Y           L   �            .       .       .           Ëapb smi gals            µ   3           ø   Ç      larb@16002000             mediatek,mt8195-smi-larb                                  Y           L   ž            .      .           Ëapb smi         µ   3           ø   �      smi@16004000              mediatek,mt8195-smi-sub-common               @                    .       .       .           Ëapb smi gals0           L   —        µ   3           ø   �      smi@16005000              mediatek,mt8195-smi-sub-common               P                    .      .      "           Ëapb smi gals0           L   ‡        µ   3           ø   ž      larb@16012000             mediatek,mt8195-smi-larb                                 Y           L   ž            Ÿ       Ÿ            Ëapb smi         µ   3            ø   �      larb@16013000             mediatek,mt8195-smi-larb                0                Y           L   �                                 Ëapb smi         µ   3            ø   È      larb@16014000             mediatek,mt8195-smi-larb                @                Y           L   ž            ¡       ¡            Ëapb smi         µ   3   !        ø   –      larb@16015000             mediatek,mt8195-smi-larb                P                Y           L   �            ¢       ¢            Ëapb smi         µ   3   !        ø   Í      clock-controller@1604f000             mediatek,mt8195-camsys_rawa             ð                           ø   Ÿ      clock-controller@1606f000             mediatek,mt8195-camsys_yuva             ð                           ø          clock-controller@1608f000             mediatek,mt8195-camsys_rawb             ð                           ø   ¡      clock-controller@160af000             mediatek,mt8195-camsys_yuvb             
ð                           ø   ¢      clock-controller@16140000             mediatek,mt8195-camsys_mraw                                         ø   £      larb@16141000             mediatek,mt8195-smi-larb                                Y           L   �            .       £       .           Ëapb smi gals            µ   3   "        ø   Ì      larb@16142000             mediatek,mt8195-smi-larb                                 Y           L   ž            £       £            Ëapb smi         µ   3   "        ø   •      clock-controller@17200000             mediatek,mt8195-ccusys                                           ø   ¤      larb@17201000             mediatek,mt8195-smi-larb                                 Y           L   ž            ¤       ¤            Ëapb smi         µ   3           ø   ‘      video-codec@18000000              mediatek,mt8195-vcodec-dec          -   …        :   ˜                        +                               @                ‰                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                :   †  à   †  á                A   &      &         �        Ësel vdec lat top                  A              �        µ   3         video-codec@10000             mediatek,mtk-vcodec-lat                               …      Ä             0  :   ˜      ˜     ˜     ˜     ˜     ˜                  A   &      &         �        Ësel vdec lat top                  A              �        µ   3         video-codec@25000             mediatek,mtk-vcodec-core                 P                …      Ã             P  :   ˜      ˜  ¡   ˜  ¢   ˜  £   ˜  ¤   ˜  ¥   ˜  ¦   ˜  §   ˜  ¨   ˜  ©                A   '      '         �        Ësel vdec lat top                  A              �        µ   3            larb@1800d000             mediatek,mt8195-smi-larb                 Ð                Y           L   —            &       &            Ëapb smi         µ   3           ø   Ë      larb@1800e000             mediatek,mt8195-smi-larb                 à                Y           L   ¥            "      &            Ëapb smi         µ   3           ø   ”      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc              ð                           ø   &      larb@1802e000             mediatek,mt8195-smi-larb                à                Y           L   —            '       '            Ëapb smi         µ   3           ø   Ê      clock-controller@1802f000             mediatek,mt8195-vdecsys             ð                           ø   '      larb@1803e000             mediatek,mt8195-smi-larb                à                Y           L   ¥            "      (            Ëapb smi         µ   3           ø   “      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1               ð                           ø   (      clock-controller@190f3000             mediatek,mt8195-apusys_pll              0                         clock-controller@1a000000             mediatek,mt8195-vencsys                                          ø   )      larb@1a010000             mediatek,mt8195-smi-larb                                 Y           L   —            )      )           Ëapb smi         µ   3           ø   É      video-codec@1a020000              mediatek,mt8195-vcodec-enc                             H  :   ˜  `   ˜  a   ˜  b   ˜  c   ˜  d   ˜  v   ˜  w   ˜  x   ˜  y        …      U               -   …            )         	  Ëvenc_sel                  @              �        µ   3                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec          µ   3         0  :   ˜  m   ˜  n   ˜  r   ˜  s   ˜  t   ˜  u                     +         0  ‰                                            jpgdec@0,0            mediatek,mt8195-jpgdec-hw                                0  :   ˜  m   ˜  n   ˜  r   ˜  s   ˜  t   ˜  u        …      W                   )           Ëjpgdec          µ   3         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw                               0  :   ˜  m   ˜  n   ˜  r   ˜  s   ˜  t   ˜  u        …      X                   )           Ëjpgdec          µ   3         jpgdec@1,0            mediatek,mt8195-jpgdec-hw                               0  :   †  �   †  Ž   †  ’   †  “   †  ”   †  •        …      \                   *           Ëjpgdec          µ   3            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                            ø   *      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                 Î   ¦                             ¦                  ø   #   port                         +       endpoint@0                      	d   §        ø   ¨            jpeg-encoder@1a030000             mediatek,mt8195-jpgenc          µ   3            :   †  ‡   †  ˆ   †  ‰   †  Œ                     +         0  ‰                                            jpgenc@0,0            mediatek,mt8195-jpgenc-hw                                   :   ˜  g   ˜  h   ˜  i   ˜  l        …      V                   )           Ëjpgenc          µ   3         jpgenc@1,0            mediatek,mt8195-jpgenc-hw                                  :   †  ‡   †  ˆ   †  ‰   †  Œ        …      [                   *           Ëjpgenc          µ   3            larb@1b010000             mediatek,mt8195-smi-larb                                 Y           L   ‡            *      *      "            Ëapb smi gals            µ   3           ø   ’      ovl@1c000000              mediatek,mt8195-disp-ovl                                  …      |               µ   3               #            :   ˜              ¦             ports                        +       port@0                 endpoint            	d   ¨        ø   §         port@1                endpoint            	d   ©        ø   ª               rdma@1c002000             mediatek,mt8195-disp-rdma                                 …      ~               µ   3               #           :   ˜               ¦             ports                        +       port@0                 endpoint            	d   ª        ø   ©         port@1                endpoint            	d   «        ø   ¬               color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                0                …                     µ   3               #              ¦     0       ports                        +       port@0                 endpoint            	d   ¬        ø   «         port@1                endpoint            	d   ­        ø   ®               ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                @                …      €               µ   3               #              ¦     @       ports                        +       port@0                 endpoint            	d   ®        ø   ­         port@1                endpoint            	d   ¯        ø   °               aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                P                …      �               µ   3               #              ¦     P       ports                        +       port@0                 endpoint            	d   °        ø   ¯         port@1                endpoint            	d   ±        ø   ²               gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                `                …      ‚               µ   3               #              ¦     `       ports                        +       port@0                 endpoint            	d   ²        ø   ±         port@1                endpoint            	d   ³        ø   ´               dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither              p                …      ƒ               µ   3               #   	           ¦     p       ports                        +       port@0                 endpoint            	d   ´        ø   ³         port@1                endpoint            	d   µ        ø   ¼               dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi              €                …      „               µ   3               #      #   *   ¶        Ëengine digital hs           	"   ¶        
€dphy            •okay                         +       panel@0       #    startek,kd070fhfid078 himax,hx8279                      y   ·        ƒ      0            v      l            �   ¸        g   ¹        Ëdefault         Ù   º   port       endpoint            	d   »        ø   ½            ports                        +       port@0                 endpoint            	d   ¼        ø   µ         port@1                endpoint            	d   ½        ø   »               dsc@1c009000              mediatek,mt8195-disp-dsc                 �                …      …               µ   3               #              ¦     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              …      Ž               µ   3               #      #   +   ¾        Ëengine digital hs           	"   ¾        
€dphy          	  •disabled          merge@1c014000            mediatek,mt8195-disp-merge              @                …      �               µ   3               #              ¦     @          dp-intf@1c015000              mediatek,mt8195-dp-intf             P                …      ‘               µ   3               #   ,   #                 Ëpixel engine pll          	  •disabled          mutex@1c016000            mediatek,mt8195-disp-mutex              `                …      ’               µ   3               #              ¦     `              U      larb@1c018000             mediatek,mt8195-smi-larb                €                Y            L   —            #   (   #   (   "           Ëapb smi gals            µ   3           ø   À      larb@1c019000             mediatek,mt8195-smi-larb                �                Y           L   ‡            #   (   "       "           Ëapb smi gals            µ   3           ø   ‰      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                               Î   ¦                 ¦                             á           ø   +   port                         +       endpoint@1                     	d   ¿        ø   Ò            smi@1c01b000              mediatek,mt8195-smi-common-vdo              °                     #   %   #   &   #   )   #   $        Ëapb smi gals0 gals1         µ   3           ø   —      iommu@1c01f000            mediatek,mt8195-iommu-vdo               ð              8  j   À   Á   Â   Ã   Ä   Å   Æ   Ç   È   É   Ê   Ë   Ì   Í        …      �               €               #   '        Ëbclk            µ   3           ø   ˜      mutex@1c101000            mediatek,mt8195-disp-mutex                              …      î               µ   3               +              ¦                   À      larb@1c102000             mediatek,mt8195-smi-larb                                 Y           L   —            +       +       +           Ëapb smi gals            µ   3           ø   Á      larb@1c103000             mediatek,mt8195-smi-larb                0                Y           L   ‡            +      +      "            Ëapb smi gals            µ   3           ø   Š      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma               @                …      ï                   +           µ   3           :   ˜   @           ¦     @            A         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma               P                …      ð                   +           µ   3           :   †   `           ¦     P            A         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma               `                …      ñ                   +           µ   3           :   ˜   A           ¦     `            A         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma               p                …      ò                   +           µ   3           :   †   a           ¦     p            A         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma               €                …      ó                   +           µ   3           :   ˜   B           ¦     €            A         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma               �                …      ô                   +           µ   3           :   †   b           ¦     �            A         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma                                …      õ                   +           µ   3           :   ˜   C           ¦                  A         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma               °                …      ö                   +           µ   3           :   †   c           ¦     °            A         vpp-merge@1c10c000            mediatek,mt8195-disp-merge              À                …      ÷                   +   	   +           Ëmerge merge_async           µ   3              ¦     À             �        ç   +         vpp-merge@1c10d000            mediatek,mt8195-disp-merge              Ð                …      ø                   +   
   +           Ëmerge merge_async           µ   3              ¦     Ð             �        ç   +         vpp-merge@1c10e000            mediatek,mt8195-disp-merge              à                …      ù                   +      +           Ëmerge merge_async           µ   3              ¦     à             �        ç   +         vpp-merge@1c10f000            mediatek,mt8195-disp-merge              ð                …      ú                   +      +           Ëmerge merge_async           µ   3              ¦     ð             �        ç   +         vpp-merge@1c110000            mediatek,mt8195-disp-merge                               …      û                   +      +           Ëmerge merge_async           µ   3              ¦                   ±        ç   +      ports                        +       port@0                       +                   endpoint@1                     	d   Î        ø   Ó         port@1                       +                  endpoint@1                     	d   Ï        ø   Ð               dpi@1c112000              mediatek,mt8195-dpi                                  +   -   +      +   2        Ëpixel engine pll            …                      µ   3           ç   +           •okay       ports                        +       port@0                 endpoint            	d   Ð        ø   Ï         port@1                endpoint            	d   Ñ        ø   Ö               dp-intf@1c113000              mediatek,mt8195-dp-intf             0                …                     µ   3               +   /   +                 Ëpixel engine pll          	  •disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p      @            P            p            �                         °            À              4  îmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p     ¦     @       ¦     P       ¦     p       ¦     �       ¦             ¦     °       ¦     À          h      +   %   +       +   #   +   !   +   $   +   "   +   1   +   &   +   '   +   (   +   )   +   *            ƒ  Ëmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          µ   3           :   †   d   †   e        …                   (  ç   +   3   +   4   +   5   +   6   +   7      E  îvdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async       ports                        +       port@0                       +                   endpoint@1                     	d   Ò        ø   ¿         port@1                       +                  endpoint@1                     	d   Ó        ø   Î               hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx         (               0                         Q      L      M   $   ,        Ëbus hdcp hdcp24m hdmi-split               L              “        …      ¥               µ   3           	"   Ô        
€hdmi            •okay            Ëdefault         Ù   Õ        ø      i2c           mediatek,mt8195-hdmi-ddc                        ø   ã      ports                        +       port@0                 endpoint            	d   Ö        ø   Ñ         port@1                endpoint            	d   ×        ø   ä               edp-tx@1c500000           mediatek,mt8195-edp-tx              P        €         ú   Ø        dp_calibration_data         µ   3           …      ¤               È  ¤      	  •disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx               `        €         ú   Ø        dp_calibration_data         µ   3           …      Ê               È  ¤      	  •disabled             thermal-zones      cpu0-thermal            Ù  è        ç   ú        ý   Ù      trips      trip-alert           L          Ð        passive         ø   Ú      trip-crit            †           Ð      	  critical             cooling-maps       map0            $   Ú      0  )   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            Ù  è        ç   ú        ý   Ù      trips      trip-alert           L          Ð        passive         ø   Û      trip-crit            †           Ð      	  critical             cooling-maps       map0            $   Û      0  )   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            Ù  è        ç   ú        ý   Ù      trips      trip-alert           L          Ð        passive         ø   Ü      trip-crit            †           Ð      	  critical             cooling-maps       map0            $   Ü      0  )   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            Ù  è        ç   ú        ý   Ù      trips      trip-alert           L          Ð        passive         ø   Ý      trip-crit            †           Ð      	  critical             cooling-maps       map0            $   Ý      0  )   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            Ù  è        ç   ú        ý   Ù       trips      trip-alert           L          Ð        passive         ø   Þ      trip-crit            †           Ð      	  critical             cooling-maps       map0            $   Þ      0  )   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            Ù  è        ç   ú        ý   Ù      trips      trip-alert           L          Ð        passive         ø   ß      trip-crit            †           Ð      	  critical             cooling-maps       map0            $   ß      0  )   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            Ù  è        ç   ú        ý   Ù      trips      trip-alert           L          Ð        passive         ø   à      trip-crit            †           Ð      	  critical             cooling-maps       map0            $   à      0  )   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            Ù  è        ç   ú        ý   Ù      trips      trip-alert           L          Ð        passive         ø   á      trip-crit            †           Ð      	  critical             cooling-maps       map0            $   á      0  )   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            Ù  è        ç   ú        ý   â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                vpu1-thermal            Ù  è        ç   ú        ý   â   	   trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                gpu-thermal         Ù  è        ç   ú        ý   â   
   trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                gpu1-thermal            Ù  è        ç   ú        ý   â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                vdec-thermal            Ù  è        ç   ú        ý   â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                img-thermal         Ù  è        ç   ú        ý   â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                infra-thermal           Ù  è        ç   ú        ý   â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                cam0-thermal            Ù  è        ç   ú        ý   â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                cam1-thermal            Ù  è        ç   ú        ý   â      trips      trip-alert           L          Ð        passive       trip-crit            †           Ð      	  critical                   chosen          8serial0:921600n8          connector             hdmi-connector          
ähdmi            a           D   ã        P   Ô   port       endpoint            	d   ä        ø   ×            firmware       optee             linaro,optee-tz         'smc          memory@40000000         memory              @                reserved-memory                      +            ‰   optee@43200000           `            C        À        memory@50000000           shared-dma-pool             P       �           `        ø   1      memory@53000000           shared-dma-pool             S       @        memory@54600000          `            T`                memory@60000000           shared-dma-pool             `        ð           `        ø   7      memory@60f00000           shared-dma-pool             `ð                  `        ø   9      memory@61000000           shared-dma-pool             a                   `        ø   6      memory@62000000           shared-dma-pool             b       @           backlight-lcm0            pwm-backlight           g      ÿ        y  @        ’  ÿ        ©   å     ¡         ø   ·      backlight-lcd1            pwm-backlight           ©   æ     ¡         ƒ      .            g      ÿ        ’  ÿ        y  @      	  •disabled          can-clk           fixed-clock                     B1-         <can-clk         ø   A      regulator-0           regulator-fixed         ›edp_panel_3v3           ª 2Z         Â 2Z          ®                          Ëdefault         Ù   ç      regulator-1           regulator-fixed         ›edp_backlight_12v           ª ·         Â ·          ®              `            Ëdefault         Ù   è      gpio-keys         
    gpio-keys      button-volume-up             r        Á   d        O      j         
  
ävolume_up           Ó   s         regulator-vio18-lcm0              regulator-fixed         ›vio18_lcm0           ®              /            Ëdefault         Ù   é        Þ   ê        ø   ¸      regulator-vsys-lcm0           regulator-fixed       
  ›vsys_lcm0            ö         é        Þ   p        ø   ¹      regulator-2           regulator-fixed       	  ›wifi_3v3            ª 2Z         Â 2Z               ‡             ®         ö         	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 ethernet0 mmc0 mmc1 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform pinctrl-names pinctrl-0 audio-routing mediatek,adsp link-name sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux output-high drive-strength input-enable input-disable bias-disable bias-pull-up bias-pull-down drive-strength-microamp output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells mediatek,mic-type-0 mediatek,mic-type-1 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select cs-gpios spi-max-frequency vdd-supply xceiver-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us mediatek,tx-delay-ps mediatek,mac-wol pinctrl-1 snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup dr_mode usb-role-switch vusb33-supply remote-endpoint bus-width cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc freq-table-hz mediatek,ufs-disable-mcq bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply label data-role op-sink-microwatt power-role try-power-role source-pdos sink-pdos pd-revision svid vdo mediatek,ibias mediatek,ibias_up irq-gpios reset-gpios AVDD28-supply vcc-supply mode-switch orientation-switch mediatek,force-mode operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs backlight enable-gpios iovcc-supply mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path ddc-i2c-bus hdmi-pwr-supply no-map brightness-levels default-brightness-level num-interpolated-steps pwms enable-active-high debounce-interval linux,code vin-supply regulator-boot-on 