Ðþí Ù%   8 ¹˜   (            � ¹`                             .    radxa,nio-12l mediatek,mt8395 mediatek,mt8195                                    +            7Radxa NIO 12L         	   =embedded       aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/dpi@1c112000            a/soc/mailbox@10320000            f/soc/mailbox@10330000            k/soc/hdmi-tx@1c300000            q/soc/hdr-engine@1c114000             x/soc/mutex@1c016000          /soc/mutex@1c101000          †/soc/vpp-merge@1c10c000          �/soc/vpp-merge@1c10d000          ”/soc/vpp-merge@1c10e000          ›/soc/vpp-merge@1c10f000          ¢/soc/vpp-merge@1c110000          ©/soc/dma-controller@1c104000             ´/soc/dma-controller@1c105000             ¿/soc/dma-controller@1c106000             Ê/soc/dma-controller@1c107000             Õ/soc/dma-controller@1c108000             à/soc/dma-controller@1c109000             ë/soc/dma-controller@1c10a000             ö/soc/dma-controller@1c10b000            /soc/ethernet@11021000          /soc/i2c@11e02000           /soc/i2c@11e03000           /soc/i2c@11e04000           /soc/i2c@11e00000           /soc/i2c@11e01000           $/soc/mmc@11230000           )/soc/mmc@11240000           ./soc/serial@11001100            6/soc/serial@11001200            >/soc/spi@11010000           C/soc/spi@11012000         cpus                         +       cpu@0           Hcpu           arm,cortex-a55          T            Xpsci            f               zec3@        Š  4        �              ­  €         º   @        Ì   €        Ù  €         æ   @        ø   €                              %           0         cpu@100         Hcpu           arm,cortex-a55          T           Xpsci            f               zec3@        Š  4        �              ­  €         º   @        Ì   €        Ù  €         æ   @        ø   €                              %           0         cpu@200         Hcpu           arm,cortex-a55          T           Xpsci            f               zec3@        Š  4        �              ­  €         º   @        Ì   €        Ù  €         æ   @        ø   €                              %           0         cpu@300         Hcpu           arm,cortex-a55          T           Xpsci            f               zec3@        Š  4        �              ­  €         º   @        Ì   €        Ù  €         æ   @        ø   €                              %           0         cpu@400         Hcpu           arm,cortex-a78          T           Xpsci            f              z�fÔÀ        Š           �              ­           º   @        Ì           Ù           æ   @        ø              	                   %   
        0         cpu@500         Hcpu           arm,cortex-a78          T           Xpsci            f              z�fÔÀ        Š           �              ­           º   @        Ì           Ù           æ   @        ø              	                   %   
        0         cpu@600         Hcpu           arm,cortex-a78          T           Xpsci            f              z�fÔÀ        Š           �              ­           º   @        Ì           Ù           æ   @        ø              	                   %   
        0         cpu@700         Hcpu           arm,cortex-a78          T           Xpsci            f              z�fÔÀ        Š           �              ­           º   @        Ì           Ù           æ   @        ø              	                   %   
        0         cpu-map    cluster0       core0           8         core1           8         core2           8         core3           8         core4           8         core5           8         core6           8         core7           8               idle-states         <psci       cpu-retention-l           arm,idle-state          I           `        q   2        ‚   _        ’  D        0         cpu-retention-b           arm,idle-state          I           `        q   -        ‚   Œ        ’  ä        0         cpu-off-l             arm,idle-state          I          `        q   7        ‚   ›        ’  H        0         cpu-off-b             arm,idle-state          I          `        q   2        ‚   È        ’  è        0            l2-cache0             cache           £           ¯           ¼   @        Î                       ¯        0         l2-cache1             cache           £           ¯           ¼   @        Î                       ¯        0   	      l3-cache              cache           £           ¯            ¼   @        Î            ¯        0            dsu-pmu           arm,dsu-pmu         ½                       È                                Ífail          dmic-codec            dmic-codec          Ô           á   2        0   Ü      mt8195-sound            ñ           Íokay              mediatek,mt8195_mt6359           7mt8395-evk          default                  ,  Headphone Headphone L Headphone Headphone R         )           0   Ý   headphone-dai-link        
  7DL_SRC_BE      codec           A                hdmi-dai-link           7ETDM3_OUT_BE       codec           A                   fixed-factor-clock-13m            fixed-factor-clock          K            X           _           i           tclk13m          0   0      oscillator-26m            fixed-clock         K            zŒº€        tclk26m          0         oscillator-32k            fixed-clock         K            z  €         tclk32k          0   Þ      performance-controller@11bc10             mediatek,cpufreq-hw          T     ¼            ½0               ‡           0         opp-table-gpu             operating-points-v2          ¡        0   ~   opp-390000000           ¬    >í€        ³ 	‰h      opp-410000000           ¬    p€        ³ 	¡Ò      opp-431000000           ¬    °‰À        ³ 	¡Ò      opp-473000000           ¬    1h@        ³ 	º<      opp-515000000           ¬    ²FÀ        ³ 	º<      opp-556000000           ¬    !#ã         ³ 	Ò¦      opp-598000000           ¬    #¤Á€        ³ 	ë      opp-640000000           ¬    &%          ³ 	ë      opp-670000000           ¬    'ïc€        ³ 
ä      opp-700000000           ¬    )¹'         ³ 
L¸      opp-730000000           ¬    +‚ê€        ³ 
}Œ      opp-760000000           ¬    -L®         ³ 
®`      opp-790000000           ¬    /q€        ³ 
ß4      opp-820000000           ¬    0à5         ³       opp-850000000           ¬    2©ø€        ³ @Ü      opp-880000000           ¬    4s¼         ³ q°         pmu-a55           arm,cortex-a55-pmu                      ½                  pmu-a78           arm,cortex-a78-pmu                      ½                  psci              arm,psci-1.0            _smc       timer             arm,armv8-timer                   @  ½                                             
               0   ß      soc                      +             simple-bus           Á        È                          interrupt-controller@c000000              arm,gic-v3          Ó           ä                        û         T                                    ½      	               0      ppi-partitions     interrupt-partition-0                               0         interrupt-partition-1                               0               syscon@10000000            mediatek,mt8195-topckgen syscon         T                      K           0         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          T                     K                      0          syscon@10003000           mediatek,mt8195-pericfg syscon          T     0                K           0   I      pinctrl@10005000              mediatek,mt8195-pinctrl       €  T     P            Ñ             Ó             Ô             â             ë             ô              °              B  &iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            0        @           L              �         û        ½       ë               Ó            X        0      audio-default-pins          0      pins-cmd-dat            |  F  E  G  H  I  J  K         dsi0-backlight-pins         0   Ø   pins-backlight-en           |  k          ƒ         eth-default-pins            0   E   pins-cc         |  U  V  W  X        �         pins-mdio           |  Y  Z         ž      pins-power          |  [   \          ƒ      pins-rst            |  ]       pins-rxd            |  Q  R  S  T      pins-txd            |  M  N  O  P        �            eth-sleep-pins          0   F   pins-cc         |  U   V   W   X       pins-mdio           |  Y   Z          «         ¸      pins-rxd            |  Q   R   S   T       pins-txd            |  M   N   O   P          gpio-keys-pins          0   à   pins            |  j          Æ         ž         hdmi-vreg-pins          0   j   pins-pwr            |           «         hdmi-pins           0   È   pins-hotplug            |            Ó      pins-ddc            |  "  #        �   
      pins-cec            |  !         «         i2c2-pins           0   l   pins-bus            |            Æ  è        �           â  è         i2c4-pins           0   o   pins-bus            |            Æ  è        â  è         i2c6-pins           0   d   pins            |             «         mmc0-default-pins           0   N   pins-clk            |  z        Ó   f        �         pins-cmd-dat          $  |  ~  }  |  {  w  v  u  t  y        Æ   e        �            ž      pins-rst            |  x        Æ   e        �            mmc0-uhs-pins           0   O   pins-clk            |  z        Ó   f        �         pins-cmd-dat          $  |  ~  }  |  {  w  v  u  t  y        Æ   e        �            ž      pins-ds         |          Ó   f        �         pins-rst            |  x        Æ   e        �            mmc1-default-pins           0   R   pins-clk            |  o        Ó   f        �         pins-cmd-dat            |  n  p  q  r  s        Æ   e        �            ž         mmc1-detect-pins            0   S   pins-insert         |  �          Æ         mt6360-pins         0   e   pins-irq            |  d   e          ž         Æ         panel-pins          0   á   pins-rst            |  l          Æ         pcie0-default-pins          0   _   pins-bus            |               Æ         pcie1-default-pins          0   b   pins-bus            |                «         pwm0-pins           0   â   pins-disp-pwm           |  a         spi1-default-pins           0   ?   pins-bus            |  ˆ  ‰  Š  ‹         «         spi2-default-pins           0   @   pins-bus            |  Œ  �  Ž  �         «         touch-pins          0   ã   pins-touch-int          |  „          ž         «      pins-touch-rst          |  …          ƒ         uart0-pins          0   :   pins-bus            |  b  c         uart1-pins          0   ;   pins-bus            |  f  g         usb3p0-default-pins         0   J   pins-vbus           |  ?         ž         usb2p0-default-pins         0   Z   pins-iddig          |  ‚         ž         Æ      pins-vbus           |  ƒ         ú         wifi-vreg-pins          0   Ú   pins-wifi-pmu-en            |  A          ƒ      pins-wifi-vreg-en           |  C             syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            T     `                0   ä   power-controller          !    mediatek,mt8195-power-controller                         +                       0   3   power-domain@8          T                        +                                  0   å   power-domain@9          T   	        X                    'mfg alt         3                         +                          !        0   æ   power-domain@10         T   
                  power-domain@11         T                     power-domain@12         T                     power-domain@13         T                     power-domain@14         T                           power-domain@15         T         Ø  X                        	      @      A      K      à   "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "      "           'vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           3                         +                  power-domain@16         T         8  X      â   #   $   #   %   #   &   #   '   #   (   #   )      D  'vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         3                         +                  power-domain@17         T           X      á   $      $           'vppsys1 vppsys1-0 vppsys1-1         3                      power-domain@22         T            X   %      %      %      %         $  'wepsys-0 wepsys-1 wepsys-2 wepsys-3         3                      power-domain@23         T           X   &            'vdec0-0         3                         +                   power-domain@24         T           X   '            'vdec1-0         3                      power-domain@25         T           X   (            'vdec2-0         3                         power-domain@26         T           X   )            'venc0-larb          3                         +                   power-domain@27         T           X   *            'venc1-larb          3                         power-domain@18         T            X      ã   +       +      +         &  'vdosys1 vdosys1-0 vdosys1-1 vdosys1-2           3                         +                  power-domain@19         T           3                      power-domain@20         T           3                      power-domain@21         T           X      Q        'hdmi_tx                      power-domain@28         T           X   ,       ,   
        'img-0 img-1         3                         +                  power-domain@29         T                     power-domain@30         T           X         ,      -           'ipe ipe-0 ipe-1         3                         power-domain@31         T         (  X   .       .      .      .      .           'cam-0 cam-1 cam-2 cam-3 cam-4           3                         +                  power-domain@32         T                      power-domain@33         T   !                  power-domain@34         T   "                           power-domain@0          T            3                      power-domain@1          T           3                      power-domain@2          T                     power-domain@3          T                     power-domain@4          T           X      5      7        'csi_rx_top csi_rx_top1                    power-domain@5          T           X   /           'ether                     power-domain@6          T           X      X      n        'adsp adsp1                       +            3                  power-domain@7          T            X      g      "      n       2        'audio audio1 audio2 audio3          3                               watchdog@10007000             mediatek,mt8195-wdt          E        T     p                           0   8      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           T     À                K           0         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         T    p                ½      	               X   0        0   ç      pwrap@10024000            mediatek,mt8195-pwrap syscon            T    @                &pwrap           ½       ó               X                     	  'spi wrap            ]      $        m      Ë        0   è   pmic              mediatek,mt6359          û        Ó           „           •      Þ           0      adc           mediatek,mt6359-auxadc          ©           0   é      audio-codec           mediatek,mt6359-codec           0   ê      regulators            mediatek,mt6359-regulator      buck_vs1            »vs1         Ê 5         â !‘À        ú                     0   ë      buck_vgpu11         »vgpu11          Ê €        â 7        *  ˆ        ú   È        ?                           0   ì      buck_vmodem         »vmodem          Ê €        â Èà        *  *        ú   È        0   í      buck_vpu            »vpu         Ê €        â 7        *  ˆ        ú   È        ?                           0   î      buck_vcore          »vcore           Ê €        â Ö         *  ˆ        ú   È        ?                           0         buck_vs2            »vs2         Ê 5         â j         ú                     0   ï      buck_vpa            »vpa         Ê ¡         â 7±Ð        ú  ,        0   ð      buck_vproc2         »vproc2          Ê €        â 7        *  L        ú   È        ?                           0   ñ      buck_vproc1         »vproc1          Ê €        â 7        *  L        ú   È        ?                           0   ò      buck_vcore_sshub            »vcore_sshub         Ê €        â 7        0   ó      buck_vgpu11_sshub           »vgpu11_sshub            Ê €        â 7        0   ô      ldo_vaud18          »vaud18          Ê w@        â w@        ú   ð                 0   õ      ldo_vsim1           »vsim1           Ê ð         â /M`        0   ö      ldo_vibr            »vibr            Ê O€        â 2Z         0   m      ldo_vrf12           »vrf12           Ê Èà        â Ö                  0   ÷      ldo_vusb            »vusb            Ê -ÆÀ        â -ÆÀ        ú  À                 0   K      ldo_vsram_proc2         »vsram_proc2         Ê ¡         â ½¶        *  L        ú   ð                 0   ø      ldo_vio18           »vio18           Ê ð         â ýà        ú  À                 0   ù      ldo_vcamio          »vcamio          Ê ð         â ýà                 0   ú      ldo_vcn18           »vcn18           Ê w@        â w@        ú   ð        0   û      ldo_vfe28           »vfe28           Ê *¹€        â *¹€        ú   x        0   ü      ldo_vcn13           »vcn13           Ê »         â Ö         0   ý      ldo_vcn33_1_bt          »vcn33_1_bt          Ê *¹€        â 5gà        0   þ      ldo_vcn33_1_wifi            »vcn33_1_wifi            Ê *¹€        â 5gà        0   ÿ      ldo_vaux18          »vaux18          Ê w@        â w@        ú   ð                 0         ldo_vsram_others            »vsram_others            Ê q°        â q°        *  ˆ        ú   ð        0   !      ldo_vefuse          »vefuse          Ê ð         â „€        0        ldo_vxo22           »vxo22           Ê w@        â !‘À                 0        ldo_vrfck           »vrfck           Ê ã`        â ð         0        ldo_vrfck_1         »vrfck_1         Ê ëÀ        â j         0        ldo_vbif28          »vbif28          Ê *¹€        â *¹€        ú   ð        0        ldo_vio28           »vio28           Ê *¹€        â 2Z                  0        ldo_vemc            »vemc            Ê ,@         â 2Z         0        ldo_vemc_1          »vemc_1          Ê &%         â 2Z         0   P      ldo_vcn33_2_bt          »vcn33_2_bt          Ê 2Z         â 2Z         0        ldo_vcn33_2_wifi            »vcn33_2_wifi            Ê *¹€        â 5gà        0  	      ldo_va12            »va12            Ê O€        â Ö                  0  
      ldo_va09            »va09            Ê 5         â O€        0        ldo_vrf18           »vrf18           Ê ð         â žP        0        ldo_vsram_md          	  »vsram_md            Ê ¡         â ½¶        *  *        ú   ð                 0        ldo_vufs            »vufs            Ê ð         â ýà        0   Q      ldo_vm18            »vm18            Ê ð         â ýà                 0        ldo_vbbck           »vbbck           Ê Èà        â O€                 0        ldo_vsram_proc1         »vsram_proc1         Ê ¡         â ½¶        *  L        ú   ð                 0        ldo_vsim2           »vsim2           Ê ð         â /M`        0        ldo_vsram_others_sshub          »vsram_others_sshub          Ê ¡         â ½¶        0           rtc           mediatek,mt6358-rtc         0        keys              mediatek,mt6359-keys            W           p            0     power-key           ƒ   t         ’      home            ƒ   f               spmi@10027000             mediatek,mt8195-spmi             T    p            �                &pmif spmimst            X                     E      (  'pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         ]      $        m      Ë                     +            0     pmic@6            mediatek,mt6315-regulator           T               0     regulators     vbuck1          »Vbcpu           Ê “à        â 7        ú           ?                           0   
            pmic@7            mediatek,mt6315-regulator           T               0     regulators     vbuck1          »Vgpu            Ê “à        â 7        ú           ?                  0                  infra-iommu@10315000              mediatek,mt8195-iommu-infra         T    1P       P       P  ½                                                                                     0   \      mailbox@10320000              mediatek,mt8195-gce         T    2        @         ½       â               ­           X               0   ¡      mailbox@10330000              mediatek,mt8195-gce         T    3        @         ½       ä               ­           X               0         scp@10500000              mediatek,mt8195-scp       0  T    P             r             p        €         &sram cfg l1tcm          ½      Î               Íokay            ¹   1        Çmediatek/mt8195/scp.img         0   €      clock-controller@10720000             mediatek,mt8195-scp_adsp            T    r                 K           0   2      dsp@10803000              mediatek,mt8195-dsp          T    €0            „               	  &cfg sram          ,  X      X         n      Š   2          #      K  'adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          Õ   3           ãrx tx           î   4   5        Íokay            ¹   6   7        0         mailbox@10816000              mediatek,mt8195-adsp-mbox           ­            T    �`                ½      ¾               0   4      mailbox@10817000              mediatek,mt8195-adsp-mbox           ­            T    �p                ½      ¿               0   5      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           T    ‰                 õ           Õ   3           ½      6                  8         	  audiosys          ”  X                     Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d       2   2          ó  'clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          Íokay            ¹   9        0         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           T                     ½       �               X                	  'baud bus            Íokay               :        default         0        serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           T                     ½       Ž               X                	  'baud bus            Íokay               ;        default         0        serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           T                     ½       �               X                	  'baud bus          	  Ídisabled            0        serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           T                     ½      Ó               X                	  'baud bus          	  Ídisabled            0        serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           T                     ½      Ô               X                	  'baud bus          	  Ídisabled            0        serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           T                     ½      Õ               X                	  'baud bus          	  Ídisabled            0        auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           T                      X               'main            ©         	  Ídisabled            0        syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           T     0                K           0   /      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            T                      ½       ¿               X      ™                     'parent-clk sel-clk spi-clk        	  Ídisabled            0        thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         T     °                ½       ©               X                                  <   =      $  &lvts-calib-data-1 lvts-calib-data-2         7           0   Õ      svs@1100bc00              mediatek,mt8195-svs         T     ¼                ½       Ç               X               'main               >   <      (  &svs-calibration-data t-calibration-data                        svs_rst         0         pwm@1100e000               â        default       2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           T     à                ½       Ë               Õ   3           M           X      *       0        'main mm         Íokay led        0   Ù      pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           T     ð                ½                     M           X      +       N        'main mm       	  Ídisabled            0  !      spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            T                     ½       À               X      ™             3        'parent-clk sel-clk spi-clk          Íokay               ?        default         X            0  "      spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            T                     ½       Á               X      ™             4        'parent-clk sel-clk spi-clk          Íokay               @        default         X            0  #      spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            T    0                ½       Â               X      ™             5        'parent-clk sel-clk spi-clk        	  Ídisabled            0  $      spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            T    €                ½       Ã               X      ™             <        'parent-clk sel-clk spi-clk        	  Ídisabled            0  %      spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            T    �                ½       Ä               X      ™             =        'parent-clk sel-clk spi-clk        	  Ídisabled            0  &      spi@1101d000              mediatek,mt8195-spi-slave           T    Ð                ½       Å               X       R        'spi         ]              m      ˜      	  Ídisabled            0  '      spi@1101e000              mediatek,mt8195-spi-slave           T    à                ½       Æ               X       S        'spi         ]              m      ˜      	  Ídisabled            0  (      ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           T           @         ½      Ì               lmacirq        .  'axi apb mac_main ptp_ref rmii_internal mac_cg         0  X   /       /         R      S      T   /           ]      R      S      T        m      Â      Ã      Ä        Õ   3           |            �   A        �   B        °   C        Ã           Î           Ù            Íokay            ærgmii-rxid          ï   D        default sleep              E        ú   F          î                 *      ]            :      N  †         0  )   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916            T           0   D         stmmac-axi-config           O           _           o                                 0   A      rx-queues-config            y            �        0   B   queue0                    ³          queue1                    ³          queue2                    ³          queue3                    ³             tx-queues-config            Ë            á        0   C   queue0          ó                     ÿ          queue1          ó                     ÿ         queue2          ó                     ÿ         queue3          ó                     ÿ               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           T            -ÿ     >              	  &mac ippc            Á                     ?                      +           ½       €               X       /      í       B        'sys_ck ref_ck mcu_ck            	   G      H            ’        	   I      g        Íokay            default            J        	)host             	B        	R   K        0  *   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          T                       &mac         ½       �               ]      ,      -        m      –      –      $  X       /      í                B      $  'sys_ck ref_ck mcu_ck dma_ck xhci_ck         Íokay            	`   L        0  +      port       endpoint            	l   M        0   h            mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          T    #             õ                 ½       ƒ               X                            'source hclk source_cg           Íokay            default state_uhs              N        ú   O        	|           	†ëÂ         	” L         	£         	µ         	Æ         	Õ         	ä         	ì         	ò        
    P        
   Q        0  ,      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          T    $             Ç                 ½       ‡               X                    $        'source hclk source_cg           ]              m      ¿        Íokay            default state_uhs              R   S        ú   R        	|           	†ëÂ          
        
*      �            
3         	ä         
:         
G        
    T        
   U        0  -      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          T    %             æ                 ½       ˆ               X                     I        'source hclk source_cg           ]               m      ¿      	  Ídisabled            0  .      ufshci@11270000           mediatek,mt8195-ufshci          T    '        #         ½       ‰               	   V      @  X       ?       @       A       6       7       8       Z       ]      X  'ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  
U                                                                         
c        Íokay            
|   P        
‡   Q        0  /      thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            T    '€                ½       ª               X                                 <   =      $  &lvts-calib-data-1 lvts-calib-data-2         7           0   Ì      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           T    )             )>              	  &mac ippc            ½                     	   W           ]      .      /        m      –      –      $  X   /         ï            /         $  'sys_ck ref_ck mcu_ck dma_ck xhci_ck         	   I      h         ’        Íokay             
”        	R   K        	`   X        
¥           0  0      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           T    *       -ÿ    *>              	  &mac ippc            Á            *        ?                      +           ½                     ]      0        m      –        X   /         ñ   /           'sys_ck ref_ck mcu_ck            	   Y            ’        	   I      i        Íokay            default            Z        	R   K        0  1   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          T                       &mac         ½                     ]      1        m      –        X   /           'sys_ck          Íokay            	`   X        0  2         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           T    +       -ÿ    +>              	  &mac ippc            Á            +        ?                      +           ½                     ]      2        m      –        X   /         ó   /   	        'sys_ck ref_ck mcu_ck            	   [            ’        	   I      j      	  Ídisabled            0  3   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          T                       &mac         ½                     ]      3        m      –        X   /   	        'sys_ck        	  Ídisabled            0  4         pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           Hpci                      +           T    /        @       	  &pcie-mac            ½                     
º       ÿ      8  Á�                           ‚                       à          
Ä       \              
Î          0  X       V       #       &       +       K   /         /  'pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ]      G        m              	   ]      	  
Ýpcie-phy            Õ   3            Ó           
ç                     `  
ú                  ^                      ^                     ^                     ^           Íokay            default            _        0  5   interrupt-controller             û                     Ó           0   ^         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           Hpci                      +           T    /€       @       	  &pcie-mac            ½                     
º       ÿ      8  Á�       $       $           ‚       $       $       à          
Ä       \              
Î          (  X       W          X          Q   /         /  'pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ]      H        m              	   `         	  
Ýpcie-phy            Õ   3           Ó           
ç                     `  
ú                  a                      a                     a                     a           Íokay            default            b        0  6   interrupt-controller             û                     Ó           0   a         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         T    2À                ½      9               X      o   /      /           'spi sf axi                       +          	  Ídisabled            0  7      efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            T    Á                              +           0  8   usb3-tx-imp@184,1           T  „                          0   u      usb3-rx-imp@184,2           T  „                         0   t      usb3-intr@185           T  …                         0   s      usb3-tx-imp@186,1           T  †                          0   r      usb3-rx-imp@186,2           T  †                         0   q      usb3-intr@187           T  ‡                         0   p      usb2-intr-p0@188,1          T  ˆ                          0  9      usb2-intr-p1@188,2          T  ˆ                         0  :      usb2-intr-p2@189,1          T  ‰                         0  ;      usb2-intr-p3@189,2          T  ‰                         0  <      pciephy-rx-ln1@190,1            T  �                          0   |      pciephy-tx-ln1-nmos@190,2           T  �                         0   {      pciephy-tx-ln1-pmos@191,1           T  ‘                          0   z      pciephy-rx-ln0@191,2            T  ‘                         0   y      pciephy-tx-ln0-nmos@192,1           T  ’                          0   x      pciephy-tx-ln0-pmos@192,2           T  ’                         0   w      pciephy-glb-intr@193            T  “                          0   v      dp-data@1ac         T  ¬           0   Ë      lvts1-calib@1bc         T  ¼           0   <      lvts2-calib@1d0         T  Ð   8        0   =      svs-calib@580           T  €   d        0   >      socinfo-data1@7a0           T               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Á        Ä             Íokay            0  =   usb-phy@0           T               X      ò        'ref                    0   Y         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Á        Å           	  Ídisabled            0  >   usb-phy@0           T               X      ô        'ref                    0   [         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         T    È                 X           tmipi_tx0_pll            K                        Íokay led        0   ¯      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         T    É                 X           tmipi_tx1_pll            K                      	  Ídisabled            0   ±      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          T    Ð             "€       €        ½       š               _           X   c           ;      	  'main dma                         +          	  Ídisabled            0  ?      i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          T    Ð            "        €        ½       ›               _           X   c          ;      	  'main dma                         +            Íokay            z €           d        default         0  @   pmic@34           mediatek,mt6360         T   4        •      e           lIRQB             û        Ó              e        0  A   charger           mediatek,mt6360-chg          Ý@    usb-otg-vbus-regulator          »usb-otg-vbus            Ê C…(        â Xáè        0   L         regulator             mediatek,mt6360-regulator           1   f        A   g   buck1         	  »emi_vdd2            Ê “à        â Ö         ?                           0  B      buck2         	  »emi_vddq            Ê “à        â Ö         ?                           0   g      ldo1            »ext_lcd_3v3         Ê 2Z         â 2Z         ?                        0  C      ldo2            »panel1_p1v8         Ê w@        â w@        ?               0  D      ldo3            »vmc_pmu         Ê O€        â 6î€        ?               0   U      ldo5          	  »vmch_pmu            Ê 2Z         â 2Z         ?                        0   T      ldo6            »mt6360_ldo6         Ê ¡         â           ?               0  E      ldo7            »emi_vmddr_en            Ê ¡         â           ?                        0  F         typec             mediatek,mt6360-tcpc            •      d           lPD_IRQB    connector             usb-c-connector         QUSB-C           Wdual            a ˜–€        sdual            ~sink            �"�d        ™"‘,   ports                        +       port@0          T       endpoint            	l   h        0   M         port@2          T      endpoint            	l   i        0   n                        i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          T    Ð             "€       €        ½       œ               _           X   c          ;      	  'main dma                         +          	  Ídisabled            0  G      clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          T    Ð0                K           0   c      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy            T    Õð                 X      P                           'pll_ref 26m pll1 pll2           thdmi_txpll          K                        £   
        ²           Íokay            default            j        0   Ç      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          T    à             " €       €        ½       �               _           X   k           ;      	  'main dma                         +          	  Ídisabled            0  H      i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          T    à            "        €        ½       “               _           X   k          ;      	  'main dma                         +          	  Ídisabled            0  I      i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          T    à             "€       €        ½       –               _           X   k          ;      	  'main dma                         +            Íokay            z €           l        default         0  J   typec-mux@48              ite,it5205          T   H         Ä         Ð        
|   m   port       endpoint            	l   n        0   i               i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          T    à0            "€       €        ½       ˜               _           X   k          ;      	  'main dma                         +          	  Ídisabled            0  K      i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          T    à@            "        €        ½       ™               _           X   k          ;      	  'main dma                         +            Íokay            z €           o        default         0  L   touchscreen@14             ã        default         €          j      …            v      „            •      „           T             goodix,gt911 ler         clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          T    àP                K           0   k      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Á        ã             Õ   3           Íokay            0  M   usb-phy@0           T               X      ð           'ref da_ref                     0   W      usb-phy@700         T              X            ð        'ref da_ref             p   q   r        &intr rx_imp tx_imp                     0   `         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Á        ä             Íokay            0  N   usb-phy@0           T               X      î           'ref da_ref                     0   G      usb-phy@700         T              X            î        'ref da_ref             s   t   u        &intr rx_imp tx_imp                     0   H         phy@11e80000              mediatek,mt8195-pcie-phy            T    è                 &sif            v   w   x   y   z   {   |      G  &glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          Õ   3                       Íokay            0   ]      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           T    ú        À         X            
  'unipro mp                       Íokay            0   V      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           T             @         X   }          0  ½      �             Œ             ‹               ljob mmu gpu         ã   ~      (  Õ   3   
   3      3      3      3           ÷core0 core1 core2 core3 core4           Íokay            
           0  O      clock-controller@13fbf000             mediatek,mt8195-mfgcfg          T    ûð                K           0   }      syscon@14000000           mediatek,mt8195-vppsys0 syscon          T                      K                                 0   "      dma-controller@14001000           mediatek,mt8195-mdp3-rdma           T                                          .              B   €        Õ   3           O   �   €        X   "         <  î                                                     V         display@14002000              mediatek,mt8195-mdp3-fg         T                                            X   "          display@14003000              mediatek,mt8195-mdp3-stitch         T     0                         0            X   "         display@14004000              mediatek,mt8195-mdp3-hdr            T     @                         @            X   "   "      display@14005000              mediatek,mt8195-mdp3-aal            T     P                ½      F                        P            X   "   
        Õ   3         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           T     `                         `            .    %        X   "         display@14007000              mediatek,mt8195-mdp3-tdshp          T     p                         p            X   "   #      display@14008000              mediatek,mt8195-mdp3-color          T     €                ½      I                        €            X   "   $        Õ   3         display@14009000              mediatek,mt8195-mdp3-ovl            T     �                ½      J                        �            X   "   %        Õ   3           O   �   ‚      display@1400a000              mediatek,mt8195-mdp3-padding            T                                            X   "           Õ   3         display@1400b000              mediatek,mt8195-mdp3-tcc            T     °                         °            X   "         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         T     À                         À            .    +        X   "           O   �   ƒ        Õ   3           V         mutex@1400f000            mediatek,mt8195-vpp-mutex           T     ð                ½      P                        ð            X   "           Õ   3         smi@14010000              mediatek,mt8195-smi-sub-common          T                     X   "      "      "           'apb smi gals0           a   ‚        Õ   3           0   ƒ      smi@14011000              mediatek,mt8195-smi-sub-common          T                    X   "      "      "           'apb smi gals0           a   ‚        Õ   3           0          smi@14012000              mediatek,mt8195-smi-common-vpp          T                      X   "      "      "      "           'apb smi gals0 gals1         Õ   3           0   ‚      larb@14013000             mediatek,mt8195-smi-larb            T    0                n           a   ƒ        X   "      "           'apb smi         Õ   3           0   †      iommu@14018000            mediatek,mt8195-iommu-vpp           T    €              8     „   …   †   ‡   ˆ   ‰   Š   ‹   Œ   �   Ž   �   �   ‘        ½      R               X   "           'bclk                        Õ   3           0   �      clock-controller@14e00000             mediatek,mt8195-wpesys          T    à                 K           0   %      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         T    à                 K           0  P      clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         T    à0                K           0  Q      larb@14e04000             mediatek,mt8195-smi-larb            T    à@                n           a   ’        X   %      %           'apb smi         Õ   3           0   ¶      larb@14e05000             mediatek,mt8195-smi-larb            T    àP                n           a   ‚        X   %      %      "           'apb smi gals            Õ   3           0   ˆ      syscon@14f00000           mediatek,mt8195-vppsys1 syscon          T    ð                 K                 	               0   $      mutex@14f01000            mediatek,mt8195-vpp-mutex           T    ð                ½      {                     	              X   $   '        Õ   3         larb@14f02000             mediatek,mt8195-smi-larb            T    ð                 n           a   ’        X   $      $      "           'apb smi gals            Õ   3           0   µ      larb@14f03000             mediatek,mt8195-smi-larb            T    ð0                n           a   ƒ        X   $      $      "           'apb smi gals            Õ   3           0   ‡      display@14f06000              mediatek,mt8195-mdp3-split          T    ð`                      	  `            X   $      $   +   $   ,        Õ   3         display@14f07000              mediatek,mt8195-mdp3-tcc            T    ðp                      	  p            X   $         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           T    ð€                      	  €            .  „  ¨        X   $           O   “            Õ   3           V         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           T    ð�                      	  �            .  …  ©        X   $   
        O   “   ¤        Õ   3           V         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           T    ð                       	               .  †  ª        X   $           O   �   À        Õ   3           V         display@14f0b000              mediatek,mt8195-mdp3-fg         T    ð°                      	  °            X   $   	      display@14f0c000              mediatek,mt8195-mdp3-fg         T    ðÀ                      	  À            X   $         display@14f0d000              mediatek,mt8195-mdp3-fg         T    ðÐ                      	  Ð            X   $         display@14f0e000              mediatek,mt8195-mdp3-hdr            T    ðà                      	  à            X   $         display@14f0f000              mediatek,mt8195-mdp3-hdr            T    ðð                      	  ð            X   $         display@14f10000              mediatek,mt8195-mdp3-hdr            T    ñ                       
               X   $          display@14f11000              mediatek,mt8195-mdp3-aal            T    ñ                ½      i                     
              X   $           Õ   3         display@14f12000              mediatek,mt8195-mdp3-aal            T    ñ                 ½      j                     
               X   $           Õ   3         display@14f13000              mediatek,mt8195-mdp3-aal            T    ñ0                ½      k                     
  0            X   $   !        Õ   3         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           T    ñ@                      
  @            .  �  ¯        X   $         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           T    ñP                      
  P            .  ‘  °        X   $   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           T    ñ`                      
  `            .  ’  ±        X   $   %      display@14f17000              mediatek,mt8195-mdp3-tdshp          T    ñp                      
  p            X   $         display@14f18000              mediatek,mt8195-mdp3-tdshp          T    ñ€                      
  €            X   $   (      display@14f19000              mediatek,mt8195-mdp3-tdshp          T    ñ�                      
  �            X   $   )      display@14f1a000              mediatek,mt8195-mdp3-merge          T    ñ                       
               X   $           Õ   3         display@14f1b000              mediatek,mt8195-mdp3-merge          T    ñ°                      
  °            X   $           Õ   3         display@14f1c000              mediatek,mt8195-mdp3-color          T    ñÀ                ½      t                     
  À            X   $           Õ   3         display@14f1d000              mediatek,mt8195-mdp3-color          T    ñÐ                      
  Ð            ½      u               X   $           Õ   3         display@14f1e000              mediatek,mt8195-mdp3-color          T    ñà                ½      v                     
  à            X   $           Õ   3         display@14f1f000              mediatek,mt8195-mdp3-ovl            T    ñð                ½      w                     
  ð            X   $            Õ   3           O   “   ¢      display@14f20000              mediatek,mt8195-mdp3-padding            T    ò                                      X   $           Õ   3         display@14f21000              mediatek,mt8195-mdp3-padding            T    ò                                    X   $           Õ   3         display@14f22000              mediatek,mt8195-mdp3-padding            T    ò                                      X   $           Õ   3         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         T    ò0                        0            .  Ÿ  «        X   $           O   “   £        Õ   3           V         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         T    ò@                        @            .     ¬        X   $           O   “   ¦        Õ   3           V         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         T    òP                        P            .  ¡  ­        X   $           O   �   Â        Õ   3           V         clock-controller@15000000             mediatek,mt8195-imgsys          T                      K           0   ,      larb@15001000             mediatek,mt8195-smi-larb            T                     n   	        a   ”        X   ,       ,       ,   
        'apb smi gals            Õ   3           0   ·      smi@15002000              mediatek,mt8195-smi-sub-common          T                      X   ,      ,      "           'apb smi gals0           a   ‚        Õ   3           0   —      smi@15003000              mediatek,mt8195-smi-sub-common          T     0                X   ,       ,       ,   
        'apb smi gals0           a   ’        Õ   3           0   ”      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         T                     K           0   •      larb@15120000             mediatek,mt8195-smi-larb            T                     n   
        a   ”        X   ,      •            'apb smi         Õ   3           0   ¸      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          T                     K           0  R      clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         T    "                 K           0   –      larb@15230000             mediatek,mt8195-smi-larb            T    #                 n           a   ”        X   ,      –            'apb smi         Õ   3           0   ¹      clock-controller@15330000             mediatek,mt8195-ipesys          T    3                 K           0   -      larb@15340000             mediatek,mt8195-smi-larb            T    4                 n           a   —        X   -      -           'apb smi         Õ   3           0   ‰      clock-controller@16000000             mediatek,mt8195-camsys          T                      K           0   .      larb@16001000             mediatek,mt8195-smi-larb            T                     n           a   ˜        X   .       .       .           'apb smi gals            Õ   3           0   º      larb@16002000             mediatek,mt8195-smi-larb            T                      n           a   ™        X   .      .           'apb smi         Õ   3           0   Š      smi@16004000              mediatek,mt8195-smi-sub-common          T     @                X   .       .       .           'apb smi gals0           a   ’        Õ   3           0   ˜      smi@16005000              mediatek,mt8195-smi-sub-common          T     P                X   .      .      "           'apb smi gals0           a   ‚        Õ   3           0   ™      larb@16012000             mediatek,mt8195-smi-larb            T                     n           a   ™        X   š       š            'apb smi         Õ   3            0   ‹      larb@16013000             mediatek,mt8195-smi-larb            T    0                n           a   ˜        X   ›       ›            'apb smi         Õ   3            0   »      larb@16014000             mediatek,mt8195-smi-larb            T    @                n           a   ™        X   œ       œ            'apb smi         Õ   3   !        0   ‘      larb@16015000             mediatek,mt8195-smi-larb            T    P                n           a   ˜        X   �       �            'apb smi         Õ   3   !        0   À      clock-controller@1604f000             mediatek,mt8195-camsys_rawa         T    ð                K           0   š      clock-controller@1606f000             mediatek,mt8195-camsys_yuva         T    ð                K           0   ›      clock-controller@1608f000             mediatek,mt8195-camsys_rawb         T    ð                K           0   œ      clock-controller@160af000             mediatek,mt8195-camsys_yuvb         T    
ð                K           0   �      clock-controller@16140000             mediatek,mt8195-camsys_mraw         T                     K           0   ž      larb@16141000             mediatek,mt8195-smi-larb            T                    n           a   ˜        X   .       ž       .           'apb smi gals            Õ   3   "        0   ¿      larb@16142000             mediatek,mt8195-smi-larb            T                     n           a   ™        X   ž       ž            'apb smi         Õ   3   "        0   �      clock-controller@17200000             mediatek,mt8195-ccusys          T                      K           0   Ÿ      larb@17201000             mediatek,mt8195-smi-larb            T                     n           a   ™        X   Ÿ       Ÿ            'apb smi         Õ   3           0   Œ      video-codec@18000000              mediatek,mt8195-vcodec-dec          B   €        O   “                        +            T                   @                Á                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         T                       O   �  à   �  á         X      A   &      &         �        'sel vdec lat top            ]      A        m      �        Õ   3         video-codec@10000             mediatek,mtk-vcodec-lat         T                      ½      Ä             0  O   “      “     “     “     “     “           X      A   &      &         �        'sel vdec lat top            ]      A        m      �        Õ   3         video-codec@25000             mediatek,mtk-vcodec-core            T     P                ½      Ã             P  O   “      “  ¡   “  ¢   “  £   “  ¤   “  ¥   “  ¦   “  §   “  ¨   “  ©         X      A   '      '         �        'sel vdec lat top            ]      A        m      �        Õ   3            larb@1800d000             mediatek,mt8195-smi-larb            T     Ð                n           a   ’        X   &       &            'apb smi         Õ   3           0   ¾      larb@1800e000             mediatek,mt8195-smi-larb            T     à                n           a            X   "      &            'apb smi         Õ   3           0   �      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         T     ð                K           0   &      larb@1802e000             mediatek,mt8195-smi-larb            T    à                n           a   ’        X   '       '            'apb smi         Õ   3           0   ½      clock-controller@1802f000             mediatek,mt8195-vdecsys         T    ð                K           0   '      larb@1803e000             mediatek,mt8195-smi-larb            T    à                n           a            X   "      (            'apb smi         Õ   3           0   Ž      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           T    ð                K           0   (      clock-controller@190f3000             mediatek,mt8195-apusys_pll          T    0                K           0  S      clock-controller@1a000000             mediatek,mt8195-vencsys         T                      K           0   )      larb@1a010000             mediatek,mt8195-smi-larb            T                     n           a   ’        X   )      )           'apb smi         Õ   3           0   ¼      video-codec@1a020000              mediatek,mt8195-vcodec-enc          T                   H  O   “  `   “  a   “  b   “  c   “  d   “  v   “  w   “  x   “  y        ½      U               B   €        X   )         	  'venc_sel            ]      @        m      �        Õ   3                        +           0  T      jpeg-decoder@1a040000             mediatek,mt8195-jpgdec          Õ   3         0  O   “  m   “  n   “  r   “  s   “  t   “  u                     +         0  Á                                            jpgdec@0,0            mediatek,mt8195-jpgdec-hw           T                     0  O   “  m   “  n   “  r   “  s   “  t   “  u        ½      W               X   )           'jpgdec          Õ   3         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw           T                    0  O   “  m   “  n   “  r   “  s   “  t   “  u        ½      X               X   )           'jpgdec          Õ   3         jpgdec@1,0            mediatek,mt8195-jpgdec-hw           T                    0  O   �  �   �  Ž   �  ’   �  “   �  ”   �  •        ½      \               X   *           'jpgdec          Õ   3            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           T                      K           0   *      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            T                     î   ¡               K              ¡                  0   #   port             +                   endpoint@0          0  š        	l  V        T                jpeg-encoder@1a030000             mediatek,mt8195-jpgenc          Õ   3            O   �  ‡   �  ˆ   �  ‰   �  Œ                     +         0  Á                                            jpgenc@0,0            mediatek,mt8195-jpgenc-hw           T                        O   “  g   “  h   “  i   “  l        ½      V               X   )           'jpgenc          Õ   3         jpgenc@1,0            mediatek,mt8195-jpgenc-hw           T                       O   �  ‡   �  ˆ   �  ‰   �  Œ        ½      [               X   *           'jpgenc          Õ   3            larb@1b010000             mediatek,mt8195-smi-larb            T                     n           a   ‚        X   *      *      "            'apb smi gals            Õ   3           0   �      ovl@1c000000              mediatek,mt8195-disp-ovl            T                      ½      |               Õ   3           X   #            O   “              ¡                  0  U   ports                        +       port@0          T       endpoint            	l  š        0  V         port@1          T      endpoint            	l   ¢        0   £               rdma@1c002000             mediatek,mt8195-disp-rdma           T                      ½      ~               Õ   3           X   #           O   “               ¡                  0  W   ports                        +       port@0          T       endpoint            	l   £        0   ¢         port@1          T      endpoint            	l   ¤        0   ¥               color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           T     0                ½                     Õ   3           X   #              ¡     0            0  X   ports                        +       port@0          T       endpoint            	l   ¥        0   ¤         port@1          T      endpoint            	l   ¦        0   §               ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           T     @                ½      €               Õ   3           X   #              ¡     @            0  Y   ports                        +       port@0          T       endpoint            	l   §        0   ¦         port@1          T      endpoint            	l   ¨        0   ©               aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           T     P                ½      �               Õ   3           X   #              ¡     P            0  Z   ports                        +       port@0          T       endpoint            	l   ©        0   ¨         port@1          T      endpoint            	l   ª        0   «               gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           T     `                ½      ‚               Õ   3           X   #              ¡     `            0  [   ports                        +       port@0          T       endpoint            	l   «        0   ª         port@1          T      endpoint            	l   ¬        0   ­               dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         T     p                ½      ƒ               Õ   3           X   #   	           ¡     p            0  \   ports                        +       port@0          T       endpoint            	l   ­        0   ¬         port@1          T      endpoint            	l   ®        0   °               dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         T     €                ½      „               Õ   3           X   #      #   *   ¯        'engine digital hs           	   ¯        
Ýdphy            Íokay led                     +            0  ]   panel@0            á        default         j      l           ]  D        R          Ê  ’        T          +    radxa,display-8hd-ad002 jadard,jd9365da-h3 t   port       endpoint            0  ™        	l  ^            ports                        +       port@0          T       endpoint            	l   °        0   ®         port@1          T      endpoint            	l  ™        0  ^               dsc@1c009000              mediatek,mt8195-disp-dsc            T     �                ½      …               Õ   3           X   #              ¡     �            0  _      dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         T                     ½      Ž               Õ   3           X   #      #   +   ±        'engine digital hs           	   ±        
Ýdphy          	  Ídisabled            0  `      merge@1c014000            mediatek,mt8195-disp-merge          T    @                ½      �               Õ   3           X   #              ¡     @            0  a      dp-intf@1c015000              mediatek,mt8195-dp-intf         T    P                ½      ‘               Õ   3           X   #   ,   #                 'pixel engine pll          	  Ídisabled            0  b      mutex@1c016000            mediatek,mt8195-disp-mutex          T    `                ½      ’               Õ   3           X   #              ¡     `            .  U        0  c      larb@1c018000             mediatek,mt8195-smi-larb            T    €                n            a   ’        X   #   (   #   (   "           'apb smi gals            Õ   3           0   ³      larb@1c019000             mediatek,mt8195-smi-larb            T    �                n           a   ‚        X   #   (   "       "           'apb smi gals            Õ   3           0   „      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          T                     î   ¡                 ¡                  K                      0   +   port                         +       endpoint@1          T           	l   ²        0   Å            smi@1c01b000              mediatek,mt8195-smi-common-vdo          T    °                 X   #   %   #   &   #   )   #   $        'apb smi gals0 gals1         Õ   3           0   ’      iommu@1c01f000            mediatek,mt8195-iommu-vdo           T    ð              8     ³   ´   µ   ¶   ·   ¸   ¹   º   »   ¼   ½   ¾   ¿   À        ½      �                           X   #   '        'bclk            Õ   3           0   “      mutex@1c101000            mediatek,mt8195-disp-mutex          T                    ½      î               Õ   3           X   +              ¡                 .  À        0  d      larb@1c102000             mediatek,mt8195-smi-larb            T                     n           a   ’        X   +       +       +           'apb smi gals            Õ   3           0   ´      larb@1c103000             mediatek,mt8195-smi-larb            T    0                n           a   ‚        X   +      +      "            'apb smi gals            Õ   3           0   …      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           T    @                ½      ï               X   +           Õ   3           O   “   @           ¡     @            V           0  e      dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           T    P                ½      ð               X   +           Õ   3           O   �   `           ¡     P            V           0  f      dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           T    `                ½      ñ               X   +           Õ   3           O   “   A           ¡     `            V           0  g      dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           T    p                ½      ò               X   +           Õ   3           O   �   a           ¡     p            V           0  h      dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           T    €                ½      ó               X   +           Õ   3           O   “   B           ¡     €            V           0  i      dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           T    �                ½      ô               X   +           Õ   3           O   �   b           ¡     �            V           0  j      dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           T                     ½      õ               X   +           Õ   3           O   “   C           ¡                  V           0  k      dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           T    °                ½      ö               X   +           Õ   3           O   �   c           ¡     °            V           0  l      vpp-merge@1c10c000            mediatek,mt8195-disp-merge          T    À                ½      ÷               X   +   	   +           'merge merge_async           Õ   3              ¡     À             Ž           +           0  m      vpp-merge@1c10d000            mediatek,mt8195-disp-merge          T    Ð                ½      ø               X   +   
   +           'merge merge_async           Õ   3              ¡     Ð             Ž           +           0  n      vpp-merge@1c10e000            mediatek,mt8195-disp-merge          T    à                ½      ù               X   +      +           'merge merge_async           Õ   3              ¡     à             Ž           +           0  o      vpp-merge@1c10f000            mediatek,mt8195-disp-merge          T    ð                ½      ú               X   +      +           'merge merge_async           Õ   3              ¡     ð             Ž           +           0  p      vpp-merge@1c110000            mediatek,mt8195-disp-merge          T                     ½      û               X   +      +           'merge merge_async           Õ   3              ¡                   ¢           +           0  q   ports                        +       port@0                       +            T       endpoint@1          T           	l   Á        0   Æ         port@1                       +            T      endpoint@1          T           	l   Â        0   Ã               dpi@1c112000              mediatek,mt8195-dpi         T                     X   +   -   +      +   2        'pixel engine pll            ½                      Õ   3              +           Íokay            0  r   ports                        +       port@0          T       endpoint            	l   Ã        0   Â         port@1          T      endpoint            	l   Ä        0   É               dp-intf@1c113000              mediatek,mt8195-dp-intf         T    0                ½                     Õ   3           X   +   /   +                 'pixel engine pll          	  Ídisabled            0  s      hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  T    @            P            p            �                         °            À              4  &mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p     ¡     @       ¡     P       ¡     p       ¡     �       ¡             ¡     °       ¡     À          h  X   +   %   +       +   #   +   !   +   $   +   "   +   1   +   &   +   '   +   (   +   )   +   *            ƒ  'mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          Õ   3           O   �   d   �   e        ½                   (     +   3   +   4   +   5   +   6   +   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async            0  t   ports                        +       port@0                       +            T       endpoint@1          T           	l   Å        0   ²         port@1                       +            T      endpoint@1          T           	l   Æ        0   Á               hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx         „           T    0                  X      Q      L      M   $   ,        'bus hdcp hdcp24m hdmi-split         ]      L        m      “        ½      ¥               Õ   3           	   Ç        
Ýhdmi            Íokay            default            È        0      i2c           mediatek,mt8195-hdmi-ddc            X           0   Ö      ports                        +       port@0          T       endpoint            	l   É        0   Ä         port@1          T      endpoint            	l   Ê        0   ×               edp-tx@1c500000           mediatek,mt8195-edp-tx          T    P        €            Ë        &dp_calibration_data         Õ   3           ½      ¤               ¹  ¤      	  Ídisabled            0  u      dp-tx@1c600000            mediatek,mt8195-dp-tx           T    `        €            Ë        &dp_calibration_data         Õ   3           ½      Ê               ¹  ¤      	  Ídisabled            0  v         thermal-zones           0  w   cpu0-thermal            Ê  è        Ø   ú        î   Ì      trips      trip-alert          þ L        
  Ð         Epassive         0   Í      trip-crit           þ †         
  Ð      	   Ecritical            0  x         cooling-maps       map0               Í      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            Ê  è        Ø   ú        î   Ì      trips      trip-alert          þ L        
  Ð         Epassive         0   Î      trip-crit           þ †         
  Ð      	   Ecritical            0  y         cooling-maps       map0               Î      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            Ê  è        Ø   ú        î   Ì      trips      trip-alert          þ L        
  Ð         Epassive         0   Ï      trip-crit           þ †         
  Ð      	   Ecritical            0  z         cooling-maps       map0               Ï      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            Ê  è        Ø   ú        î   Ì      trips      trip-alert          þ L        
  Ð         Epassive         0   Ð      trip-crit           þ †         
  Ð      	   Ecritical            0  {         cooling-maps       map0               Ð      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            Ê  è        Ø   ú        î   Ì       trips      trip-alert          þ L        
  Ð         Epassive         0   Ñ      trip-crit           þ †         
  Ð      	   Ecritical            0  |         cooling-maps       map0               Ñ      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            Ê  è        Ø   ú        î   Ì      trips      trip-alert          þ L        
  Ð         Epassive         0   Ò      trip-crit           þ †         
  Ð      	   Ecritical            0  }         cooling-maps       map0               Ò      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            Ê  è        Ø   ú        î   Ì      trips      trip-alert          þ L        
  Ð         Epassive         0   Ó      trip-crit           þ †         
  Ð      	   Ecritical            0  ~         cooling-maps       map0               Ó      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            Ê  è        Ø   ú        î   Ì      trips      trip-alert          þ L        
  Ð         Epassive         0   Ô      trip-crit           þ †         
  Ð      	   Ecritical            0           cooling-maps       map0               Ô      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            Ê  è        Ø   ú        î   Õ      trips      trip-alert          þ L        
  Ð         Epassive         0  €      trip-crit           þ †         
  Ð      	   Ecritical            0  �            vpu1-thermal            Ê  è        Ø   ú        î   Õ   	   trips      trip-alert          þ L        
  Ð         Epassive         0  ‚      trip-crit           þ †         
  Ð      	   Ecritical            0  ƒ            gpu-thermal         Ê  è        Ø   ú        î   Õ   
   trips      trip-alert          þ L        
  Ð         Epassive         0  „      trip-crit           þ †         
  Ð      	   Ecritical            0  …            gpu1-thermal            Ê  è        Ø   ú        î   Õ      trips      trip-alert          þ L        
  Ð         Epassive         0  †      trip-crit           þ †         
  Ð      	   Ecritical            0  ‡            vdec-thermal            Ê  è        Ø   ú        î   Õ      trips      trip-alert          þ L        
  Ð         Epassive         0  ˆ      trip-crit           þ †         
  Ð      	   Ecritical            0  ‰            img-thermal         Ê  è        Ø   ú        î   Õ      trips      trip-alert          þ L        
  Ð         Epassive         0  Š      trip-crit           þ †         
  Ð      	   Ecritical            0  ‹            infra-thermal           Ê  è        Ø   ú        î   Õ      trips      trip-alert          þ L        
  Ð         Epassive         0  Œ      trip-crit           þ †         
  Ð      	   Ecritical            0  �            cam0-thermal            Ê  è        Ø   ú        î   Õ      trips      trip-alert          þ L        
  Ð         Epassive         0  Ž      trip-crit           þ †         
  Ð      	   Ecritical            0  �            cam1-thermal            Ê  è        Ø   ú        î   Õ      trips      trip-alert          þ L        
  Ð         Epassive         0  �      trip-crit           þ †         
  Ð      	   Ecritical            0  ‘               chosen          )serial0:921600n8          connector             hdmi-connector          Qhdmi             Ea           5   Ö        A   Ç   port       endpoint            	l   ×        0   Ê            firmware       optee             linaro,optee-tz         _smc          memory@40000000         Hmemory          T    @                backlight             pwm-backlight           Q      ÿ        c  @        |      k            ‰  ÿ        default            Ø            Ù     ¡         Íokay led        0  ’      gpio-keys         
    gpio-keys           0  “   button-volume-up             ’        ¥   d        
-      j         
  Qvolume_up           ·   s         regulator-wifi-3v3-en             regulator-fixed         »wifi_3v3_en                  Ê 2Z         â 2Z          Â        5      C            default            Ú        Õ   X        0  ”      regulator-vsys            regulator-fixed         »vsys                      à        Ê LK@        â LK@        Õ   Û        0   X      regulator-vsys-buck           regulator-fixed       
  »vsys_buck                     à        Ê LK@        â LK@        Õ   Û        0   f      regulator-vcc5v0-sys              regulator-fixed         »vcc5v0_sys                    à        0   Û      reserved-memory                      +            Á   optee@43200000          T    C        À           ò        0  •      memory@50000000           shared-dma-pool         T    P       �           ò        0   1      memory@53000000           shared-dma-pool         T    S       @          0  –      memory@54600000         T    T`                   ò        0  —      memory@60000000           shared-dma-pool         T    `        ð           ò        0   7      memory@60f00000           shared-dma-pool         T    `ð                  ò        0   9      memory@61000000           shared-dma-pool         T    a                   ò        0   6      memory@62000000           shared-dma-pool         T    b       @          0  ˜         __symbols__         ù/cpus/cpu@0         þ/cpus/cpu@100           /cpus/cpu@200           /cpus/cpu@300           /cpus/cpu@400           /cpus/cpu@500           /cpus/cpu@600           /cpus/cpu@700         "  !/cpus/idle-states/cpu-retention-l         "  +/cpus/idle-states/cpu-retention-b           5/cpus/idle-states/cpu-off-l         ?/cpus/idle-states/cpu-off-b         I/cpus/l2-cache0         N/cpus/l2-cache1         S/cpus/l3-cache          X/dmic-codec         c/mt8195-sound           i/fixed-factor-clock-13m         p/oscillator-26m         w/oscillator-32k         ~/performance-controller@11bc10          Š/opp-table-gpu          ˜/timer        "  ž/soc/interrupt-controller@c000000         G  ¢/soc/interrupt-controller@c000000/ppi-partitions/interrupt-partition-0        G  ¯/soc/interrupt-controller@c000000/ppi-partitions/interrupt-partition-1          þ/soc/syscon@10000000            ¼/soc/syscon@10001000            …/soc/syscon@10003000            6/soc/pinctrl@10005000         )  È/soc/pinctrl@10005000/audio-default-pins          *  Û/soc/pinctrl@10005000/dsi0-backlight-pins         '  ï/soc/pinctrl@10005000/eth-default-pins        %   /soc/pinctrl@10005000/eth-sleep-pins          %  /soc/pinctrl@10005000/gpio-keys-pins          %  /soc/pinctrl@10005000/hdmi-vreg-pins             ,/soc/pinctrl@10005000/hdmi-pins          6/soc/pinctrl@10005000/i2c2-pins          @/soc/pinctrl@10005000/i2c4-pins          J/soc/pinctrl@10005000/i2c6-pins       (  T/soc/pinctrl@10005000/mmc0-default-pins       $  f/soc/pinctrl@10005000/mmc0-uhs-pins       (  t/soc/pinctrl@10005000/mmc1-default-pins       '  †/soc/pinctrl@10005000/mmc1-detect-pins        "  —/soc/pinctrl@10005000/mt6360-pins         !  £/soc/pinctrl@10005000/panel-pins          )  ¶/soc/pinctrl@10005000/pcie0-default-pins          )  É/soc/pinctrl@10005000/pcie1-default-pins             Ü/soc/pinctrl@10005000/pwm0-pins       (  î/soc/pinctrl@10005000/spi1-default-pins       (  ø/soc/pinctrl@10005000/spi2-default-pins       !  /soc/pinctrl@10005000/touch-pins          !  /soc/pinctrl@10005000/uart0-pins          !  /soc/pinctrl@10005000/uart1-pins          *  #/soc/pinctrl@10005000/usb3p0-default-pins         *  3/soc/pinctrl@10005000/usb2p0-default-pins         %  C/soc/pinctrl@10005000/wifi-vreg-pins            R/soc/syscon@10006000          &  Y/soc/syscon@10006000/power-controller         5  ]/soc/syscon@10006000/power-controller/power-domain@8          D  b/soc/syscon@10006000/power-controller/power-domain@8/power-domain@9         g/soc/watchdog@10007000          p/soc/syscon@1000c000            {/soc/timer@10017000         „/soc/pwrap@10024000         Š/soc/pwrap@10024000/pmic            �/soc/pwrap@10024000/pmic/adc          %  ˜/soc/pwrap@10024000/pmic/audio-codec          -  ¤/soc/pwrap@10024000/pmic/regulators/buck_vs1          0  ¸/soc/pwrap@10024000/pmic/regulators/buck_vgpu11       0  Ï/soc/pwrap@10024000/pmic/regulators/buck_vmodem       -  æ/soc/pwrap@10024000/pmic/regulators/buck_vpu          /  ú/soc/pwrap@10024000/pmic/regulators/buck_vcore        -  /soc/pwrap@10024000/pmic/regulators/buck_vs2          -  $/soc/pwrap@10024000/pmic/regulators/buck_vpa          0  8/soc/pwrap@10024000/pmic/regulators/buck_vproc2       0  O/soc/pwrap@10024000/pmic/regulators/buck_vproc1       5  f/soc/pwrap@10024000/pmic/regulators/buck_vcore_sshub          6  ‚/soc/pwrap@10024000/pmic/regulators/buck_vgpu11_sshub         /  Ÿ/soc/pwrap@10024000/pmic/regulators/ldo_vaud18        .  µ/soc/pwrap@10024000/pmic/regulators/ldo_vsim1         -  Ê/soc/pwrap@10024000/pmic/regulators/ldo_vibr          .  Þ/soc/pwrap@10024000/pmic/regulators/ldo_vrf12         -  ó/soc/pwrap@10024000/pmic/regulators/ldo_vusb          4  /soc/pwrap@10024000/pmic/regulators/ldo_vsram_proc2       .  "/soc/pwrap@10024000/pmic/regulators/ldo_vio18         /  7/soc/pwrap@10024000/pmic/regulators/ldo_vcamio        .  M/soc/pwrap@10024000/pmic/regulators/ldo_vcn18         .  b/soc/pwrap@10024000/pmic/regulators/ldo_vfe28         .  w/soc/pwrap@10024000/pmic/regulators/ldo_vcn13         3  Œ/soc/pwrap@10024000/pmic/regulators/ldo_vcn33_1_bt        5  ¦/soc/pwrap@10024000/pmic/regulators/ldo_vcn33_1_wifi          /  Â/soc/pwrap@10024000/pmic/regulators/ldo_vaux18        5  Ø/soc/pwrap@10024000/pmic/regulators/ldo_vsram_others          /  ô/soc/pwrap@10024000/pmic/regulators/ldo_vefuse        .  
/soc/pwrap@10024000/pmic/regulators/ldo_vxo22         .  /soc/pwrap@10024000/pmic/regulators/ldo_vrfck         0  4/soc/pwrap@10024000/pmic/regulators/ldo_vrfck_1       /  K/soc/pwrap@10024000/pmic/regulators/ldo_vbif28        .  a/soc/pwrap@10024000/pmic/regulators/ldo_vio28         -  v/soc/pwrap@10024000/pmic/regulators/ldo_vemc          /  Š/soc/pwrap@10024000/pmic/regulators/ldo_vemc_1        3   /soc/pwrap@10024000/pmic/regulators/ldo_vcn33_2_bt        5  º/soc/pwrap@10024000/pmic/regulators/ldo_vcn33_2_wifi          -  Ö/soc/pwrap@10024000/pmic/regulators/ldo_va12          -  ê/soc/pwrap@10024000/pmic/regulators/ldo_va09          .  þ/soc/pwrap@10024000/pmic/regulators/ldo_vrf18         1  /soc/pwrap@10024000/pmic/regulators/ldo_vsram_md          -  +/soc/pwrap@10024000/pmic/regulators/ldo_vufs          -  ?/soc/pwrap@10024000/pmic/regulators/ldo_vm18          .  S/soc/pwrap@10024000/pmic/regulators/ldo_vbbck         4  h/soc/pwrap@10024000/pmic/regulators/ldo_vsram_proc1       .  ƒ/soc/pwrap@10024000/pmic/regulators/ldo_vsim2         ;  ˜/soc/pwrap@10024000/pmic/regulators/ldo_vsram_others_sshub          ¶/soc/pwrap@10024000/pmic/rtc            À/soc/pwrap@10024000/pmic/keys           Ë/soc/spmi@10027000          Ð/soc/spmi@10027000/pmic@6         ,  Ù/soc/spmi@10027000/pmic@6/regulators/vbuck1         é/soc/spmi@10027000/pmic@7         ,  ò/soc/spmi@10027000/pmic@7/regulators/vbuck1         /soc/infra-iommu@10315000            a/soc/mailbox@10320000            f/soc/mailbox@10330000           K/soc/scp@10500000           /soc/clock-controller@10720000          2/soc/dsp@10803000           /soc/mailbox@10816000           %/soc/mailbox@10817000           3/soc/mt8195-afe-pcm@10890000            7/soc/serial@11001100            =/soc/serial@11001200            C/soc/serial@11001300            I/soc/serial@11001400            O/soc/serial@11001500            U/soc/serial@11001600            [/soc/auxadc@11002000            b/soc/syscon@11003000            >/soc/spi@1100a000           m/soc/thermal-sensor@1100b000            u/soc/svs@1100bc00           y/soc/pwm@1100e000           ƒ/soc/pwm@1100f000           C/soc/spi@11010000           �/soc/spi@11012000           ’/soc/spi@11013000           —/soc/spi@11018000           œ/soc/spi@11019000           ¡/soc/spi@1101d000           §/soc/spi@1101e000           ­/soc/ethernet@11021000        +  ±/soc/ethernet@11021000/mdio/ethernet-phy@1        )  »/soc/ethernet@11021000/stmmac-axi-config          (  Ì/soc/ethernet@11021000/rx-queues-config       (  Ù/soc/ethernet@11021000/tx-queues-config         æ/soc/usb@11201000           í/soc/usb@11201000/usb@0          ó/soc/usb@11201000/port/endpoint         $/soc/mmc@11230000           )/soc/mmc@11240000           /soc/mmc@11250000           	/soc/ufshci@11270000            /soc/thermal-sensor@11278000            /soc/usb@11290000           /soc/usb@112a1000           &/soc/usb@112a1000/usb@0         ,/soc/usb@112b1000           3/soc/usb@112b1000/usb@0         9/soc/pcie@112f0000        (  ?/soc/pcie@112f0000/interrupt-controller         J/soc/pcie@112f8000        (  P/soc/pcie@112f8000/interrupt-controller         [/soc/spi@1132c000           e/soc/efuse@11c10000       &  k/soc/efuse@11c10000/usb3-tx-imp@184,1         &  x/soc/efuse@11c10000/usb3-rx-imp@184,2         "  …/soc/efuse@11c10000/usb3-intr@185         &  �/soc/efuse@11c10000/usb3-tx-imp@186,1         &  Ÿ/soc/efuse@11c10000/usb3-rx-imp@186,2         "  ®/soc/efuse@11c10000/usb3-intr@187         '  »/soc/efuse@11c10000/usb2-intr-p0@188,1        '  Æ/soc/efuse@11c10000/usb2-intr-p1@188,2        '  Ñ/soc/efuse@11c10000/usb2-intr-p2@189,1        '  Ü/soc/efuse@11c10000/usb2-intr-p3@189,2        )  ç/soc/efuse@11c10000/pciephy-rx-ln1@190,1          .  ö/soc/efuse@11c10000/pciephy-tx-ln1-nmos@190,2         .  
/soc/efuse@11c10000/pciephy-tx-ln1-pmos@191,1         )  /soc/efuse@11c10000/pciephy-rx-ln0@191,2          .  -/soc/efuse@11c10000/pciephy-tx-ln0-nmos@192,1         .  A/soc/efuse@11c10000/pciephy-tx-ln0-pmos@192,2         )  U/soc/efuse@11c10000/pciephy-glb-intr@193             f/soc/efuse@11c10000/dp-data@1ac       $  u/soc/efuse@11c10000/lvts1-calib@1bc       $  †/soc/efuse@11c10000/lvts2-calib@1d0       "  —/soc/efuse@11c10000/svs-calib@580           ¦/soc/t-phy@11c40000         ­/soc/t-phy@11c40000/usb-phy@0           µ/soc/t-phy@11c50000         ¼/soc/t-phy@11c50000/usb-phy@0           Ä/soc/dsi-phy@11c80000           Í/soc/dsi-phy@11c90000           Ö/soc/i2c@11d00000           Û/soc/i2c@11d01000           à/soc/i2c@11d01000/pmic@34         9  ç/soc/i2c@11d01000/pmic@34/charger/usb-otg-vbus-regulator          *  ú/soc/i2c@11d01000/pmic@34/regulator/buck1         *  /soc/i2c@11d01000/pmic@34/regulator/buck2         )  /soc/i2c@11d01000/pmic@34/regulator/ldo1          )   /soc/i2c@11d01000/pmic@34/regulator/ldo2          )  ,/soc/i2c@11d01000/pmic@34/regulator/ldo3          )  8/soc/i2c@11d01000/pmic@34/regulator/ldo5          )  D/soc/i2c@11d01000/pmic@34/regulator/ldo6          )  P/soc/i2c@11d01000/pmic@34/regulator/ldo7          @  \/soc/i2c@11d01000/pmic@34/typec/connector/ports/port@0/endpoint       @  i/soc/i2c@11d01000/pmic@34/typec/connector/ports/port@2/endpoint         w/soc/i2c@11d02000           |/soc/clock-controller@11d03000          ‹/soc/hdmi-phy@11d5f000          /soc/i2c@11e00000           /soc/i2c@11e01000           /soc/i2c@11e02000         -  ”/soc/i2c@11e02000/typec-mux@48/port/endpoint            /soc/i2c@11e03000           /soc/i2c@11e04000           £/soc/clock-controller@11e05000          ²/soc/t-phy@11e30000         ¹/soc/t-phy@11e30000/usb-phy@0            Á/soc/t-phy@11e30000/usb-phy@700         É/soc/t-phy@11e40000         Ð/soc/t-phy@11e40000/usb-phy@0            Ø/soc/t-phy@11e40000/usb-phy@700         à/soc/phy@11e80000           è/soc/ufs-phy@11fa0000           ï/soc/gpu@13000000           ó/soc/clock-controller@13fbf000          ú/soc/syscon@14000000            /soc/smi@14010000           /soc/smi@14011000           </soc/smi@14012000           K/soc/larb@14013000          Q/soc/iommu@14018000         [/soc/clock-controller@14e00000          b/soc/clock-controller@14e02000          n/soc/clock-controller@14e03000          z/soc/larb@14e04000          €/soc/larb@14e05000          †/soc/syscon@14f00000            Ž/soc/larb@14f02000          ”/soc/larb@14f03000          š/soc/clock-controller@15000000          ¡/soc/larb@15001000          §/soc/smi@15002000           ¿/soc/smi@15003000           ×/soc/clock-controller@15110000          ç/soc/larb@15120000          î/soc/clock-controller@15130000          ý/soc/clock-controller@15220000          	/soc/larb@15230000          /soc/clock-controller@15330000          /soc/larb@15340000          /soc/clock-controller@16000000          %/soc/larb@16001000          ,/soc/larb@16002000          3/soc/smi@16004000           J/soc/smi@16005000           a/soc/larb@16012000          h/soc/larb@16013000          o/soc/larb@16014000          v/soc/larb@16015000          }/soc/clock-controller@1604f000          ‰/soc/clock-controller@1606f000          •/soc/clock-controller@1608f000          ¡/soc/clock-controller@160af000          ­/soc/clock-controller@16140000          ¹/soc/larb@16141000          À/soc/larb@16142000          Ç/soc/clock-controller@17200000          Î/soc/larb@17201000          Õ/soc/larb@1800d000          Ü/soc/larb@1800e000          ã/soc/clock-controller@1800f000          ï/soc/larb@1802e000          ö/soc/clock-controller@1802f000          þ/soc/larb@1803e000          /soc/clock-controller@1803f000          /soc/clock-controller@190f3000          /soc/clock-controller@1a000000          &/soc/larb@1a010000          -/soc/video-codec@1a020000           2/soc/clock-controller@1b000000          @/soc/syscon@1c01a000            H/soc/larb@1b010000          O/soc/ovl@1c000000         (  T/soc/ovl@1c000000/ports/port@0/endpoint       (  \/soc/ovl@1c000000/ports/port@1/endpoint          ®/soc/rdma@1c002000        )  e/soc/rdma@1c002000/ports/port@0/endpoint          )  n/soc/rdma@1c002000/ports/port@1/endpoint            x/soc/color@1c003000       *  /soc/color@1c003000/ports/port@0/endpoint         *  ‰/soc/color@1c003000/ports/port@1/endpoint           ”/soc/ccorr@1c004000       *  ›/soc/ccorr@1c004000/ports/port@0/endpoint         *  ¥/soc/ccorr@1c004000/ports/port@1/endpoint           °/soc/aal@1c005000         (  µ/soc/aal@1c005000/ports/port@0/endpoint       (  ½/soc/aal@1c005000/ports/port@1/endpoint         Æ/soc/gamma@1c006000       *  Í/soc/gamma@1c006000/ports/port@0/endpoint         *  ×/soc/gamma@1c006000/ports/port@1/endpoint           â/soc/dither@1c007000          +  ê/soc/dither@1c007000/ports/port@0/endpoint        +  õ/soc/dither@1c007000/ports/port@1/endpoint          /soc/dsi@1c008000         (  /soc/dsi@1c008000/ports/port@0/endpoint       (  /soc/dsi@1c008000/ports/port@1/endpoint         /soc/dsc@1c009000           /soc/dsi@1c012000           !/soc/merge@1c014000         (/soc/dp-intf@1c015000           1/soc/mutex@1c016000         7/soc/larb@1c018000          =/soc/larb@1c019000          C/soc/syscon@1c100000          %  K/soc/syscon@1c100000/port/endpoint@1            Z/soc/smi@1c01b000           i/soc/iommu@1c01f000          /soc/mutex@1c101000         s/soc/larb@1c102000          y/soc/larb@1c103000          /soc/dma-controller@1c104000            Š/soc/dma-controller@1c105000            •/soc/dma-controller@1c106000             /soc/dma-controller@1c107000            «/soc/dma-controller@1c108000            ¶/soc/dma-controller@1c109000            Á/soc/dma-controller@1c10a000            Ì/soc/dma-controller@1c10b000             †/soc/vpp-merge@1c10c000          �/soc/vpp-merge@1c10d000          ”/soc/vpp-merge@1c10e000          ›/soc/vpp-merge@1c10f000          ¢/soc/vpp-merge@1c110000       0  ×/soc/vpp-merge@1c110000/ports/port@0/endpoint@1       0  á/soc/vpp-merge@1c110000/ports/port@1/endpoint@1          \/soc/dpi@1c112000         (  ì/soc/dpi@1c112000/ports/port@0/endpoint       (  ô/soc/dpi@1c112000/ports/port@1/endpoint         ý/soc/dp-intf@1c113000            q/soc/hdr-engine@1c114000          1  /soc/hdr-engine@1c114000/ports/port@0/endpoint@1          1  /soc/hdr-engine@1c114000/ports/port@1/endpoint@1            /soc/hdmi-tx@1c300000            /soc/hdmi-tx@1c300000/i2c         ,  +/soc/hdmi-tx@1c300000/ports/port@0/endpoint       ,  4/soc/hdmi-tx@1c300000/ports/port@1/endpoint         >/soc/edp-tx@1c500000            ?/soc/dp-tx@1c600000         E/thermal-zones        -  S/thermal-zones/cpu0-thermal/trips/trip-alert          ,  ^/thermal-zones/cpu0-thermal/trips/trip-crit       -  h/thermal-zones/cpu1-thermal/trips/trip-alert          ,  s/thermal-zones/cpu1-thermal/trips/trip-crit       -  }/thermal-zones/cpu2-thermal/trips/trip-alert          ,  ˆ/thermal-zones/cpu2-thermal/trips/trip-crit       -  ’/thermal-zones/cpu3-thermal/trips/trip-alert          ,  �/thermal-zones/cpu3-thermal/trips/trip-crit       -  §/thermal-zones/cpu4-thermal/trips/trip-alert          ,  ²/thermal-zones/cpu4-thermal/trips/trip-crit       -  ¼/thermal-zones/cpu5-thermal/trips/trip-alert          ,  Ç/thermal-zones/cpu5-thermal/trips/trip-crit       -  Ñ/thermal-zones/cpu6-thermal/trips/trip-alert          ,  Ü/thermal-zones/cpu6-thermal/trips/trip-crit       -  æ/thermal-zones/cpu7-thermal/trips/trip-alert          ,  ñ/thermal-zones/cpu7-thermal/trips/trip-crit       -  û/thermal-zones/vpu0-thermal/trips/trip-alert          ,  /thermal-zones/vpu0-thermal/trips/trip-crit       -  /thermal-zones/vpu1-thermal/trips/trip-alert          ,  /thermal-zones/vpu1-thermal/trips/trip-crit       ,  %/thermal-zones/gpu-thermal/trips/trip-alert       +  0/thermal-zones/gpu-thermal/trips/trip-crit        -  :/thermal-zones/gpu1-thermal/trips/trip-alert          ,  E/thermal-zones/gpu1-thermal/trips/trip-crit       -  O/thermal-zones/vdec-thermal/trips/trip-alert          ,  Z/thermal-zones/vdec-thermal/trips/trip-crit       ,  d/thermal-zones/img-thermal/trips/trip-alert       +  n/thermal-zones/img-thermal/trips/trip-crit        .  w/thermal-zones/infra-thermal/trips/trip-alert         -  ƒ/thermal-zones/infra-thermal/trips/trip-crit          -  Ž/thermal-zones/cam0-thermal/trips/trip-alert          ,  ™/thermal-zones/cam0-thermal/trips/trip-crit       -  £/thermal-zones/cam1-thermal/trips/trip-alert          ,  ®/thermal-zones/cam1-thermal/trips/trip-crit         ¸/connector/port/endpoint            Ê/backlight          Æ/gpio-keys          Ô/regulator-wifi-3v3-en          Þ/regulator-vsys         ã/regulator-vsys-buck            í/regulator-vcc5v0-sys            ù/reserved-memory/optee@43200000       !  /reserved-memory/memory@50000000          !  /reserved-memory/memory@53000000          !  /reserved-memory/memory@54600000          !  (/reserved-memory/memory@60000000          !  1/reserved-memory/memory@60f00000          !  =/reserved-memory/memory@61000000          !  J/reserved-memory/memory@62000000             	compatible interrupt-parent #address-cells #size-cells model chassis-type dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 ethernet0 i2c0 i2c1 i2c2 i2c3 i2c4 mmc0 mmc1 serial0 serial1 spi0 spi1 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform pinctrl-names pinctrl-0 audio-routing mediatek,adsp link-name sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit pinmux output-high drive-strength input-enable bias-disable input-disable bias-pull-up bias-pull-down drive-strength-microamp output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,tx-delay-ps mediatek,mac-wol snps,reset-gpio snps,reset-delays-us snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup role-switch-default-mode usb-role-switch vusb33-supply vbus-supply remote-endpoint bus-width max-frequency hs400-ds-delay cap-mmc-highspeed cap-mmc-hw-reset mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 freq-table-hz mediatek,ufs-disable-mcq vcc-supply vccq2-supply usb2-lpm-disable mediatek,u3p-dis-msk bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN1-supply LDO_VIN3-supply label data-role op-sink-microwatt power-role try-power-role source-pdos sink-pdos mediatek,ibias mediatek,ibias_up mode-switch orientation-switch operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path ddc-i2c-bus hdmi-pwr-supply brightness-levels default-brightness-level enable-gpios num-interpolated-steps pwms debounce-interval linux,code enable-active-high vin-supply regulator-boot-on no-map cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_ret_l cpu_ret_b cpu_off_l cpu_off_b l2_0 l2_1 l3_0 dmic_codec sound clk13m clk26m clk32k performance gpu_opp_table timer gic ppi_cluster0 ppi_cluster1 infracfg_ao audio_default_pins dsi0_backlight_pins eth_default_pins eth_sleep_pins gpio_key_pins hdmi_vreg_pins hdmi_pins i2c2_pins i2c4_pins i2c6_pins mmc0_default_pins mmc0_uhs_pins mmc1_default_pins mmc1_pins_detect mt6360_pins panel_default_pins pcie0_default_pins pcie1_default_pins pwm0_default_pins spi1_pins spi2_pins touch_pins uart0_pins uart1_pins usb3_port0_pins usb2_port0_pins wifi_vreg_pins scpsys spm mfg0 mfg1 watchdog apmixedsys systimer pwrap pmic pmic_adc mt6359codec mt6359_vs1_buck_reg mt6359_vgpu11_buck_reg mt6359_vmodem_buck_reg mt6359_vpu_buck_reg mt6359_vcore_buck_reg mt6359_vs2_buck_reg mt6359_vpa_buck_reg mt6359_vproc2_buck_reg mt6359_vproc1_buck_reg mt6359_vcore_sshub_buck_reg mt6359_vgpu11_sshub_buck_reg mt6359_vaud18_ldo_reg mt6359_vsim1_ldo_reg mt6359_vibr_ldo_reg mt6359_vrf12_ldo_reg mt6359_vusb_ldo_reg mt6359_vsram_proc2_ldo_reg mt6359_vio18_ldo_reg mt6359_vcamio_ldo_reg mt6359_vcn18_ldo_reg mt6359_vfe28_ldo_reg mt6359_vcn13_ldo_reg mt6359_vcn33_1_bt_ldo_reg mt6359_vcn33_1_wifi_ldo_reg mt6359_vaux18_ldo_reg mt6359_vsram_others_ldo_reg mt6359_vefuse_ldo_reg mt6359_vxo22_ldo_reg mt6359_vrfck_ldo_reg mt6359_vrfck_1_ldo_reg mt6359_vbif28_ldo_reg mt6359_vio28_ldo_reg mt6359_vemc_ldo_reg mt6359_vemc_1_ldo_reg mt6359_vcn33_2_bt_ldo_reg mt6359_vcn33_2_wifi_ldo_reg mt6359_va12_ldo_reg mt6359_va09_ldo_reg mt6359_vrf18_ldo_reg mt6359_vsram_md_ldo_reg mt6359_vufs_ldo_reg mt6359_vm18_ldo_reg mt6359_vbbck_ldo_reg mt6359_vsram_proc1_ldo_reg mt6359_vsim2_ldo_reg mt6359_vsram_others_sshub_ldo mt6359rtc mt6359keys spmi mt6315_6 mt6315_6_vbuck1 mt6315_7 mt6315_7_vbuck1 iommu_infra scp_adsp adsp_mailbox0 adsp_mailbox1 afe uart0 uart1 uart2 uart3 uart4 uart5 auxadc pericfg_ao lvts_ap svs disp_pwm0 disp_pwm1 spi2 spi3 spi4 spi5 spis0 spis1 eth rgmii_phy stmmac_axi_setup mtl_rx_setup mtl_tx_setup ssusb0 xhci0 mtu3_hs0_role_sw mmc2 ufshci lvts_mcu xhci1 ssusb2 xhci2 ssusb3 xhci3 pcie0 pcie_intc0 pcie1 pcie_intc1 nor_flash efuse u3_tx_imp_p0 u3_rx_imp_p0 u3_intr_p0 comb_tx_imp_p1 comb_rx_imp_p1 comb_intr_p1 u2_intr_p0 u2_intr_p1 u2_intr_p2 u2_intr_p3 pciephy_rx_ln1 pciephy_tx_ln1_nmos pciephy_tx_ln1_pmos pciephy_rx_ln0 pciephy_tx_ln0_nmos pciephy_tx_ln0_pmos pciephy_glb_intr dp_calibration lvts_efuse_data1 lvts_efuse_data2 svs_calib_data u3phy2 u2port2 u3phy3 u2port3 mipi_tx0 mipi_tx1 i2c5 i2c6 mt6360 otg_vbus_regulator mt6360_buck1 mt6360_buck2 mt6360_ldo1 mt6360_ldo2 mt6360_ldo3 mt6360_ldo5 mt6360_ldo6 mt6360_ldo7 typec_con_hs typec_con_mux i2c7 imp_iic_wrap_s hdmi_phy it5205_sbu_mux imp_iic_wrap_w u3phy1 u2port1 u3port1 u3phy0 u2port0 u3port0 pciephy ufsphy gpu mfgcfg vppsys0 smi_sub_common_vpp0_vpp1_2x1 smi_sub_common_vdec_vpp0_2x1 smi_common_vpp larb4 iommu_vpp wpesys wpesys_vpp0 wpesys_vpp1 larb7 larb8 vppsys1 larb5 larb6 imgsys larb9 smi_sub_common_img0_3x1 smi_sub_common_img1_3x1 imgsys1_dip_top larb10 imgsys1_dip_nr imgsys1_wpe larb11 ipesys larb12 camsys larb13 larb14 smi_sub_common_cam_4x1 smi_sub_common_cam_7x1 larb16 larb17 larb27 larb28 camsys_rawa camsys_yuva camsys_rawb camsys_yuvb camsys_mraw larb25 larb26 ccusys larb18 larb24 larb23 vdecsys_soc larb21 vdecsys larb22 vdecsys_core1 apusys_pll vencsys larb19 venc vencsys_core1 vdosys0 larb20 ovl0 ovl0_in ovl0_out rdma0_in rdma0_out color0 color0_in color0_out ccorr0 ccorr0_in ccorr0_out aal0 aal0_in aal0_out gamma0 gamma0_in gamma0_out dither0 dither0_in dither0_out dsi0 dsi0_in dsi0_out dsc0 dsi1 merge0 dp_intf0 mutex larb0 larb1 vdosys1 vdosys1_ep_ext smi_common_vdo iommu_vdo larb2 larb3 vdo1_rdma0 vdo1_rdma1 vdo1_rdma2 vdo1_rdma3 vdo1_rdma4 vdo1_rdma5 vdo1_rdma6 vdo1_rdma7 merge5_in merge5_out dpi1_in dpi1_out dp_intf1 ethdr0_in ethdr0_out hdmi hdmitx_ddc hdmi0_in hdmi0_out edp_tx thermal_zones cpu0_alert cpu0_crit cpu1_alert cpu1_crit cpu2_alert cpu2_crit cpu3_alert cpu3_crit cpu4_alert cpu4_crit cpu5_alert cpu5_crit cpu6_alert cpu6_crit cpu7_alert cpu7_crit vpu0_alert vpu0_crit vpu1_alert vpu1_crit gpu0_alert gpu0_crit gpu1_alert gpu1_crit vdec_alert vdec_crit img_alert img_crit infra_alert infra_crit cam0_alert cam0_crit cam1_alert cam1_crit hdmi_connector_in backlight wifi_vreg vsys vsys_buck vcc5v0_vsys optee_reserved scp_mem vpu_mem bl31_secmon_mem adsp_mem afe_dma_mem adsp_dma_mem apu_mem vdd-supply vccio-supply reset-gpios irq-gpios VDDIO-supply 