8( 9tsd,px30-cobra-ltk500hd1829tsd,px30-cobrarockchip,px30 +<7Theobroma Systems Cobra prototype with LTK500HD1829 Displayaliases=/i2c@ff180000B/i2c@ff190000G/i2c@ff1a0000L/i2c@ff1b0000Q/serial@ff030000Y/serial@ff158000a/serial@ff160000i/serial@ff168000q/serial@ff170000y/serial@ff178000/spi@ff1d0000/spi@ff1d8000/ethernet@ff360000/mmc@ff390000/mmc@ff370000cpus+cpu@0cpuarm,cortex-a35psciZcpu@1cpuarm,cortex-a35psciZcpu@2cpuarm,cortex-a35psciZ cpu@3cpuarm,cortex-a35psciZ idle-states$pscicpu-sleeparm,idle-state1BYxjzcluster-sleeparm,idle-state1BYjzopp-table-0operating-points-v2opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem okayexternal-gmac-clock fixed-clock gmac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal#9GY tripstrip-point-0ipupassivetrip-point-1iLupassivesoc-criti8u criticalcooling-mapsmap0 gpu-thermal#d9Y tripsgpu-thresholdipupassivegpu-targetiLupassivegpu-criti8u criticalcooling-mapsmap0 xin24m fixed-clockn6xin24mmpower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+opower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfdio-domains$rockchip,px30-pmu-io-voltage-domainokay%%reboot-modesyscon-reboot-modeRBRB RB RBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart &&#baudclkapb_pclk/''4txrx>HUdefault c()* disabledi2s@ff060000rockchip,px30-i2s-tdm  #mclk_txmclk_rxhclk/''4txrxm+z tx-mrx-mUdefault0c,-./01234567 disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  #i2s_clki2s_hclk/''4txrxUdefaultc89:; disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s #i2s_clki2s_hclk/''4txrxUdefaultc<=>? disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+io-domains rockchip,px30-io-voltage-domainokay@A%%B Clvdsrockchip,px30-lvdsDdphym+'lvds disabledports+port@0+endpoint@07Eendpoint@17Fport@1serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart I#baudclkapb_pclk>HUdefaultcGokayserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart J#baudclkapb_pclk/''4txrx>HUdefaultcH disabledserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart K#baudclkapb_pclk/''4txrx>HUdefault cIJK disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart L#baudclkapb_pclk/'' 4txrx>HUdefault cLMN disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart M#baudclkapb_pclk/' ' 4txrx>HUdefaultcOokayi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN #i2cpclk UdefaultcP+okaypmic@20rockchip,rk809 xin32k QUdefaultcRG_mSySSS%%%SregulatorsDCDC_REG1vdd_log~p2qregulator-state-memG_~DCDC_REG2vdd_arm~p2qregulator-state-mem{_~DCDC_REG3vcc_ddrregulator-state-memGDCDC_REG4 vcc_3v0_1v8--Cregulator-state-memG_-DCDC_REG5vcc_3v32Z2Z%regulator-state-memG_2ZLDO_REG2vcc_1v8w@w@Bregulator-state-memG_w@LDO_REG3vcc_1v0B@B@regulator-state-memG_B@LDO_REG4vcc_2v8**Vregulator-state-mem{_*LDO_REG5 vccio_sd--Aregulator-state-memG_-LDO_REG6 vcc_sdio--@regulator-state-memG_2ZLDO_REG7vcc_lcdB@B@regulator-state-mem{_B@LDO_REG8 vcc_1v8_lcdw@w@regulator-state-memG_w@LDO_REG9 vcca_1v8w@w@regulator-state-mem{_w@i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO #i2cpclk UdefaultcT+okayi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP #i2cpclk  UdefaultcU+okay2,touchscreen@14 goodix,gt911V Q QUdefaultcWX Q %i2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q #i2cpclk  UdefaultcY+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $U#spiclkapb_pclk/' ' 4txrx UdefaultcZ[\]+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %V#spiclkapb_pclk/''4txrx Udefaultc^_`ab+ disabledwatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ %okaypwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S #pwmpclkUdefaultccokaypwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S #pwmpclkUdefaultcdokaypwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S #pwmpclkUdefaultce disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S #pwmpclkUdefaultcf disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T #pwmpclkUdefaultcg disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T #pwmpclkUdefaultchokaypwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T #pwmpclkUdefaultciokaypwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T #pwmpclkUdefaultcjokaytimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& #pclktimerdma-controller@ff240000arm,pl330arm,primecell$@ #apb_pclk4'tsadc@ff280000rockchip,px30-tsadc( $?,OP,X#tsadcapb_pclkz tsadc-apbm+dUinitdefaultsleepck{lkokay saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-W#saradcapb_pclkz saradc-apbokayBnvmem@ff290000rockchip,px30-otp)@/Za#otpapb_pclkphyzphy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ m& #xin24mgpllm+8?@IOFq рр clock-controller@ff2bc000rockchip,px30-pmucru+m#xin24mm+?&&& OG&syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy & #phyclk?n usb480m_phyokaynhost-port D linestateokayqotg-port$BA@otg-bvalidotg-idlinestateokaypphy@ff2e0000rockchip,px30-dsi-dphy.& E #refpclkz>apbo okayDphy@ff2f0000rockchip,px30-csi-dphy/@F#pclko z/apbm+ disabledusb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >#otgotg/>@ p usb2-phyookayusb@ff340000 generic-ehci4 <qusbookayusb@ff350000 generic-ohci5 =qusbookayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[#stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedm+MrmiiUdefaultcrso z^ stmmacethokayVoutputctn%mdiosnps,dwmac-mdio+ethernet-phy@0ethernet-phy-id2000.a140UdefaultcuyPP vtmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CD#biuciuciu-driveciu-sampleрUdefault cwxyookayAAmmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EF#biuciuciu-driveciu-sampleрUdefault cz{|o  disabledmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GH#biuciuciu-driveciu-sampleрUdefault c}~o okay'9D%Cspi@ff3a0000 rockchip,sfc:@ 8:#clk_sfchclk_sfc cUdefaulto  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 97#ahbnfc?7OрUdefault co  disabledopp-table-1operating-points-v2opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuIookayRvideo-codec@ff442000rockchip,px30-vpuD PO vepuvdpu #aclkhclk^o iommu@ff442800rockchip,iommuD( Q #aclkifaceeo dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KD#pclkDdphyo z=apbm+okay+ports+port@0+endpoint@07endpoint@17port@1endpoint7panel@0leadtek,ltk500hd1829r|BUdefaultc Q ~Vportendpoint7vop@ff460000rockchip,px30-vop-bigF M#aclk_vopdclk_vophclk_vopz345 axiahbdclk^o okayport+ endpoint@07endpoint@17Eiommu@ff460f00rockchip,iommuF M #aclkifaceo eokayvop@ff470000rockchip,px30-vop-litG N#aclk_vopdclk_vophclk_vopz789 axiahbdclk^o  disabledport+ endpoint@07endpoint@17Fiommu@ff470f00rockchip,iommuG N #aclkifaceo e disabledvideo-capture@ff490000rockchip,px30-vipI E`#aclkhclkpclko z,-.axiahbpclkin disabledisp@ff4a0000rockchip,px30-cif-ispJ$FIJ ispmimipi 3_#ispaclkhclkpclk^dphyo  disabledports+port@0iommu@ff4a8000rockchip,iommuJ F #aclkifaceo eqos@ff518000rockchip,px30-qossysconQ qos@ff520000rockchip,px30-qossysconR $qos@ff52c000rockchip,px30-qossysconR qos@ff538000rockchip,px30-qossysconS qos@ff538080rockchip,px30-qossysconS qos@ff538100rockchip,px30-qossysconS qos@ff538180rockchip,px30-qossysconS qos@ff540000rockchip,px30-qossysconT qos@ff540080rockchip,px30-qossysconT qos@ff548000rockchip,px30-qossysconT qos@ff548080rockchip,px30-qossysconT  qos@ff548100rockchip,px30-qossysconT !qos@ff548180rockchip,px30-qossysconT "qos@ff548200rockchip,px30-qossysconT #qos@ff550000rockchip,px30-qossysconU qos@ff550080rockchip,px30-qossysconU qos@ff550100rockchip,px30-qossysconU qos@ff550180rockchip,px30-qossysconU qos@ff558000rockchip,px30-qossysconU qos@ff558080rockchip,px30-qossysconU pinctrlrockchip,px30-pinctrlm++Udefaultcgpio@ff040000rockchip,gpio-bank &Qgpio@ff250000rockchip,gpio-bank% \gpio@ff260000rockchip,gpio-bank& ]vgpio@ff270000rockchip,gpio-bank' ^pcfg-pull-uppcfg-pull-downpcfg-pull-nonepcfg-pull-none-2mapcfg-pull-up-2mapcfg-pull-up-4mapcfg-pull-none-4mapcfg-pull-down-4mapcfg-pull-none-8mapcfg-pull-up-8mapcfg-pull-none-12ma pcfg-pull-up-12ma pcfg-pull-none-smt pcfg-output-high !pcfg-output-low -pcfg-input-high 8pcfg-input 8i2c0i2c0-xfer E Pi2c1i2c1-xfer ETi2c2i2c2-xfer EUi2c3i2c3-xfer E  Ytsadctsadc-otp-pin Ektsadc-otp-out Eluart0uart0-xfer E  (uart0-cts E )uart0-rts E *uart1uart1-xfer EGuart1-cts Euart1-rts Euart2-m0uart2m0-xfer EHuart2-m1uart2m1-xfer E uart3-m0uart3m0-xfer Euart3m0-cts Euart3m0-rts Euart3-m1uart3m1-xfer EIuart3m1-cts E Juart3m1-rts E Kuart4uart4-xfer ELuart4-cts EMuart4-rts ENuart5uart5-xfer EOuart5-cts Euart5-rts Espi0spi0-clk EZspi0-csn E[spi0-miso E \spi0-mosi E ]spi0-clk-hs Espi0-miso-hs E spi0-mosi-hs E spi1spi1-clk E^spi1-csn0 E _spi1-csn1 E `spi1-miso Easpi1-mosi E bspi1-clk-hs Espi1-miso-hs Espi1-mosi-hs E pdmpdm-clk0m0 Epdm-clk0m1 Epdm-clk1 Epdm-sdi0m0 Epdm-sdi0m1 Epdm-sdi1 Epdm-sdi2 Epdm-sdi3 Epdm-clk0m0-sleep Epdm-clk0m1-sleep Epdm-clk1-sleep Epdm-sdi0m0-sleep Epdm-sdi0m1-sleep Epdm-sdi1-sleep Epdm-sdi2-sleep Epdm-sdi3-sleep Ei2s0i2s0-8ch-mclk Ei2s0-8ch-sclktx E,i2s0-8ch-sclkrx E -i2s0-8ch-lrcktx E.i2s0-8ch-lrckrx E /i2s0-8ch-sdo0 E0i2s0-8ch-sdo1 E2i2s0-8ch-sdo2 E4i2s0-8ch-sdo3 E6i2s0-8ch-sdi0 E1i2s0-8ch-sdi1 E 3i2s0-8ch-sdi2 E 5i2s0-8ch-sdi3 E7i2s1i2s1-2ch-mclk Ei2s1-2ch-sclk E8i2s1-2ch-lrck E9i2s1-2ch-sdi E:i2s1-2ch-sdo E;i2s2i2s2-2ch-mclk Ei2s2-2ch-sclk E<i2s2-2ch-lrck E=i2s2-2ch-sdi E>i2s2-2ch-sdo E?sdmmcsdmmc-clk Ewsdmmc-cmd Exsdmmc-det Esdmmc-bus1 Esdmmc-bus4@ Eysdiosdio-clk E|sdio-cmd E{sdio-bus4@ Ezemmcemmc-clk E }emmc-cmd E ~emmc-rstnout E emmc-bus1 Eemmc-bus4@ Eemmc-bus8 Eemmc-reset E flashflash-cs0 Eflash-rdy E flash-dqs E flash-ale E flash-cle E flash-wrn E flash-csl Eflash-rdn Eflash-bus8 Esfcsfc-bus4@ Esfc-bus2 Esfc-cs0 Esfc-clk E lcdclcdc-rgb-dclk-pin Elcdc-rgb-m0-hsync-pin Elcdc-rgb-m0-vsync-pin Elcdc-rgb-m0-den-pin Elcdc-rgb888-m0-data-pins E     lcdc-rgb666-m0-data-pins E     lcdc-rgb565-m0-data-pins E     lcdc-rgb888-m1-data-pins E   lcdc-rgb666-m1-data-pins E   lcdc-rgb565-m1-data-pins E   pwm0pwm0-pin Ecpwm1pwm1-pin Edpwm2pwm2-pin E epwm3pwm3-pin Efpwm4pwm4-pin Egpwm5pwm5-pin Ehpwm6pwm6-pin Eipwm7pwm7-pin Ejgmacrmii-pins E rmac-refclk-12ma E smac-refclk E cif-m0cif-clkout-m0 E dvp-d2d9-m0 E   dvp-d0d1-m0 E d10-d11-m0 Ecif-m1cif-clkout-m1 Edvp-d2d9-m1 E  dvp-d0d1-m1 Ed10-d11-m1 Eispisp-prelight Ehogcobra-pin-hogP E cobra-proto-hog E  ethernetphy-rst Euledsheartbeat-led-pin Epaneldsp-rst E tch-int EWtch-rst E Xpmicpmic-int ERchosen Sserial5:115200n8backlightpwm-backlight _S labeeper pwm-beeper lemmc-pwrseqmmc-pwrseq-emmccUdefault  gpio-leds gpio-ledsUdefaultcled-0 q Q wheartbeat }heartbeatpwm-leds pwm-ledsled-0 q off wring_red lB@ led-1 q off wring_green lB@ led-2 q off wring_blue lB@ regulator-vccsysregulator-fixed vcc5v0_sysLK@LK@S compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1ethernet0mmc0mmc1device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,outputremote-endpointsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendi2c-scl-falling-time-nsi2c-scl-rising-time-nsAVDD28-supplyirq-gpiosreset-gpiostouchscreen-inverted-xVDDIO-supplynum-cs#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outphy-handlephy-supplyreset-assert-usreset-deassert-usbus-widthfifo-depthmax-frequencybroken-cdcap-sd-highspeedsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-pwrseqnon-removablemali-supplyiommus#iommu-cellsbacklightiovcc-supplyrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathpower-supplypwmscolorlabellinux,default-triggerdefault-statemax-brightness