8<(  ,radxa,rock3arockchip,rk35687Radxa ROCK 3Aaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe310000/mmc@fe2b0000/mmc@fe000000cpus cpu@0cpu,arm,cortex-a55 psci*7@IVc@u cpu@100cpu,arm,cortex-a55 psci*7@IVc@u cpu@200cpu,arm,cortex-a55 psci*7@IVc@u cpu@300cpu,arm,cortex-a55 psci*7@IVc@u l3-cache,cache,9@Kdisplay-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smcڂ protocol@14hdmi-sound,simple-audio-cardHDMIi2s(Bokaysimple-audio-card,codecIsimple-audio-card,cpuI pmu,arm,cortex-a55-pmu0S^ psci ,arm,psci-1.0#smcreserved-memory qshmem@10f000,arm,scmi-shmemxtimer,arm,armv8-timer0S   xin24m ,fixed-clockn6xin24mxin32k ,fixed-clockxin32kdefaultsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob S_  Bdisabledsata-port@0@  sata-phy ( sata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob S`  Bdisabledsata-port@0@  sata-phy ( usb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ Sref_clksuspend_clkbus_clk7otg ?utmi_wideHOBokay  usb2-phyusb3-phyhusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ Sref_clksuspend_clkbus_clk7host  usb2-phyusb3-phy ?utmi_wideHOBokayinterrupt-controller@fd400000 ,arm,gic-v3 @F S oA(q msi-controller@fd440000,arm,gic-v3-itsDjusb@fd800000 ,generic-ehci S usbBokayusb@fd840000 ,generic-ohci S usbBokayusb@fd880000 ,generic-ehci S usbBokayusb@fd8c0000 ,generic-ohci S usbBokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdhio-domains&,rockchip,rk3568-pmu-io-voltage-domainBokay (6Dsyscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucruRclock-controller@fdd20000,rockchip,rk3568-cruxin24mR_ oG  i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c S.- i2cpclk!default Bokayregulator@1c ,tcs,tcs4525vdd_cpu 50*?"regulator-state-memJpmic@20,rockchip,rk809 #S_HmclkHdefault$%c{&&&&&&&&&regulatorsDCDC_REG1 vdd_logic p*qregulator-state-memJDCDC_REG2vdd_gpu p*qHregulator-state-memJDCDC_REG3vcc_ddrregulator-state-memDCDC_REG4vdd_npu p*qregulator-state-memJDCDC_REG5vcc_1v8w@w@regulator-state-memJLDO_REG1vdda0v9_image  dregulator-state-memJLDO_REG2 vdda_0v9  regulator-state-memJLDO_REG3 vdda0v9_pmu  regulator-state-mem5 LDO_REG4 vccio_acodec2Z2Zregulator-state-memJLDO_REG5 vccio_sdw@2Zregulator-state-memJLDO_REG6 vcc3v3_pmu2Z2Zregulator-state-mem52ZLDO_REG7 vcca_1v8w@w@regulator-state-memJLDO_REG8 vcca1v8_pmuw@w@regulator-state-mem5w@LDO_REG9vcca1v8_imagew@w@eregulator-state-memJSWITCH_REG1vcc_3v3regulator-state-memJSWITCH_REG2 vcc3v3_sdqregulator-state-memJeeprom@50,belling,bl24c16aatmel,24c16PQZdserial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart St ,baudclkapb_pclko''(defaultt Bdisabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk)default Bdisabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk*default Bdisabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk+default Bdisabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk,default Bdisabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controller power-domain@7-power-domain@8 ./0power-domain@9  123power-domain@10 456789power-domain@11 :power-domain@13 ;power-domain@14 <=>power-domain@15 ?@ABCDEFgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$S()' jobmmugpugpubus BokayGHvideo-codec@fdea0400,rockchip,rk3568-vpu Svdpu aclkhclkI iommu@fdea0800,rockchip,rk3568-iommu@ S aclkiface Irga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga SZaclkhclksclkH&$% coreaxiahb video-codec@fdee0000,rockchip,rk3568-vepu S@ aclkhclkJ iommu@fdee0800,rockchip,rk3568-iommu@ S? aclkiface Jvideo-capture@fdfe0000,rockchip,rk3568-vicap S_o aclkhclkdclkiclkK(Harsthrstdrstprstirst  Bdisabledports port@0port@1iommu@fdfe0800,rockchip,rk3568-iommu S aclkiface BdisabledKmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ Sd biuciuciu-driveciu-sampleрHresetBokay!+6GTjLudefault MNO&ethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20aS macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refH stmmaceth PQRBokay_ S!input.T 9rgmii-idBdefaultUVWXYZmdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22default[MN ] o\Tstmmac-axi-config{Prx-queues-configQqueue0tx-queues-configRqueue0vop@fe040000 0@vopgamma-lut S(%aclkhclkdclk_vp0dclk_vp1dclk_vp2]  Bokay,rockchip,rk3568-vop_ports port@0 endpoint@2^fport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >? S aclkiface Bokay]dsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi SDpclkdphy _ apbH  Bdisabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi SEpclkdphy ` apbH  Bdisabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  S-((iahbisfrcecrefdefault abc t {Bokaydeports port@0endpointf^port@1endpointgqos@fe128000,rockchip,rk3568-qossyscon -qos@fe138080,rockchip,rk3568-qossyscon <qos@fe138100,rockchip,rk3568-qossyscon =qos@fe138180,rockchip,rk3568-qossyscon >qos@fe148000,rockchip,rk3568-qossyscon .qos@fe148080,rockchip,rk3568-qossyscon /qos@fe148100,rockchip,rk3568-qossyscon 0qos@fe150000,rockchip,rk3568-qossyscon :qos@fe158000,rockchip,rk3568-qossyscon 4qos@fe158100,rockchip,rk3568-qossyscon 5qos@fe158180,rockchip,rk3568-qossyscon 6qos@fe158200,rockchip,rk3568-qossyscon 7qos@fe158280,rockchip,rk3568-qossyscon 8qos@fe158300,rockchip,rk3568-qossyscon 9qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon ?qos@fe190280,rockchip,rk3568-qossyscon Cqos@fe190300,rockchip,rk3568-qossyscon Dqos@fe190380,rockchip,rk3568-qossyscon Eqos@fe190400,rockchip,rk3568-qossyscon Fqos@fe198000,rockchip,rk3568-qossyscon ;qos@fe1a8000,rockchip,rk3568-qossyscon 1qos@fe1a8080,rockchip,rk3568-qossyscon 2qos@fe1a8100,rockchip,rk3568-qossyscon 3dfi@fe230000,rockchip,rk3568-dfi# S  hpcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<SKJIHGsyspmcmsglegacyerr 0)aclk_mstaclk_slvaclk_dbipclkauxpipepci "` 5iiii C T c r j   pcie-phyTq @Hpipe Bokaydefaultk o\ llegacy-interrupt-controllero SHimmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ Sb biuciuciu-driveciu-sampleрHresetBokay!6 #+defaultmnopqmmc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ Sc biuciuciu-driveciu-sampleрHreset Bdisabledspi@fe300000 ,rockchip,sfc0@ Sexvclk_sfchclk_sfcrdefaultBokay flash@0,jedec,spi-nor 2  mmc@fe310000,rockchip,rk3568-dwcmshc1 S_{}o n6(|zy{}corebusaxiblocktimerBokay! udefaultstuvrng@fe388000,rockchip,rk3568-rng8@po coreahbHmBokayefuse@fe38c000,rockchip,rk3568-otp8@ sqrotpapb_pclkphysbpi Hnlmotpapbphysbpinvmem-layout ,fixed-layout cpu-code@2cpu-version@8 id@a cpu-leakage@1alog-leakage@1bnpu-leakage@1cgpu-leakage@1di2s@fe400000,rockchip,rk3568-i2s-tdm@ S4_=AoFqFq?C9mclk_txmclk_rxhclkow txHPQ tx-mrx-m {Bokay i2s@fe410000,rockchip,rk3568-i2s-tdmA S5_EIoFqFqGK:mclk_txmclk_rxhclkoww rxtxHRS tx-mrx-m defaultxyz{{Bokay i2s@fe420000,rockchip,rk3568-i2s-tdmB S6_MoFqOO;mclk_txmclk_rxhclkoww txrxHTtx-m default|}~{Bokay i2s@fe430000,rockchip,rk3568-i2s-tdmC S7SW<mclk_txmclk_rxhclkoww txrxHUV tx-mrx-m { Bdisabledpdm@fe440000,rockchip,rk3568-pdmD SLZYpdm_clkpdm_hclkow  rxdefaultHXpdm-m{ Bdisabledspdif@fe460000,rockchip,rk3568-spdifF Sf mclkhclk_\ow txdefault{ Bdisableddma-controller@fe530000,arm,pl330arm,primecellS@S    apb_pclk !'dma-controller@fe550000,arm,pl330arm,primecellU@S   apb_pclk !wi2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ S/HG i2cpclkdefault  Bdisabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ S0JI i2cpclkdefault  Bdisabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ S1LK i2cpclkdefault  Bdisabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] S2NM i2cpclkdefault  Bdisabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ S3PO i2cpclkdefault Bokayrtc@51,haoyu,hym8563Q#S rtcic_32koutdefaultwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt` S tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia SgRQspiclkapb_pclko'' txrxdefault   Bdisabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib ShTSspiclkapb_pclko'' txrxdefault   Bdisabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic SiVUspiclkapb_pclko'' txrxdefault   Bdisabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid SjXWspiclkapb_pclko'' txrxdefault   Bdisabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte Subaudclkapb_pclko'' defaulttBokay ,serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf Sv# baudclkapb_pclko''defaulttBokayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg Sw'$baudclkapb_pclko''defaultt Bdisabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth Sx+(baudclkapb_pclko'' defaultt Bdisabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti Sy/,baudclkapb_pclko' ' defaultt Bdisabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj Sz30baudclkapb_pclko' ' defaultt Bdisabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk S{74baudclkapb_pclko''defaultt Bdisabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl S|;8baudclkapb_pclko''defaultt Bdisabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm S}?<baudclkapb_pclko''defaultt Bdisabledthermal-zonescpu-thermal <d R `tripscpu_alert0 pp |passivecpu_alert1 p$ |passivecpu_crit ps | criticalcooling-mapsmap0 0 gpu-thermal < R `tripsgpu-threshold pp |passivegpu-target p$ |passivegpu-crit ps | criticalcooling-mapsmap0  tsadc@fe710000,rockchip,rk3568-tsadcq Ss_of@ `tsadcapb_pclkH  sdefaultsleep  Bokay  saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr S]saradcapb_pclkH saradc-apb Bokay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault Bdisabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefault Bdisabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefault Bdisabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefault Bdisabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault Bdisabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefault Bdisabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefault Bdisabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefault Bdisabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault Bdisabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefault Bdisabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefault Bdisabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefault Bdisabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe_"oHphy " 4 JBokayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe_%oHphy " 4 JBokayphy@fe870000,rockchip,rk3568-csi-dphyypclk JHapb  Bdisabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz J apbH Bdisabled_mipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ J apbH Bdisabled`usb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m S UBokayhost-port JBokayBotg-port JBokayBusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m S UBokayhost-port JBokayBotg-port JBokayBpinctrl,rockchip,rk3568-pinctrl  h qgpio@fdd60000,rockchip,gpio-bank S!.  e u  o#gpio@fe740000,rockchip,gpio-bankt S"cd e u  ogpio@fe750000,rockchip,gpio-banku S#ef e u@  ogpio@fe760000,rockchip,gpio-bankv S$gh e u`  o\gpio@fe770000,rockchip,gpio-bankw S%ij e u  opcfg-pull-up pcfg-pull-down pcfg-pull-none pcfg-pull-none-drv-level-1  pcfg-pull-none-drv-level-2  pcfg-pull-none-drv-level-3  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  acodecaudiopwmbt656bt1120camvcc_cam_en  can0can0m0-pins  can1can1m0-pins can2can2m0-pins   cifclk32kclk32k-out0 cpuebcedpdpemmcemmc-bus8   semmc-clk temmc-cmd uemmc-datastrobe veth0eth1flashfspifspi-pins` rgmac0gmac1gmac1m1-miim Ugmac1m1-clkinout Ygmac1m1-rx-bus20  Wgmac1m1-tx-bus20 Vgmac1m1-rgmii-clk Xgmac1m1-rgmii-bus@ Zgpuhdmitxhdmitxm1-cec chdmitx-scl ahdmitx-sda bi2c0i2c0-xfer  !i2c1i2c1-xfer  i2c2i2c2m0-xfer i2c3i2c3m1-xfer  i2c4i2c4m1-xfer   i2c5i2c5m0-xfer   i2s1i2s1m0-lrcktx yi2s1m0-mclk %i2s1m0-sclktx xi2s1m0-sdi0  zi2s1m0-sdo0 {i2s2i2s2m0-lrcktx }i2s2m0-sclktx |i2s2m0-sdi ~i2s2m0-sdo i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pcie30x2m1-pins0 pdmpdmm0-clk pdmm0-clk1 pdmm0-sdi0  pdmm0-sdi1  pdmm0-sdi2  pdmm0-sdi3 pmicpmic_int $pmupwm0pwm0m0-pins )pwm1pwm1m0-pins *pwm2pwm2m0-pins +pwm3pwm3-pins ,pwm4pwm4-pins pwm5pwm5-pins pwm6pwm6-pins pwm7pwm7-pins pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins pwm12pwm12m0-pins pwm13pwm13m0-pins pwm14pwm14m0-pins pwm15pwm15m0-pins refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ msdmmc0-clk nsdmmc0-cmd osdmmc0-det psdmmc1sdmmc2sdmmc2m0-bus4@ Msdmmc2m0-clk Osdmmc2m0-cmd Nspdifspdifm0-tx spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m0-pins0  spi1m0-cs0 spi1m0-cs1 spi2spi2m0-pins0 spi2m0-cs0 spi2m0-cs1 spi3spi3m0-pins0   spi3m0-cs0 spi3m0-cs1 tsadctsadc-shutorg tsadc-pin uart0uart0-xfer (uart1uart1m0-xfer   uart1m0-ctsn uart1m0-rtsn  uart2uart2m0-xfer uart3uart3m0-xfer uart4uart4m0-xfer uart5uart5m0-xfer uart6uart6m0-xfer uart7uart7m0-xfer uart8uart8m0-xfer uart9uart9m0-xfer vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2displayvcc_mipi_en etherneteth_phy_rst [hym8563hym8563-int ledsled_user_en pciepcie-enable-h pcie-reset-h kusbvcc5v0_usb_host_en vcc5v0_usb_hub_en vcc5v0_usb_otg_en btbt-enable  bt-host-wake  bt-wake  sdio-pwrseqwifi-enable opp-table-0,operating-points-v2 opp-408000000 Q P P0 @opp-600000000 #F P P0 @opp-816000000 0, P P0 @ opp-1104000000 Aʹ 0 @opp-1416000000 Tfr 0 @opp-1608000000 _" 0 @opp-1800000000 kI 000 @opp-1992000000 v 000 @opp-table-1,operating-points-v2Gopp-200000000  P PB@opp-300000000  P PB@opp-400000000 ׄ P PB@opp-600000000 #F B@opp-700000000 )' ~~B@opp-800000000 / B@B@B@sata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob S^  sata-phy Bdisabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconqos@fe190080,rockchip,rk3568-qossyscon @qos@fe190100,rockchip,rk3568-qossyscon Aqos@fe190200,rockchip,rk3568-qossyscon Bsyscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconˀphy@fe8c0000,rockchip,rk3568-pcie3-phy J&'wrefclk_mrefclk_npclkHphy %BokayBpcie@fe270000,rockchip,rk3568-pcie  0)aclk_mstaclk_slvaclk_dbipclkauxpipepci<Ssyspmcmsglegacyerr "` 5 C T c r j   pcie-phy0@@'Tq @@@dbiapbconfigHpipe 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Analog RK809(simple-audio-card,cpuIsimple-audio-card,codecIsdio-pwrseq,mmc-pwrseq-simple ext_clockdefault gd ~LK@ o\Lregulator-vcc12v-dcin,regulator-fixed vcc12v_dcinregulator-pcie30-avdd0v9,regulator-fixedpcie30_avdd0v9  ?&regulator-pcie30-avdd1v8,regulator-fixedpcie30_avdd1v8w@w@?&regulator-vcc3v3-pi6c-03,regulator-fixedvcc3v3_pi6c_032Z2Z?"regulator-vcc3v3-pcie,regulator-fixed  u#default vcc3v3_pcie2Z2Z?"lregulator-vcc3v3-sys,regulator-fixed vcc3v3_sys2Z2Z?&regulator-vcc5v0-sys,regulator-fixed vcc5v0_sysLK@LK@?"regulator-vcc5v0-usb,regulator-fixed vcc5v0_usbLK@LK@?regulator-vcc5v0-usb-host,regulator-fixed  #defaultvcc5v0_usb_hostLK@LK@?regulator-vcc5v0-usb-hub,regulator-fixed  #defaultvcc5v0_usb_hub?regulator-vcc5v0-usb-otg,regulator-fixed  #defaultvcc5v0_usb_otgLK@LK@?regulator-vcc-cam,regulator-fixed  defaultvcc_cam2Z2Z?&regulator-state-memJregulator-vcc-mipi,regulator-fixed  \default vcc_mipi2Z2Z?&regulator-state-memJ interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandlecache-levelcache-unifiedportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityrangesno-maparm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesclock-namesports-implementedpower-domainshba-port-capphysphy-namessnps,rx-ts-maxsnps,tx-ts-maxdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerdma-noncoherent#msi-cellspmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendsystem-power-controller#sound-dai-cellsvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltpagesizeread-onlyvcc-supplydmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesrockchip,disable-mmu-resetfifo-depthmax-frequencybus-widthdisable-wpcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modephy-supplyreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplycd-gpiosspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthbitsdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendrockchip,phy-grfstdout-pathfunctioncolorlinux,default-triggerpost-power-on-delay-mspower-off-delay-usenable-active-highgpio