w8 <( ; "ti,omap3-evmti,omap3430ti,omap3 +7TI OMAP35XX EVM (TMDSEVM3530)chosenaliases=/ocp@68000000/i2c@48070000B/ocp@68000000/i2c@48072000G/ocp@68000000/i2c@48060000L/ocp@68000000/mmc@4809c000Q/ocp@68000000/mmc@480b4000V/ocp@68000000/mmc@480ad000[/ocp@68000000/serial@4806a000c/ocp@68000000/serial@4806c000k/ocp@68000000/serial@49020000 s/displaycpus+cpu@0arm,cortex-a8|cpucpupmu@54000000arm,cortex-a8-pmuTdebugsssocti,omap-inframpu ti,omap3-mpumpuiva ti,iva2.2ivadsp ti,omap3-c64ocp@68000000ti,omap3-l3-smxsimple-bush +l3_mainl4@48000000ti,omap3-l4-coresimple-bus+ Hscm@2000ti,omap3-scmsimple-bus + pinmux@30 ti,omap3-padconfpinctrl-single08+ 5Spdefault~twl4030-pinsAdss-dpi2-pinsmmc1-pinsP "$&mmc2-pinsP(*,.02468:uart3-pinsnApehci-port-select-pinshsusb2-pins0      wl12xx-gpio-pinsPNsmsc911x-pinsscm_conf@270sysconsimple-busp0+ p0pbias_regulator@2b0ti,pbias-omap3ti,pbias-omappbias_mmc_omap2430pbias_mmc_omap2430w@-clocks+clock@68 ti,clkselh+clock-mcbsp5-mux-fck@4ti,composite-mux-clockmcbsp5_mux_fck  clock-mcbsp3-mux-fck@0ti,composite-mux-clockmcbsp3_mux_fck clock-mcbsp4-mux-fck@2ti,composite-mux-clockmcbsp4_mux_fck mcbsp5_fckti,composite-clock clock@4 ti,clksel+clock-mcbsp1-mux-fck@2ti,composite-mux-clockmcbsp1_mux_fck clock-mcbsp2-mux-fck@6ti,composite-mux-clockmcbsp2_mux_fck mcbsp1_fckti,composite-clock mcbsp2_fckti,composite-clockmcbsp3_fckti,composite-clockmcbsp4_fckti,composite-clockclockdomainspinmux@a00 ti,omap3-padconfpinctrl-single \+ 5Stwl4030-vpins-pins dss-dpi1-pins0   target-module@480a6000ti,sysc-omap2ti,syscH `DH `HH `Lrevsyscsyss  'ick+ H ` aes1@0 ti,omap3-aesP4  9txrxtarget-module@480c5000ti,sysc-omap2ti,syscH PDH PHH PLrevsyscsyss  'ick+ H P aes2@0 ti,omap3-aesP4AB9txrxprm@48306000 ti,omap3-prmH0`@ clocks+virt_16_8m_ck fixed-clockCYosc_sys_ck@d40 ti,mux-clock @sys_ck@1270ti,divider-clockS`pk#sys_clkout1@d70ti,gate-clock pSdpll3_x2_ckfixed-factor-clockdpll3_m2x2_ckfixed-factor-clock "dpll4_x2_ckfixed-factor-clock!corex2_fckfixed-factor-clock"$wkup_l4_ickfixed-factor-clock#ccorex2_d3_fckfixed-factor-clock$corex2_d5_fckfixed-factor-clock$clockdomainscm@48004000 ti,omap3-cmH@@clocks+dummy_apb_pclk fixed-clockComap_32k_fck fixed-clockCIvirt_12m_ck fixed-clockCvirt_13m_ck fixed-clockC]@virt_19200000_ck fixed-clockC$virt_26000000_ck fixed-clockCvirt_38_4m_ck fixed-clockCIdpll4_ck@d00ti,omap3-dpll-per-clock## D 0!dpll4_m2_ck@d48ti,divider-clock!`? Hk%dpll4_m2x2_mul_ckfixed-factor-clock%&dpll4_m2x2_ck@d00ti,gate-clock&S 'omap_96m_alwon_fckfixed-factor-clock'3dpll3_ck@d00ti,omap3-dpll-core-clock## @ 0clock@1140 ti,clksel@+clock-dpll3-m3@16ti,divider-clock dpll3_m3_ck`k-clock-dpll4-m6@24ti,divider-clock dpll4_m6_ck!`?k?clock-emu-src-mux@0 ti,mux-clockemu_src_mux_ck#()*wclock-pclk-fck@8ti,divider-clock pclk_fck+`kclock-pclkx2-fck@6ti,divider-clock pclkx2_fck+`kclock-atclk-fck@4ti,divider-clock atclk_fck+`kclock-traceclk-src-fck@2 ti,mux-clocktraceclk_src_fck#()*,clock-traceclk-fck@11 ti,divider-clock traceclk_fck,`kdpll3_m3x2_mul_ckfixed-factor-clock-.dpll3_m3x2_ck@d00ti,gate-clock.S  /emu_core_alwon_ckfixed-factor-clock/(sys_altclk fixed-clockC6mcbsp_clks fixed-clockC core_ckfixed-factor-clock 0dpll1_fck@940ti,divider-clock0S` @k1dpll1_ck@904ti,omap3-dpll-clock#1  $ @ 4dpll1_x2_ckfixed-factor-clock2dpll1_x2m2_ck@944ti,divider-clock2` DkFcm_96m_fckfixed-factor-clock34clock@d40 ti,clksel @+clock-dpll3-m2@27ti,divider-clock dpll3_m2_ck`k clock-omap-96m-fck@6 ti,mux-clock omap_96m_fck4#Zclock-omap-54m-fck@5 ti,mux-clock omap_54m_fck56Bclock-omap-48m-fck@3 ti,mux-clock omap_48m_fck76:clock@e40 ti,clksel@+clock-dpll4-m3@8ti,divider-clock dpll4_m3_ck!` k8clock-dpll4-m4@0ti,divider-clock dpll4_m4_ck!`k;dpll4_m3x2_mul_ckfixed-factor-clock89dpll4_m3x2_ck@d00ti,gate-clock9S 5cm_96m_d2_fckfixed-factor-clock47omap_12m_fckfixed-factor-clock:[dpll4_m4x2_mul_ckti,fixed-factor-clock;<dpll4_m4x2_ck@d00ti,gate-clock<S _dpll4_m5_ck@f40ti,divider-clock!`?@k=dpll4_m5x2_mul_ckti,fixed-factor-clock=>dpll4_m5x2_ck@d00ti,gate-clock>S {dpll4_m6x2_mul_ckfixed-factor-clock?@dpll4_m6x2_ck@d00ti,gate-clock@S Aemu_per_alwon_ckfixed-factor-clockA)clock@d70 ti,clksel p+clock-clkout2-src-gate@7 ti,composite-no-wait-gate-clockclkout2_src_gate_ck0Dclock-clkout2-src-mux@0ti,composite-mux-clockclkout2_src_mux_ck0#4BEclock-sys-clkout2@3ti,divider-clock sys_clkout2C`@clkout2_src_ckti,composite-clockDECmpu_ckfixed-factor-clockFGarm_fck@924ti,divider-clockG $`emu_mpu_alwon_ckfixed-factor-clockG*clock@a40 ti,clksel @+clock-l3-ick@0ti,divider-clockl3_ick0`kHclock-l4-ick@2ti,divider-clockl4_ickH`kJclock-gpt10-mux-fck@6ti,composite-mux-clockgpt10_mux_fckI#Wclock-gpt11-mux-fck@7ti,composite-mux-clockgpt11_mux_fckI#Yclock-ssi-ssr-div-fck-3430es2@8ti,composite-divider-clockssi_ssr_div_fck_3430es2$$clock@c40 ti,clksel @+clock-rm-ick@1ti,divider-clockrm_ickJ`kclock-gpt1-mux-fck@0ti,composite-mux-clock gpt1_mux_fckI#bclock-usim-mux-fck@3ti,composite-mux-clock usim_mux_fck(#KLMNOPQRSkclock@a00 ti,clksel +clock-gpt10-gate-fck@11 ti,composite-gate-clockgpt10_gate_fck#Vclock-gpt11-gate-fck@12 ti,composite-gate-clockgpt11_gate_fck#Xclock-mmchs2-fck@25ti,wait-gate-clock mmchs2_fckclock-mmchs1-fck@24ti,wait-gate-clock mmchs1_fckclock-i2c3-fck@17ti,wait-gate-clock i2c3_fckclock-i2c2-fck@16ti,wait-gate-clock i2c2_fckclock-i2c1-fck@15ti,wait-gate-clock i2c1_fckclock-mcbsp5-gate-fck@10 ti,composite-gate-clockmcbsp5_gate_fck  clock-mcbsp1-gate-fck@9 ti,composite-gate-clockmcbsp1_gate_fck  clock-mcspi4-fck@21ti,wait-gate-clock mcspi4_fckTclock-mcspi3-fck@20ti,wait-gate-clock mcspi3_fckTclock-mcspi2-fck@19ti,wait-gate-clock mcspi2_fckTclock-mcspi1-fck@18ti,wait-gate-clock mcspi1_fckTclock-uart2-fck@14ti,wait-gate-clock uart2_fckTclock-uart1-fck@13 ti,wait-gate-clock uart1_fckTclock-hdq-fck@22ti,wait-gate-clockhdq_fckUclock-modem-fck@31ti,omap3-interface-clock modem_fck#clock-mspro-fck@23ti,wait-gate-clock mspro_fckclock-ssi-ssr-gate-fck-3430es2@0 ti,composite-no-wait-gate-clockssi_ssr_gate_fck_3430es2$clock-mmchs3-fck@30ti,wait-gate-clock mmchs3_fckgpt10_fckti,composite-clockVWgpt11_fckti,composite-clockXYcore_96m_fckfixed-factor-clockZcore_48m_fckfixed-factor-clock:Tcore_12m_fckfixed-factor-clock[Ucore_l3_ickfixed-factor-clockH\clock@a10 ti,clksel +clock-sdrc-ick@1ti,wait-gate-clock sdrc_ick\clock-mmchs2-ick@25ti,omap3-interface-clock mmchs2_ick]clock-mmchs1-ick@24ti,omap3-interface-clock mmchs1_ick]clock-hdq-ick@22ti,omap3-interface-clockhdq_ick]clock-mcspi4-ick@21ti,omap3-interface-clock mcspi4_ick]clock-mcspi3-ick@20ti,omap3-interface-clock mcspi3_ick]clock-mcspi2-ick@19ti,omap3-interface-clock mcspi2_ick]clock-mcspi1-ick@18ti,omap3-interface-clock mcspi1_ick]clock-i2c3-ick@17ti,omap3-interface-clock i2c3_ick]clock-i2c2-ick@16ti,omap3-interface-clock i2c2_ick]clock-i2c1-ick@15ti,omap3-interface-clock i2c1_ick]clock-uart2-ick@14ti,omap3-interface-clock uart2_ick]clock-uart1-ick@13 ti,omap3-interface-clock uart1_ick]clock-gpt11-ick@12 ti,omap3-interface-clock gpt11_ick]clock-gpt10-ick@11 ti,omap3-interface-clock gpt10_ick]clock-mcbsp5-ick@10 ti,omap3-interface-clock mcbsp5_ick]clock-mcbsp1-ick@9 ti,omap3-interface-clock mcbsp1_ick]clock-omapctrl-ick@6ti,omap3-interface-clock omapctrl_ick]clock-aes2-ick@28ti,omap3-interface-clock aes2_ick]clock-sha12-ick@27ti,omap3-interface-clock sha12_ick]clock-icr-ick@29ti,omap3-interface-clockicr_ick]clock-des2-ick@26ti,omap3-interface-clock des2_ick]clock-mspro-ick@23ti,omap3-interface-clock mspro_ick]clock-mailboxes-ick@7ti,omap3-interface-clockmailboxes_ick]clock-sad2d-ick@3ti,omap3-interface-clock sad2d_ickHclock-hsotgusb-ick-3430es2@4"ti,omap3-hsotgusb-interface-clockhsotgusb_ick_3430es2\clock-ssi-ick-3430es2@0ti,omap3-ssi-interface-clockssi_ick_3430es2^ clock-mmchs3-ick@30ti,omap3-interface-clock mmchs3_ick]gpmc_fckfixed-factor-clock\core_l4_ickfixed-factor-clockJ]clock@e00 ti,clksel+clock-dss-tv-fckti,gate-clock dss_tv_fckBSclock-dss-96m-fckti,gate-clock dss_96m_fckZSclock-dss2-alwon-fckti,gate-clockdss2_alwon_fck#Sclock-dss1-alwon-fck-3430es2@0ti,dss-gate-clockdss1_alwon_fck_3430es2_dummy_ck fixed-clockCclock@c00 ti,clksel +clock-gpt1-gate-fck@0ti,composite-gate-clockgpt1_gate_fck#aclock-gpio1-dbck@3ti,gate-clock gpio1_dbck`clock-wdt2-fck@5ti,wait-gate-clock wdt2_fck`clock-sr1-fck@6ti,wait-gate-clocksr1_fck#clock-sr2-fck@7ti,wait-gate-clocksr2_fck#clock-usim-gate-fck@9 ti,composite-gate-clockusim_gate_fckZgpt1_fckti,composite-clockabwkup_32k_fckfixed-factor-clockI`clock@c10 ti,clksel +clock-wdt2-ick@5ti,omap3-interface-clock wdt2_ickcclock-wdt1-ick@4ti,omap3-interface-clock wdt1_ickcclock-gpio1-ick@3ti,omap3-interface-clock gpio1_ickcclock-omap-32ksync-ick@2ti,omap3-interface-clockomap_32ksync_ickcclock-gpt12-ick@1ti,omap3-interface-clock gpt12_ickcclock-gpt1-ick@0ti,omap3-interface-clock gpt1_ickcclock-usim-ick@9 ti,omap3-interface-clock usim_ickcper_96m_fckfixed-factor-clock3 per_48m_fckfixed-factor-clock:dclock@1000 ti,clksel+clock-uart3-fck@11 ti,wait-gate-clock uart3_fckdclock-gpt2-gate-fck@3ti,composite-gate-clockgpt2_gate_fck#fclock-gpt3-gate-fck@4ti,composite-gate-clockgpt3_gate_fck#hclock-gpt4-gate-fck@5ti,composite-gate-clockgpt4_gate_fck#jclock-gpt5-gate-fck@6ti,composite-gate-clockgpt5_gate_fck#lclock-gpt6-gate-fck@7ti,composite-gate-clockgpt6_gate_fck#nclock-gpt7-gate-fck@8ti,composite-gate-clockgpt7_gate_fck#pclock-gpt8-gate-fck@9 ti,composite-gate-clockgpt8_gate_fck#rclock-gpt9-gate-fck@10 ti,composite-gate-clockgpt9_gate_fck#tclock-gpio6-dbck@17ti,gate-clock gpio6_dbckeclock-gpio5-dbck@16ti,gate-clock gpio5_dbckeclock-gpio4-dbck@15ti,gate-clock gpio4_dbckeclock-gpio3-dbck@14ti,gate-clock gpio3_dbckeclock-gpio2-dbck@13 ti,gate-clock gpio2_dbckeclock-wdt3-fck@12 ti,wait-gate-clock wdt3_fckeclock-mcbsp2-gate-fck@0ti,composite-gate-clockmcbsp2_gate_fck clock-mcbsp3-gate-fck@1ti,composite-gate-clockmcbsp3_gate_fck clock-mcbsp4-gate-fck@2ti,composite-gate-clockmcbsp4_gate_fck clock@1040 ti,clksel@+clock-gpt2-mux-fck@0ti,composite-mux-clock gpt2_mux_fckI#gclock-gpt3-mux-fck@1ti,composite-mux-clock gpt3_mux_fckI#iclock-gpt4-mux-fck@2ti,composite-mux-clock gpt4_mux_fckI#kclock-gpt5-mux-fck@3ti,composite-mux-clock gpt5_mux_fckI#mclock-gpt6-mux-fck@4ti,composite-mux-clock gpt6_mux_fckI#oclock-gpt7-mux-fck@5ti,composite-mux-clock gpt7_mux_fckI#qclock-gpt8-mux-fck@6ti,composite-mux-clock gpt8_mux_fckI#sclock-gpt9-mux-fck@7ti,composite-mux-clock gpt9_mux_fckI#ugpt2_fckti,composite-clockfggpt3_fckti,composite-clockhigpt4_fckti,composite-clockjkgpt5_fckti,composite-clocklmgpt6_fckti,composite-clocknogpt7_fckti,composite-clockpqgpt8_fckti,composite-clockrsgpt9_fckti,composite-clocktuper_32k_alwon_fckfixed-factor-clockIeper_l4_ickfixed-factor-clockJvclock@1010 ti,clksel+clock-gpio6-ick@17ti,omap3-interface-clock gpio6_ickvclock-gpio5-ick@16ti,omap3-interface-clock gpio5_ickvclock-gpio4-ick@15ti,omap3-interface-clock gpio4_ickvclock-gpio3-ick@14ti,omap3-interface-clock gpio3_ickvclock-gpio2-ick@13 ti,omap3-interface-clock gpio2_ickvclock-wdt3-ick@12 ti,omap3-interface-clock wdt3_ickvclock-uart3-ick@11 ti,omap3-interface-clock uart3_ickvclock-uart4-ick@18ti,omap3-interface-clock uart4_ickvclock-gpt9-ick@10 ti,omap3-interface-clock gpt9_ickvclock-gpt8-ick@9 ti,omap3-interface-clock gpt8_ickvclock-gpt7-ick@8ti,omap3-interface-clock gpt7_ickvclock-gpt6-ick@7ti,omap3-interface-clock gpt6_ickvclock-gpt5-ick@6ti,omap3-interface-clock gpt5_ickvclock-gpt4-ick@5ti,omap3-interface-clock gpt4_ickvclock-gpt3-ick@4ti,omap3-interface-clock gpt3_ickvclock-gpt2-ick@3ti,omap3-interface-clock gpt2_ickvclock-mcbsp2-ick@0ti,omap3-interface-clock mcbsp2_ickvclock-mcbsp3-ick@1ti,omap3-interface-clock mcbsp3_ickvclock-mcbsp4-ick@2ti,omap3-interface-clock mcbsp4_ickvemu_src_ckti,clkdm-gate-clockw+secure_32k_fck fixed-clockCxgpt12_fckfixed-factor-clockxwdt1_fckfixed-factor-clockxsecurity_l4_ick2fixed-factor-clockJyclock@a14 ti,clksel +clock-aes1-ick@3ti,omap3-interface-clock aes1_ickyclock-rng-ick@2ti,omap3-interface-clockrng_ickyclock-sha11-ick@1ti,omap3-interface-clock sha11_ickyclock-des1-ick@0ti,omap3-interface-clock des1_ickyclock-pka-ick@4ti,omap3-interface-clockpka_ickzclock@f00 ti,clksel+clock-cam-mclk@0ti,gate-clock cam_mclk{clock-csi2-96m-fck@1ti,gate-clock csi2_96m_fckcam_ick@f10!ti,omap3-no-wait-interface-clockJSsecurity_l3_ickfixed-factor-clockHzssi_l4_ickfixed-factor-clockJ^sr_l4_ickfixed-factor-clockJdpll2_fck@40ti,divider-clock0S`@k|dpll2_ck@4ti,omap3-dpll-clock#|$@4}dpll2_m2_ck@44ti,divider-clock}`Dk~iva2_ck@0ti,wait-gate-clock~Sclock@a18 ti,clksel ++clock-mad2d-ick@3ti,omap3-interface-clock mad2d_ickHclock-usbtll-ick@2ti,omap3-interface-clock usbtll_ick]ssi_ssr_fck_3430es2ti,composite-clockssi_sst_fck_3430es2fixed-factor-clock sys_d2_ckfixed-factor-clock#Komap_96m_d2_fckfixed-factor-clockZLomap_96m_d4_fckfixed-factor-clockZMomap_96m_d8_fckfixed-factor-clockZNomap_96m_d10_fckfixed-factor-clockZ Odpll5_m2_d4_ckfixed-factor-clockPdpll5_m2_d8_ckfixed-factor-clockQdpll5_m2_d16_ckfixed-factor-clockRdpll5_m2_d20_ckfixed-factor-clockSusim_fckti,composite-clockdpll5_ck@d04ti,omap3-dpll-clock##  $ L 4dpll5_m2_ck@d50ti,divider-clock` Pksgx_gate_fck@b00ti,composite-gate-clock0S core_d3_ckfixed-factor-clock0core_d4_ckfixed-factor-clock0core_d6_ckfixed-factor-clock0omap_192m_alwon_fckfixed-factor-clock'core_d2_ckfixed-factor-clock0sgx_mux_fck@b40ti,composite-mux-clock 4 @sgx_fckti,composite-clocksgx_ick@b10ti,wait-gate-clockH Scpefuse_fck@a08ti,gate-clock# Sts_fck@a08ti,gate-clockI Susbtll_fck@a08ti,wait-gate-clock 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gpio@49054000ti,omap3-gpioI@ gpio4} gpio@49056000ti,omap3-gpioI`!gpio5} gpio@49058000ti,omap3-gpioI"gpio6} serial@4806a000ti,omap3-uartH HR4129txrxuart1Clserial@4806c000ti,omap3-uartHIJ4349txrxuart2Clserial@49020000ti,omap3-uartIJn4569txrxuart3Clpdefault~i2c@48070000 ti,omap3-i2cH8+i2c1C'@twl@48H  ti,twl4030 pdefault~rtcti,twl4030-rtc chargerti,twl4030-bci  vacwatchdogti,twl4030-wdtregulator-vaux1ti,twl4030-vaux1regulator-vaux2ti,twl4030-vaux2usb_1v8w@w@regulator-vaux3ti,twl4030-vaux3regulator-vaux4ti,twl4030-vaux4regulator-vdd1ti,twl4030-vdd1 ' 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4+,-.9tx0rx0tx1rx1spi@480b8000ti,omap2-mcspiH [+mcspi3 49tx0rx0tx1rx1spi@480ba000ti,omap2-mcspiH 0+mcspi44FG9tx0rx01w@480b2000 ti,omap3-1wH :hdq1wmmc@4809c000ti,omap3-hsmmcH Smmc14=>9txrxSpdefault~mmc@480b4000ti,omap3-hsmmcH @Vmmc24/09txrxV.+pdefault~wlcore@2 ti,wl1271N irqwakeupImmc@480ad000ti,omap3-hsmmcH ^mmc34MN9txrx disabledmmu@480bd400ti,omap2-iommuH mmu_isp(mmu@5d000000ti,omap2-iommu]mmu_iva disabledwatchdog@48314000 ti,omap3-wdtH1@ wd_timer2mcbsp@48074000ti,omap3-mcbspH@mpu ;< commontxrx8mcbsp14 9txrxfck disabledtarget-module@480a0000ti,sysc-omap2ti,syscH <H @H Drevsyscsyss 'ick+ H rng@0 ti,omap2-rng 4mcbsp@49022000ti,omap3-mcbspI I mpusidetone>?commontxrxsidetone8mcbsp2mcbsp2_sidetone4!"9txrxfckick disabledmcbsp@49024000ti,omap3-mcbspI@I mpusidetoneYZcommontxrxsidetone8mcbsp3mcbsp3_sidetone49txrxfckick disabledmcbsp@49026000ti,omap3-mcbspI`mpu 67 commontxrx8mcbsp449txrxfckG disabledmcbsp@48096000ti,omap3-mcbspH `mpu QR commontxrx8mcbsp549txrxfck disabledsham@480c3000ti,omap3-shamshamH 0d14E9rxtarget-module@48318000ti,sysc-omap2-timerti,syscH1H1H1revsyscsyss ' 'fckick+ H1Xltimer@0ti,omap3430-timerfck%wItarget-module@49032000ti,sysc-omap2-timerti,syscI I I revsyscsyss ' 'fckick+ I timer@0ti,omap3430-timer&timer@49034000ti,omap3430-timerI@'timer3timer@49036000ti,omap3430-timerI`(timer4timer@49038000ti,omap3430-timerI)timer5timer@4903a000ti,omap3430-timerI*timer6timer@4903c000ti,omap3430-timerI+timer7timer@4903e000ti,omap3430-timerI,timer8timer@49040000ti,omap3430-timerI-timer9timer@48086000ti,omap3430-timerH`.timer10timer@48088000ti,omap3430-timerH/timer11target-module@48304000ti,sysc-omap2-timerti,syscH0@H0@H0@revsyscsyss ' 'fckick+ H0@timer@0ti,omap3430-timer_wusbhstll@48062000 ti,usbhs-tllH N usb_tll_hsusbhshost@48064000ti,usbhs-hostH@ usb_host_hs+ ehci-phyusb@48064400ti,ohci-omap3HDLusb@48064800 ti,ehci-omapHHMgpmc@6e000000ti,omap3430-gpmcgpmcn49rxtx + } 0,ethernet@gpmcsmsc,lan9221smsc,lan9115(:Tn|(-- 1x@ZKqK    pdefault~nand@0,0ti,omap2-nand   %( 4bch8 Dn|,,",(61@R R(+target-module@480ab000ti,sysc-omap2ti,syscH H H revsyscsyss  8 'fck+ H usb@0ti,omap3-musb\]mcdma U ` h  q  usb2-phyJ 2dss@48050000 ti,omap3-dssHokay dss_corefck+  pdefault~ dispc@48050400ti,omap3-dispcH dss_dispcfckencoder@4804fc00 ti,omap3-dsiHH@H protophypll disabled dss_dsi1 fcksys_clk+encoder@48050800ti,omap3-rfbiH disabled dss_rfbifckickencoder@48050c00ti,omap3-vencH  disabled dss_vencfckportendpoint   ssi-controller@48058000 ti,omap3-ssissiokayHHsysgddGgdd_mpu+    ssi_ssr_fckssi_sst_fckssi_ickssi-port@4805a000ti,omap3-ssi-portHHtxrxCDssi-port@4805b000ti,omap3-ssi-portHHtxrxEFpinmux@480025d8 ti,omap3-padconfpinctrl-singleH%$+ 5Spdefault~ ehci-phy-pinshsusb2-2-pins0   "  isp@480bc000 ti,omap3-ispH H | l ports+bandgap@48002524H%$ti,omap34xx-bandgap target-module@480cb000ti,sysc-omap3430-srti,syscsmartreflex_coreH $sysc fck+ H smartreflex@0ti,omap3-smartreflex-coretarget-module@480c9000ti,sysc-omap3430-srti,syscsmartreflex_mpu_ivaH $sysc fck+ H smartreflex@480c9000ti,omap3-smartreflex-mpu-ivatarget-module@50000000ti,sysc-omap2ti,syscPrevfckick+ Pgpu@0#ti,omap3430-gpuimg,powervr-sgx530opp-tableoperating-points-v2-ti-cpuopp-125000000 sY@  opp-250000000 沀 g8g8g8  $opp-500000000 e OOO opp-550000000 U txtxtx opp-600000000 #F ppp opp-720000000 *T ppp  0thermal-zonescpu-thermal ; Q _N  ltripscpu_alert |8 passivecpu_crit |_  criticalcooling-mapsmap0  regulator-vddvarioregulator-fixed vddvarioregulator-vdd33aregulator-fixedvdd33ahsusb2_power_regregulator-fixed hsusb2_vbus2Z2Z  p hsusb2-phy-pinsusb-nop-xceiv Opdefault~leds gpio-ledsledb omap3evm::ledb  default-onwl12xx_vmmcregulator-fixedvwl1271w@w@  p  pdefault~backlightgpio-backlight  regulator-lcd-3v3regulator-fixedlcd_3v32Z2Z p displaysharp,ls037v7dw01 lcd   # $ 0portendpoint  memory@80000000|memory compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2mmc0mmc1mmc2serial0serial1serial2display0device_typeregclocksclock-namesclock-latencyoperating-points-v2#cooling-cellscpu0-supplyphandleinterruptsti,hwmodsranges#pinctrl-cells#interrupt-cellsinterrupt-controllerpinctrl-single,register-widthpinctrl-single,function-maskpinctrl-namespinctrl-0pinctrl-single,pinssysconregulator-nameregulator-min-microvoltregulator-max-microvolt#clock-cellsclock-output-namesreg-namesti,sysc-maskti,sysc-sidleti,syss-maskdmasdma-namesclock-frequencyti,bit-shiftti,max-divti,index-starts-at-oneclock-multclock-divti,set-bit-to-disableti,clock-multti,clock-divti,set-rate-parentti,index-power-of-twoti,dividersti,low-power-stopti,lockti,low-power-bypass#ssize-cellsti,sysc-midle#dma-cellsdma-channelsdma-requeststi,gpio-always-ongpio-controller#gpio-cellsgpio-hoggpiosoutput-lowline-nameinterrupts-extendedbci3v1-supplyio-channelsio-channel-namesregulator-always-onti,use-ledsusb1v5-supplyusb1v8-supplyusb3v1-supplyusb_mode#phy-cells#pwm-cellskeypad,num-rowskeypad,num-columnslinux,keymap#io-channel-cellsti,use_poweroff#mbox-cellsti,mbox-num-usersti,mbox-num-fifosti,mbox-txti,mbox-rxti,spi-num-csspi-max-frequencyvcc-supplyti,x-minti,x-maxti,y-minti,y-maxti,x-plate-ohmsti,pressure-maxti,swap-xywakeup-sourcependown-gpioti,dual-voltpbias-supplyvmmc-supplyvqmmc-supplybus-widthnon-removablecap-power-off-cardinterrupt-namesref-clock-frequencystatus#iommu-cellsti,#tlb-entriesti,buffer-size#sound-dai-cellsti,no-reset-on-initti,no-idleti,timer-alwonassigned-clocksassigned-clock-parentsti,timer-dspti,timer-pwmti,timer-secureport2-moderemote-wakeup-connectedphysgpmc,num-csgpmc,num-waitpinsbank-widthgpmc,device-widthgpmc,cycle2cycle-samecsengpmc,cycle2cycle-diffcsengpmc,cs-on-nsgpmc,cs-rd-off-nsgpmc,cs-wr-off-nsgpmc,adv-on-nsgpmc,adv-rd-off-nsgpmc,adv-wr-off-nsgpmc,oe-on-nsgpmc,oe-off-nsgpmc,we-on-nsgpmc,we-off-nsgpmc,rd-cycle-nsgpmc,wr-cycle-nsgpmc,access-nsgpmc,page-burst-access-nsgpmc,bus-turnaround-nsgpmc,cycle2cycle-delay-nsgpmc,wait-monitoring-nsgpmc,clk-activation-nsgpmc,wr-data-mux-bus-nsgpmc,wr-access-nsvddvario-supplyvdd33a-supplyreg-io-widthsmsc,save-mac-addressnand-bus-widthti,nand-ecc-optgpmc,sync-clk-psmultipointnum-epsram-bitsinterface-typeusb-phyphy-namespowervdds_dsi-supplyvdda_video-supplyremote-endpointdata-linesiommusti,phy-type#thermal-sensor-cellsopp-hzopp-microvoltopp-supported-hwopp-suspendturbo-modepolling-delay-passivepolling-delaycoefficientsthermal-sensorstemperaturehysteresistripcooling-devicestartup-delay-usenable-active-highreset-gpioslabellinux,default-triggervin-supplydefault-onpower-supplyenvdd-supplyenable-gpiosmode-gpios