Ðþí  ÿ   8  ø   (              À                                  cudy,wr3000-v1 mediatek,mt7981b                                  +            7Cudy WR3000 V1     cpus                         +       cpu@0             arm,cortex-a53           =             Acpu          Mpsci          cpu@1             arm,cortex-a53           =            Acpu          Mpsci             oscillator-40m            fixed-clock          [bZ          kclkxtal          ~          psci              arm,psci-1.0             Tsmc       reserved-memory                      +             ‹   secmon@43000000          =    C                    ’         soc           simple-bus            ‹                     +      interrupt-controller@c000000              arm,gic-v3            =                                                 ™      	             ¤         ¹            Ê         clock-controller@10001000              mediatek,mt7981-infracfg syscon          =                      ~            Ê         clock-controller@1001b000              mediatek,mt7981-topckgen syscon          =    °                 ~            Ê         watchdog@1001c000             mediatek,mt7986-wdt          =    À                 ™       n            Ò            Ê   	      clock-controller@1001e000             mediatek,mt7981-apmixedsys           =    à                 ~            Ê         pwm@10048000              mediatek,mt7981-pwm          =    €              (   ß                                       ætop main pwm1 pwm2 pwm3          ò         serial@11002000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =                       ™       {            ýuart wakeup          ß                  	   æbaud bus            default                  	  %disabled          serial@11003000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =     0                 ™       |            ýuart wakeup          ß                   	   æbaud bus          	  %disabled          serial@11004000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =     @                 ™       }            ýuart wakeup          ß            !      	   æbaud bus          	  %disabled          i2c@11007000              mediatek,mt7981-i2c           =     p            !p€       €         ™       ˆ             ß                  3      4         æmain dma arb pmic                        +          	  %disabled          spi@11009000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =     �                 ™       Ž             ß            N      "      #          æparent-clk sel-clk spi-clk hclk                      +          	  %disabled          spi@1100a000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =                       ™       Œ             ß            N      '      )          æparent-clk sel-clk spi-clk hclk                      +          	  %disabled          spi@1100b000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =     °                 ™       �             ß            N      (      *          æparent-clk sel-clk spi-clk hclk                      +          	  %disabled          thermal@1100c800          0    mediatek,mt7981-thermal mediatek,mt7986-thermal          =     È                 ™       Š            ß            0         ætherm auxadc            ,           8calibration-data            I           _           o         adc@1100d000          .    mediatek,mt7981-auxadc mediatek,mt7986-auxadc            =     Ð                 ß      0         æmain            ƒ         	  %disabled             Ê         pinctrl@11d00000              mediatek,mt7981-pinctrl       �   =    Ð             À             Á             Ò             à             â             ð             ñ              °              I  •gpio iocfg_rt iocfg_rm iocfg_rb iocfg_lb iocfg_bl iocfg_tm iocfg_tl eint              ¤         ™       á                       Ÿ              8         «        »            ¹            Ê      uart0-pins           Ê      mux         Çuart            Ðuart0               efuse@11f20000        %    mediatek,mt7981-efuse mediatek,efuse             =    ò                              +      soc-uuid@140             =  @         thermal-calib@274            =  t            Ê            clock-controller@15000000             mediatek,mt7981-ethsys syscon            =                       ~            Ò         wifi@18000000             mediatek,mt7981-wmac          0   =                   0            Ñ               0   ™       Õ          Ö          ×          Ø            ß      _      \         æmcu ap2conn         ×   	           Þconsys           timer             arm,armv8-timer                   0   ™                                 
         memory@40000000          =    @                   Amemory        keys          
    gpio-keys      key-wps         êWPS         ð                  ö        key-reset           êRESET           ð                 ö  ˜         leds          
    gpio-leds      led-0                      Çwan         ð               led-1                    
  Çwlan-2ghz           ð               led-2                    
  Çwlan-5ghz           ð               led-3                      Çlan         ð      	         led-4                      Çstatus          ð      
         led-5                      Çwan-online          ð                     	compatible interrupt-parent #address-cells #size-cells model reg device_type enable-method clock-frequency clock-output-names #clock-cells ranges no-map interrupts interrupt-controller #interrupt-cells phandle #reset-cells clocks clock-names #pwm-cells interrupt-names pinctrl-names pinctrl-0 status nvmem-cells nvmem-cell-names #thermal-sensor-cells mediatek,auxadc mediatek,apmixedsys #io-channel-cells reg-names gpio-ranges gpio-controller #gpio-cells function groups resets reset-names label gpios linux,code color 