Ðþí KØ   8 =Ø   (              =                              -    google,ciri-sku5 google,ciri mediatek,mt8188                                     +            7Google Ciri sku5 board (rev4)      aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dsc@1c009000            T/soc/ethdr@1c114000          [/soc/mailbox@10320000            `/soc/mailbox@10330000            e/soc/merge0@1c014000             l/soc/merge@1c10c000          s/soc/merge@1c10d000          z/soc/merge@1c10e000          �/soc/merge@1c10f000          ˆ/soc/merge@1c110000          �/soc/mutex@1c016000          –/soc/mutex@1c101000          �/soc/padding@1c11d000            ¦/soc/padding@1c11e000            ¯/soc/padding@1c11f000            ¸/soc/padding@1c120000            Á/soc/padding@1c121000            Ê/soc/padding@1c122000            Ó/soc/padding@1c123000            Ü/soc/padding@1c124000            å/soc/rdma@1c104000           ð/soc/rdma@1c105000           û/soc/rdma@1c106000          /soc/rdma@1c107000          /soc/rdma@1c108000          /soc/rdma@1c109000          '/soc/rdma@1c10a000          2/soc/rdma@1c10b000          =/soc/dsi@1c008000           B/soc/i2c@11280000           G/soc/i2c@11e00000           L/soc/i2c@11281000           Q/soc/i2c@11282000           V/soc/i2c@11e01000           [/soc/i2c@11ec0000           `/soc/i2c@11ec1000           e/soc/mmc@11230000           j/soc/serial@11001100          cpus                         +       cpu@0           rcpu           arm,cortex-a55          ~            ‚psci            �w5”                    ³              Ã  €         Ð   @        â   €        ï  €         ü   @           €                   ,               @           O   	      cpu@100         rcpu           arm,cortex-a55          ~           ‚psci            �w5”                    ³              Ã  €         Ð   @        â   €        ï  €         ü   @           €                   ,               @           O   
      cpu@200         rcpu           arm,cortex-a55          ~           ‚psci            �w5”                    ³              Ã  €         Ð   @        â   €        ï  €         ü   @           €                   ,               @           O         cpu@300         rcpu           arm,cortex-a55          ~           ‚psci            �w5”                    ³              Ã  €         Ð   @        â   €        ï  €         ü   @           €                   ,               @           O         cpu@400         rcpu           arm,cortex-a55          ~           ‚psci            �w5”                    ³              Ã  €         Ð   @        â   €        ï  €         ü   @           €                   ,               @           O         cpu@500         rcpu           arm,cortex-a55          ~           ‚psci            �w5”                    ³              Ã  €         Ð   @        â   €        ï  €         ü   @           €                   ,               @           O         cpu@600         rcpu           arm,cortex-a78          ~           ‚psci            �šøÚ                     ³              Ã           Ð   @        â           ï           ü   @                              ,              @           O         cpu@700         rcpu           arm,cortex-a78          ~           ‚psci            �šøÚ                     ³              Ã           Ð   @        â           ï           ü   @                              ,              @           O         cpu-map    cluster0       core0           W   	      core1           W   
      core2           W         core3           W         core4           W         core5           W         core6           W         core7           W               idle-states         [psci       cpu-off-l             arm,idle-state          h                    �   2        ¡   _        ±  D        O         cpu-off-b             arm,idle-state          h                    �   -        ¡   Œ        ±  ä        O         cluster-off-l             arm,idle-state          h                  �   7        ¡   ›        ±  H        O         cluster-off-b             arm,idle-state          h                  �   2        ¡   È        ±  è        O            l2-cache0             cache           Â           Å           Ò   @        ä                       Î        O         l2-cache1             cache           Â           Å           Ò   @        ä                       Î        O         l3-cache              cache           Â           Å            Ò   @        ä            Î        O            oscillator-13m            fixed-clock         Ü            � Æ]@        éclk13m          O   @      oscillator-26m            fixed-clock         Ü            �Œº€        éclk26m          O   C      oscillator-32k            fixed-clock         Ü            �  €         éclk32k        opp-table-gpu             operating-points-v2          ü        O   w   opp-390000000               >í€         Æ           ÿ      opp-431000000               °‰À         öì           ÿ      opp-473000000               1h@         	'À           ÿ      opp-515000000               ²FÀ         	X”           ÿ      opp-556000000               !#ã          	‰h           ÿ      opp-598000000               #¤Á€         	º<           ÿ      opp-640000000               &%           	ë           ÿ      opp-670000000               'ïc€         
ä           ÿ      opp-700000000               )¹'          
L¸           ÿ      opp-730000000               +‚ê€         
}Œ           ÿ      opp-760000000               -L®          
®`           ÿ      opp-790000000               /q€         
ß4           ÿ      opp-835000000               1ÅÀ         (r           ÿ      opp-880000000               4s¼          q°           ÿ      opp-915000000               6‰ÊÀ         ÓX           �      opp-915000000-5             6‰ÊÀ         ¢„           0      opp-915000000-6             6‰ÊÀ         q°           p      opp-950000000               8ŸÙ€         5            �      opp-950000000-5             8ŸÙ€         ÓX           0      opp-950000000-6             8ŸÙ€         q°           p         pmu-a55           arm,cortex-a55-pmu                      -                  pmu-a78           arm,cortex-a78-pmu                      -                  psci              arm,psci-1.0            ‰smc       sound           8           Jokay          ]  Qaud_etdm_hp_on aud_etdm_hp_off aud_etdm_spk_on aud_etdm_spk_off aud_mtkaif_on aud_mtkaif_off            _           i           s           }           ‡           ‘           ›             mediatek,mt8188-es8326           7mt8188_tas2563_8326       ©  ©ETDM1_OUT ETDM_SPK_PIN ETDM2_OUT ETDM_HP_PIN ETDM1_IN ETDM_SPK_PIN ETDM2_IN ETDM_HP_PIN ADDA Capture MTKAIF_PIN Headphone Jack HPOL Headphone Jack HPOR MIC1 Headset Mic       dai-link-0          ·ETDM1_IN_BE         Ái2s         Ìcpu       dai-link-1          ·ETDM1_OUT_BE            Ái2s         Ìcpu    codec           â            dai-link-2          ·ETDM2_IN_BE         Ìcpu    codec           â            dai-link-3          ·ETDM2_OUT_BE            Ìcpu    codec           â            dai-link-4          ·DPTX_BE    codec           â               thermal-zones      cpu-little0-thermal         ì  è        ú   –                  trips      trip-alert0           _�        ,  Ð        ypassive         O          trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical             cooling-maps       map0            7          H  <   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little1-thermal         ì  è        ú   –                 trips      trip-alert0           _�        ,  Ð        ypassive         O   !      trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical             cooling-maps       map0            7   !      H  <   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little2-thermal         ì  è        ú   –                 trips      trip-alert0           _�        ,  Ð        ypassive         O   "      trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical             cooling-maps       map0            7   "      H  <   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little3-thermal         ì  è        ú   –                 trips      trip-alert0           _�        ,  Ð        ypassive         O   #      trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical             cooling-maps       map0            7   #      H  <   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-big0-thermal            ì  è        ú   d                 trips      trip-alert0           _�        ,  Ð        ypassive         O   $      trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical             cooling-maps       map0            7   $        <   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-big1-thermal            ì  è        ú   d                 trips      trip-alert0           _�        ,  Ð        ypassive         O   %      trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical             cooling-maps       map0            7   %        <   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            apu-thermal         ì  è        ú   ú           &       trips      trip-alert0           L        ,  Ð        ypassive       trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical                gpu-thermal         ì  è        ú   ú           &      trips      trip-alert0           L        ,  Ð        ypassive         O   '      trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical             cooling-maps       map0            7   '        <   (ÿÿÿÿÿÿÿÿ            gpu1-thermal            ì  è        ú   ú           &      trips      trip-alert0           L        ,  Ð        ypassive         O   )      trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical             cooling-maps       map0            7   )        <   (ÿÿÿÿÿÿÿÿ            adsp-thermal            ì  è        ú   ú           &      trips      trip-alert0           L        ,  Ð        ypassive       trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical                vdo-thermal         ì  è        ú   ú           &      trips      trip-alert0           L        ,  Ð        ypassive       trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical                infra-thermal           ì  è        ú   ú           &      trips      trip-alert0           L        ,  Ð        ypassive       trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical                cam1-thermal            ì  è        ú   ú           &      trips      trip-alert0           L        ,  Ð        ypassive       trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical                cam2-thermal            ì  è        ú   ú           &      trips      trip-alert0           L        ,  Ð        ypassive       trip-alert1           s        ,  Ð        yhot       trip-crit             †         ,          	  ycritical                   timer             arm,armv8-timer                   @  -                                             
               � Æ]@      soc                      +             simple-bus          K                                O   performance-controller@11bc10             mediatek,cpufreq-hw          ~     ¼            ½0               V           O         interrupt-controller@c000000              arm,gic-v3          p           �                        ˜         ~                                    -      	               O      ppi-partitions     interrupt-partition-0           ­   	   
                    O         interrupt-partition-1           ­              O               syscon@10000000            mediatek,mt8188-topckgen syscon         ~                      Ü           O   -      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon          ~                     Ü           ¶           O   .      syscon@10003000           mediatek,mt8188-pericfg syscon          ~     0                Ü           O   W      pinctrl@10005000              mediatek,mt8188-pinctrl       `  ~     P            À             á             â             ê              °              0  Ãiocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint          Í        Ý           é   *           °         ˜        -       ë               p        B  õGSC_AP_INT_ODL AP_DISP_BKLTEN  EN_PPVAR_MIPI_DISP EN_PPVAR_MIPI_DISP_150MA TCHSCR_RST_1V8_L      I2S_SPKR_DATAOUT EN_PP3300_WLAN_X WIFI_KILL_1V8_L BT_KILL_1V8_L AP_FLASH_WP_L   WCAM_PWDN_L WCAM_RST_L UCAM_PWDM_L UCAM_RST_L WCAM_24M_CLK UCAM_24M_CLK MT6319_INT DISP_RST_1V8_L DSIO_DSI_TE  TP MIPI_BL_PWM_1V8  UART_AP_TX_GSC_RX UART_GSC_TX_AP_RX UART_SSPM_TX_DBGCON_RX UART_DBGCON_TX_SSPM_RX UART_ADSP_TX_DBGCON_RX UART_DBGCON_TX_ADSP_RX JTAG_AP_TMS JTAG_AP_TCK JTAG_AP_TDI JTAG_AP_TDO JTAG_AP_TRST AP_KPCOL0 TP  TP EC_AP_HPD_OD PCIE_WAKE_1V8_ODL PCIE_RST_1V8_L PCIE_CLKREQ_1V8_ODL      AP_I2C_AUD_SCL_1V8 AP_I2C_AUD_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_TPM_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_PMIC_SAR_SCL_1V8 AP_I2C_PMIC_SAR_SDA_1V8 AP_I2C_EC_HID_KB_SCL_1V8 AP_I2C_EC_HID_KB_SDA_1V8 AP_I2C_UCAM_SCL_1V8 AP_I2C_UCAM_SDA_1V8 AP_I2C_WCAM_SCL_1V8 AP_I2C_WCAM_SDA_1V8 SPI_AP_CS_EC_L SPI_AP_CLK_EC SPI_AP_DO_EC_DI SPI_AP_DI_EC_DO TP TP SPI_AP_CS_TCHSCR_L SPI_AP_CLK_TCHSCR SPI_AP_DO_TCHSCR_DI SPI_AP_DI_TCHSCR_DO TP TP TP TP    TP      PWRAP_SPI_CS_L PWRAP_SPI_CK PWRAP_SPI_MOSI PWRAP_SPI_MISO SRCLKENA0 SRCLKENA1 SCP_VREQ_VAO AP_RTC_CLK32K AP_PMIC_WDTRST_L AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1  HP_INT_ODL SPKR_INT_ODL I2S_HP_DATAIN EN_SPKR I2S_SPKR_MCLK I2S_SPKR_BCLK I2S_HP_MCLK I2S_HP_BCLK I2S_HP_LRCK I2S_HP_DATAOUT RST_SPKR_L I2S_SPKR_LRCK I2S_SPKR_DATAIN     SPI_AP_CLK_ROM SPI_AP_CS_ROM_L SPI_AP_DO_ROM_DI SPI_AP_DI_ROM_DO TP TP         EN_PP2800A_UCAM_X EN_PP1200_UCAM_X EN_PP2800A_WCAM_X EN_PP1100_WCAM_X TCHSCR_INT_1V8_L  MT7921_PMU_EN_1V8  AP_EC_WARM_RST_REQ EC_AP_HID_INT_ODL EC_AP_INT_ODL AP_XHCI_INIT_DONE EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_RST_L EMMC_CMD EMMC_CLK EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 EMMC_DSL         USB3_HUB_RST_L EC_AP_RSVD0_ODL   SPMI_SCL SPMI_SDA           O   *   adsp-uart-pins          O   K   pins-bus              #  $         aud-etdm-hp-on-pins         O      pins-bus              n  s  t  u      pins-mclk             r         aud-etdm-hp-off-pins            O      pins-bus              n   s   t   u                         pins-mclk             r                            aud-etdm-spk-on-pins            O      pins-bus                q  w  x        (            aud-etdm-spk-off-pins           O      pins-bus                 q   w   x                            aud-mtkaif-on-pins          O      pins-bus              e  f  g  h  i  j         aud-mtkaif-off-pins         O      pins-bus              e   f   g   h   i   j                            cros-ec-int-pins            O   N   pins-ec-ap-int-odl            •                   disp-pwm0-pins          O   P   pins-disp-pwm0                     7         disp-pwm1-pins          O   Q   pins-disp-pwm1                     7         dp-tx-hpd-pins          O   ­   pins-dp-tx-hpd            .         gsc-int-pins            O   p   pins-gsc-ap-int-odl                               i2c0-pins           O   b   pins-bus              8  7         i2c1-pins           O   o   pins-bus              :  9         i2c2-pins           O   d   pins-bus              <  ;         C        (            i2c3-pins           O   e   pins-bus              >  =         i2c4-pins           O   q   pins-bus              @  ?         i2c5-pins           O   s   pins-bus              B  A         i2c6-pins           O   t   pins-bus              D  C         mipi-disp-avdd-en-pins          O   ³   pins-en-ppvar-mipi-disp                     P         mipi-disp-avee-en-pins          O   ´   pins-en-ppvar-mipi-disp-150ma                       P         mipi-dsi-pins           O   ”   pins-bus                           P         mmc0-default-pins           O   ]   pins-bus          $    ¡     Ÿ  ž  š  ™  ˜  —  œ                 (           [   e      pins-clk              �        (              f      pins-rst              ›        (           [   e         mmc0-uhs-pins           O   ^   pins-bus          $    ¡     Ÿ  ž  š  ™  ˜  —  œ                 (           [   e      pins-clk              �        (              f      pins-ds           ¢        (              f      pins-rst              ›        (           [   e         nor-default-pins            O   m   pins-clk                }  €               pins-cs           ~         [         pcie-default-pins           O   l   pins-bus              /  0  1         scp-pins            O   A   pins-scp-vreq             b         C         spi0-pins           O   M   pins-bus              E  F  G  H         C         spi1-default-pins           O   R   pins-bus              K  L  M  N         C         spi1-sleep-pins         O   S   pins-bus              K   L   M   N                            spi2-pins           O   T   pins-bus              O  P  Q  R         C         uart0-pins          O   L   pins-bus                          [         wlan-en-pins            O   ±   pins-en-pp3300-wlan                     P         audio-codec-pins            O   c   pins-hp-int-odl           l                   speaker-en-pins    pins-en-spkr              o             syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd            ~     `           power-controller          !    mediatek,mt8188-power-controller                         +            h           O   D   power-domain@0          ~                         +            h           |   +   power-domain@1          ~           Š   ,      -           ‘mfg alt         �   .                     +            h           |   /   power-domain@2          ~           h          power-domain@3          ~           h          power-domain@4          ~           h                power-domain@15         ~         à  Š   -      -      -      -   
   -   3   -   4   -   =   -   ¹   -   ¾   0      0      0      0      0      0      0      0      0      0      0      0      0      0      0      0      0      0      0          û  ‘top cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1          �   .                     +            h      power-domain@16         ~         H  Š   -   »   -   À   1      1      1      1      1      1      1         A  ‘cfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus            �   .                     +            h      power-domain@20         ~         0  Š   -   º   -   ¿   2      2      2      2         8  ‘cfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6         �   .        h          power-domain@22         ~           Š   3            ‘ss-vdec1-soc-l1         �   .                     +            h      power-domain@23         ~           Š   4            ‘ss-vdec2-l1         �   .        h             power-domain@29         ~            Š   -      -      -   	   -   ½        ‘cam ccu bus cfgck           �   .                     +            h           |   5   power-domain@30         ~         (  Š   6       6      6      6      6         6  ‘ss-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys           �   .                     +            h      power-domain@32         ~            Š   6      7       8          $  ‘ss-camb-sub ss-camb-raw ss-camb-yuv         h          power-domain@31         ~           Š   6      9       :          $  ‘ss-cama-sub ss-cama-raw ss-cama-yuv         h                power-domain@17         ~         (  Š   -   ¼   -   Á   ;       ;      ;         &  ‘cfgck cfgxo ss-larb2 ss-larb3 ss-gals           �   .                     +            h      power-domain@9          ~   	        Š   -   @   -   ?      	  ‘bus hdcp            �   .        h          power-domain@18         ~           �   .        h          power-domain@19         ~           �   .        h             power-domain@24         ~            Š   <       <      <      <         0  ‘ss-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram         �   .        h          power-domain@21         ~           Š   =      =           ‘ss-wpe-l7 ss-wpe-l7pce          �   .        h                power-domain@5          ~           �   .        Š   >           ‘ss-pextp-fmem           h          power-domain@7          ~           Š   -   0   -   1        ‘seninf0 seninf1         h          power-domain@6          ~           h          power-domain@10         ~   
        Š   -   E   -   D      	  ‘bus main            �   .                     +            h      power-domain@11         ~           �   .                     +            h      power-domain@14         ~           Š   -   F        ‘asm         �   .        h          power-domain@13         ~           Š   -   S   -      ?            ‘a1sys intbus adspck         �   .        h          power-domain@12         ~           �   .        h                power-domain@8          ~           Š   >         	  ‘ethermac            �   .        h                watchdog@10007000             mediatek,mt8188-wdt         ~     p                 ¯        ¶           O   E      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon           ~     À                Ü           O   ,      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer         ~    p                -      	               Š   @      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon          ~    @                Ãpwrap           -       ó               Š   .      .          	  ‘spi wrap       pmic              mediatek,mt6359          ˜        p           Ç           Ø   *   Þ      adc           mediatek,mt6359-auxadc          ì         audio-codec           mediatek,mt6359-codec           þ                      %         regulators            mediatek,mt6359-regulator      buck_vs1            9vs1         H 5         ` !‘À        x             ”      buck_vgpu11         9vgpu11          H €        ` 7        ¨  ˆ        x   È        ½                   ”      buck_vmodem         9vmodem          H ÓX        ` ÓX        ¨  *        x   È      buck_vpu            9vpu         H €        ` 7        ¨  ˆ        x   È        ½                   ”      buck_vcore          9vcore           H €        ` Ö         ¨  ˆ        x   È        ½                   ”      buck_vs2            9vs2         H 5         ` j         x             ”      buck_vpa            9vpa         H ¡         ` /M`        x  ,      buck_vproc2         9ppvar_dvdd_vgpu         H dp        ` 5         ¨  L        x   È        ½                  Õ   /        ì  j        O   +      buck_vproc1         9vproc1          H €        ` 7        ¨  L        x   È        ½                  O   5      buck_vcore_sshub            9vcore_sshub         H €        ` 7      buck_vgpu11_sshub           9vgpu11_sshub            H dp        ` dp         ”      ldo_vaud18          9vaud18          H w@        ` w@        x   ð      ldo_vsim1           9vsim1           H ð         ` /M`      ldo_vibr            9vibr            H O€        ` 2Z       ldo_vrf12           9vrf12           H Èà        ` Ö          ”      ldo_vusb            9vusb            H -ÆÀ        ` -ÆÀ        x  À         ”      ldo_vsram_proc2         9vsram_proc2         H ¡         ` ½¶        ¨  L        x   ð         ”      ldo_vio18           9vio18           H ð         ` ýà        x  À         ”      ldo_vcamio          9vcamio          H ð         ` ýà      ldo_vcn18           9vcn18           H w@        ` w@        x   ð      ldo_vfe28           9vfe28           H *¹€        ` *¹€        x   x      ldo_vcn13           9vcn13           H »         ` Ö       ldo_vcn33_1_bt          9vcn33_1_bt          H *¹€        ` 5gà      ldo_vcn33_1_wifi            9vcn33_1_wifi            H *¹€        ` 5gà      ldo_vaux18          9vaux18          H w@        ` w@        x   ð         ”      ldo_vsram_others            9pp0850_dvdd_sram_gpu            H q°        ` 5         ¨  ˆ        x   ð        Õ   +        ì  j        O   /      ldo_vefuse          9vefuse          H ð         ` „€      ldo_vxo22           9vxo22           H w@        ` !‘À         ”      ldo_vrfck           9vrfck           H ã`        ` ð       ldo_vrfck_1         9vrfck           H ëÀ        ` j       ldo_vbif28          9vbif28          H *¹€        ` *¹€        x   ð      ldo_vio28           9vio28           H *¹€        ` 2Z       ldo_vemc            9vemc            H ,@         ` 2Z       ldo_vemc_1          9vemc            H &%         ` 2Z         O   _      ldo_vcn33_2_bt          9vcn33_2_bt          H *¹€        ` 5gà      ldo_vcn33_2_wifi            9vcn33_2_wifi            H *¹€        ` 5gà      ldo_va12            9va12            H O€        ` Ö          ”      ldo_va09            9va09            H 5         ` O€      ldo_vrf18           9vrf18           H ð         ` žP      ldo_vsram_md          	  9vsram_md            H 5         ` 5         ¨  *        x   ð      ldo_vufs            9vufs            H ð         ` ýà         ”        O   `      ldo_vm18            9vm18            H w@        ` ýà        	 †         O   ˜      ldo_vbbck           9vbbck           H Èà        ` O€      ldo_vsram_proc1         9vsram_proc1         H ¡         ` ½¶        ¨  L        x   ð         ”      ldo_vsim2           9vsim2           H ð         ` /M`      ldo_vsram_others_sshub          9vsram_others_sshub          H ¡         ` ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi            ~    p            �                Ãpmif spmimst            $   -   8        4   -   ¬        Š   .      .       -   8      (  ‘pmif_sys_ck pmif_tmr_ck spmimst_clk_mux       iommu@10315000            mediatek,mt8188-iommu-infra         ~    1P                -                     K           O   j      mailbox@10320000              mediatek,mt8188-gce         ~    2        @         -       â               X           Š   .           O   x      mailbox@10330000              mediatek,mt8188-gce         ~    3        @         -       ä               X           Š   .           O   z      scp@10720000              mediatek,mt8188-scp-dual            ~    r                 Ãcfg                      +           O        P             Jokay       scp@0             mediatek,scp-core           ~               Ãsram            -      Î               Jokay            Qdefault         _   A        dmediatek/mt8188/scp.img         r   B        O   {      scp@d0000             mediatek,scp-core           ~    ð         Ãsram            -      Ï             	  Jdisabled             audio-controller@10b10000             mediatek,mt8188-afe         ~    ±                 $   -   S        4   -   „      ´  Š   C   ,   	   ,   
   -   ³   -   ´   -   µ   -   ¶   -   ¸   -   S   -      -       -   E   -   Q   -   M   -   N   -   O   -   P   ?       -   „   -   †   -   ·   -   T   -   R      ÿ  ‘clk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          -      6               €   D           Ž   E         	  •audiosys            �   .        ¡   -        Jokay            r   F        ³            Ô           O         adsp@10b80000             mediatek,mt8188-dsp       @  ~    ¸              Ð             ¸°            ¸ð                Ãcfg sram sec bus            $   -   D        Š   -   D   -   E        ‘audiodsp adsp_bus           ô   G   H        ûrx tx           €   D           Jokay            r   I   J        Qdefault         _   K        O         mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         ~    ¸a                -      Þ               X            O   G      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         ~    ¸q                -      ß               X            O   H      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m           ~    ¹                Ü           O   ?      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -       �               Š   C   .         	  ‘baud bus            Jokay            Qdefault         _   L      serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -       Ž               Š   C   .         	  ‘baud bus          	  Jdisabled          serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -       �               Š   C   .         	  ‘baud bus          	  Jdisabled          serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart           ~                     -      Ó               Š   C   .         	  ‘baud bus          	  Jdisabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc           ~                      Š   .           ‘main            ì           Jokay          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon           ~     0                Ü           O   >      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                      -       ¿               Š   -   y   -      .           ‘parent-clk sel-clk spi-clk          Jokay            Qdefault         _   M   ec@0              google,cros-ec-spi          ~            Ø   *   •           Qdefault         _   N         -ÆÀ   i2c-tunnel            google,cros-ec-i2c-tunnel                                   +       sbs-battery@f             sbs,sbs-battery         ~           *           >            cbas              google,cros-cbas          keyboard-controller           google,cros-ec-keyb         S           c            v     D  �  ž ­t x à á ø	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	 Ž + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      (  �               	  	                 thermal-sensor@1100b000           mediatek,mt8188-lvts-ap         ~     °                -       È               Š   .           Ž   .           ²   O        ¾lvts-calib-data-1           Ï           O   &      pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           ~     à                Š   -   '   .   /        ‘main mm         -       Ë               å           Jokay            Qdefault         _   P        O   °      pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           ~     ð                Š   -   (   .   F        ‘main mm         -                     å         	  Jdisabled            Qdefault         _   Q      spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                     -       À               Š   -   y   -      .   2        ‘parent-clk sel-clk spi-clk          Jokay            Qdefault sleep           _   R        i   S      spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~                     -       Á               Š   -   y   -      .   3        ‘parent-clk sel-clk spi-clk          Jokay            Qdefault         _   T      spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~    0                -       Â               Š   -   y   -      .   4        ‘parent-clk sel-clk spi-clk        	  Jdisabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~    €                -       Ã               Š   -   y   -      .   8        ‘parent-clk sel-clk spi-clk        	  Jdisabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ~    �                -       Ä               Š   -   y   -      .   9        ‘parent-clk sel-clk spi-clk        	  Jdisabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ~            -ÿ     >              	  Ãmac ippc            O                     ?                      +           -       €               $   -   )        4   -   v        Š   >   	   -   Å   >   
        ‘sys_ck ref_ck mcu_ck            ð   U      V            õ        	   W  h           Jokay            	host            	"   X   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ~                       Ãmac         -       �               $   -   *        4   -   v        Š   >   
        ‘sys_ck          Jokay            	"   X        	0   Y         ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a          ~           @         -      Ì               	<macirq        0  Š   >       >      -   A   -   B   -   C   >         .  ‘axi apb mac_main ptp_ref rmii_internal mac_cg           $   -   A   -   B   -   C        4   -       -   ¢   -   £        €   D           	L   .        	]   Z        	m   [        	€   \        	“           	ž           	©          	  Jdisabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           	¶                                 	À           	Ð           O   Z      rx-queues-config            	à            	ö        O   [   queue0           
        
          queue1           
        
          queue2           
        
          queue3           
        
             tx-queues-config            
2            
H        O   \   queue0           
        
Z            
h         queue1           
        
Z           
h         queue2           
        
Z           
h         queue3           
        
Z           
h               mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ~    #             õ                 -       ƒ                Š   -      .      .      .   M      !  ‘source hclk source_cg crypto_clk            Jokay            
t            
~         
�        
¡ H        
ëÂ          
°         
¿         
Î         
è         
î         
ö        Qdefault state_uhs           _   ]        i   ^                    _           `      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ~    $             ë                 -       ‡               Š   -      .      .   $        ‘source hclk source_cg           $   -           4   -   �      	  Jdisabled          mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ~    %             æ                 -       ˆ               Š   -      .      .   A        ‘source hclk source_cg           $   -           4   -   �      	  Jdisabled          thermal-sensor@11278000           mediatek,mt8188-lvts-mcu            ~    '€                -       Ê               Š   .           Ž   .            ²   O        ¾lvts-calib-data-1           Ï           O         i2c@11280000              mediatek,mt8188-i2c          ~    (             " €       €        -       —               *           Š   a       .   7      	  ‘main dma                         +            Jokay            Qdefault         _   b        � €   audio-codec@19            everest,es8326          ~           Ø   *   l           Qdefault         _   c        Ç            4           E            O         amplifier@4f              ti,tas2563 ti,tas2781           ~   O   L        [   *   v            Ç            O            i2c@11281000              mediatek,mt8188-i2c          ~    (            "€       €        -       ’               *           Š   a      .   7      	  ‘main dma                         +            Jokay            Qdefault         _   d        � €      i2c@11282000              mediatek,mt8188-i2c          ~    (             "€       €        -       “               *           Š   a      .   7      	  ‘main dma                         +            Jokay            Qdefault         _   e        � €      clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c          ~    (0                Ü           O   a      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ~    *       -ÿ    *>              	  Ãmac ippc            O            *        ?                      +           -                     $   -   -        4   -   v        Š   >      -   Ë   >           ‘sys_ck ref_ck mcu_ck            ð   f            õ        	   W  p           Jokay            	host            	"   X   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ~                       Ãmac         -                     $   -   .        4   -   v        Š   >           ‘sys_ck          Jokay             g         usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ~    +       -ÿ    +>              	  Ãmac ippc            O            +        ?                      +           -                     $   -   ,        4   -   v        Š   >      -   É   >           ‘sys_ck ref_ck mcu_ck            ð   g            õ        	   W  `           Jokay            	host            	"   X   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ~                       Ãmac         -                     $   -   +        4   -   v        Š   >           ‘sys_ck          Jokay            	0   h         pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie           ~    /                	  Ãpcie-mac            O‚                                  x       ÿ        rpci         ‚                         +         0  Š   .   L   .   #   .   &   .   +   .   C   >         /  ‘pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          p           -                   `  “                  i                      i                     i                     i           ¡                       ´       j      ÿÿ        ¾            ð   k         	  Ípcie-phy            €   D           Ž   E           •mac         Jokay            Qdefault         _   l   interrupt-controller                         p            ˜        O   i         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor         ~    2À                Š   -   X   >      >           ‘spi sf axi          $   -   X        -      9                            +            Jokay            Qdefault         _   m   flash@0           jedec,spi-nor           ~            u          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3           O        Â                         +           €   D           Jokay       pcie-phy@0          ~               Š   -   Ä        ‘ref         ×           O   k         dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         ~    È                 Š   C        émipi_tx0_pll            Ü            ×            Jokay            â  P        O   “      dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         ~    É                 Š   C        émipi_tx0_pll            Ü            ×          	  Jdisabled            O   œ      i2c@11e00000              mediatek,mt8188-i2c          ~    à             "        €        -       ˜               *           Š   n       .   7      	  ‘main dma                         +            Jokay            Qdefault         _   o        � €   tpm@50            google,cr50         ~   P        Ø   *               Qdefault         _   p         i2c@11e01000              mediatek,mt8188-i2c          ~    à            "€       €        -       ”               *           Š   n      .   7      	  ‘main dma                         +            Jokay            Qdefault         _   q        � €      clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w          ~    à                 Ü           O   n      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           O        ã             Jokay       usb-phy@0           ~               Š   -   Ê   ,           ‘ref da_ref          ×           O   g         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           O        ä             Jokay       usb-phy@0           ~               Š   -   Æ   ,           ‘ref da_ref          ×           O   U      usb-phy@700         ~              Š   ,      C        ‘ref da_ref          ×           O   V         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           O        è             Jokay       usb-phy@0           ~               Š   -   Ì   ,           ‘ref da_ref          ×           O   f         i2c@11ec0000              mediatek,mt8188-i2c          ~    ì             "€       €        -       •               *           Š   r       .   7      	  ‘main dma                         +            Jokay            Qdefault         _   s        � €      i2c@11ec1000              mediatek,mt8188-i2c          ~    ì            "        €        -       –               *           Š   r      .   7      	  ‘main dma                         +            Jokay            Qdefault         _   t        � €      clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en         ~    ì                 Ü           O   r      efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse         ~    ò                              +      dp-calib@1a0            ~              O   ¬      lvts1-calib@1ac         ~  ¬   @        O   O      gpu-speedbin@581            ~  �           ú               O   v      socinfo-data1@7a0           ~            socinfo-data2@7e0           ~  à            gpu@13000000          )    mediatek,mt8188-mali arm,mali-valhall-jm            ~             @         Š   u          0  -                   ~             }               	<job mmu gpu         ²   v      
  ¾speed-bin           ÿ   w        €   D      D      D           core0 core1 core2           @           Jokay            &   +        O   (      clock-controller@13fbf000             mediatek,mt8188-mfgcfg          ~    ûð                Ü           O   u      syscon@14000000           mediatek,mt8188-vppsys0 syscon          ~                      Ü           O   0      dma-controller@14001000           mediatek,mt8188-mdp3-rdma           ~                     2           Š   0         <  ô   x         x         x         x         x              =   y   €        €   D           D   z                  \              p   {      display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ~                      Š   0            D   z                 display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ~     @                Š   0   "        D   z      @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ~     P                -      F               Š   0   
        €   D           D   z      P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ~     `                Š   0           D   z      `            \    %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ~     p                Š   0   #        D   z      p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ~     €                -      I               Š   0   $        €   D           D   z      €          display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl           ~     �                -      J               Š   0   %        €   D           D   z      �            =   y   ‚      display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ~                      Š   0           €   D           D   z                 display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc           ~     °                Š   0           D   z      °          display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ~     À                2           Š   0           =   y   ƒ        €   D           D   z      À            \    +      mutex@1400f000            mediatek,mt8188-vpp-mutex           ~     ð                -      P               Š   0           €   D           D   z      ð          smi@14012000              mediatek,mt8188-smi-common-vpp          ~                     Š   0      0           ‘apb smi         €   D           O   |      smi@14013000              mediatek,mt8188-smi-larb            ~    0                Š   0      0           ‘apb smi         €   D           }           Ž   |        O         iommu@14018000            mediatek,mt8188-iommu-vpp           ~    €       P         Š   0           ‘bclk            -      R               €   D           K           ›   }   ~      €   �   ‚        O   y      dma-controller@14f09000           mediatek,mt8188-mdp3-rdma           ~    ð�                2           Š   2   
        =   ƒ   ¤        €   D           D   z   	  �            \  …  ©      dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma           ~    ð                 2           Š   2           =   y   À        €   D           D   z   	               \  †  ª      display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ~    ðÀ                Š   2           D   z   	  À          display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ~    ðÐ                Š   2           D   z   	  Ð          display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ~    ðð                Š   2   "        D   z   	  ð          display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ~    ñ                 Š   2   $        D   z   
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ~    ñ                 -      j               Š   2   #        €   D           D   z   
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ~    ñ0                -      k               Š   2   %        €   D           D   z   
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ~    ñP                Š   2           D   z   
  P            \  ‘  °      display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ~    ñ`                Š   2           D   z   
  `            \  ’  ±      display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ~    ñ€                Š   2           D   z   
  €          display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ~    ñ�                Š   2           D   z   
  �          display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           ~    ñ                 Š   2           €   D           D   z   
             display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           ~    ñ°                Š   2           €   D           D   z   
  °          display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ~    ñÐ                -      u               Š   2           €   D           D   z   
  Ð          display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ~    ñà                -      v               Š   2           €   D           D   z   
  à          display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ~    ò                Š   2           €   D           D   z               display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ~    ò                 Š   2           €   D           D   z                display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ~    ò@                2           Š   2           =   ƒ   ¦        €   D           D   z     @            \     ¬      display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ~    òP                2           Š   2           =   y   Â        €   D           D   z     P            \  ¡  ­      clock-controller@14e00000             mediatek,mt8188-wpesys          ~    à                 Ü           O   =      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0         ~    à                 Ü         smi@14e04000              mediatek,mt8188-smi-larb            ~    à@                Š   =      =           ‘apb smi         €   D           }           Ž   |        O   �      syscon@14f00000           mediatek,mt8188-vppsys1 syscon          ~    ð                 Ü           O   2      mutex@14f01000            mediatek,mt8188-vpp-mutex           ~    ð                -      {               Š   2   &        €   D           D   z   	            smi@14f02000              mediatek,mt8188-smi-larb            ~    ð                 Š   2      2           ‘apb smi         €   D           }           Ž   „        O   ¢      smi@14f03000              mediatek,mt8188-smi-larb            ~    ð0                Š   2      2           ‘apb smi         €   D           }           Ž   |        O   €      clock-controller@15000000             mediatek,mt8188-imgsys          ~                      Ü         clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top         ~                     Ü           ¶         clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr          ~                     Ü           ¶         clock-controller@15220000             mediatek,mt8188-imgsys-wpe1         ~    "                 Ü           ¶         clock-controller@15330000             mediatek,mt8188-ipesys          ~    3                 Ü           ¶         clock-controller@15520000             mediatek,mt8188-imgsys-wpe2         ~    R                 Ü           ¶         clock-controller@15620000             mediatek,mt8188-imgsys-wpe3         ~    b                 Ü           ¶         clock-controller@16000000             mediatek,mt8188-camsys          ~                      Ü           O   6      clock-controller@1604f000             mediatek,mt8188-camsys-rawa         ~    ð                Ü           ¶           O   9      clock-controller@1606f000             mediatek,mt8188-camsys-yuva         ~    ð                Ü           ¶           O   :      clock-controller@1608f000             mediatek,mt8188-camsys-rawb         ~    ð                Ü           ¶           O   7      clock-controller@160af000             mediatek,mt8188-camsys-yuvb         ~    
ð                Ü           ¶           O   8      clock-controller@17200000             mediatek,mt8188-ccusys          ~                      Ü         video-decoder@18000000            mediatek,mt8188-vcodec-dec           ~                   @                O                    `         =   y  æ                     +           p   {   video-codec@10000             mediatek,mtk-vcodec-lat         ~                      $   -   4        4   -   x         Š   -   4   3      3      -   x        ‘sel vdec lat top            -      Ä             H  =   y  à   y  á   y  â   y  ã   y  ä   y  å   y  æ   y  ç   y  è        €   D         video-codec@25000             mediatek,mtk-vcodec-core            ~     P                $   -   4        4   -   x         Š   -   4   4      4      -   x        ‘sel vdec lat top            -      Ã             X  =   ƒ  À   ƒ  Á   ƒ  Â   ƒ  Ã   ƒ  Ä   ƒ  Å   ƒ  Æ   ƒ  Ç   ƒ  È   ƒ  É   ƒ  Ê        €   D            smi@1800d000              mediatek,mt8188-smi-larb            ~     Ð                Š   3       3            ‘apb smi         €   D           }           Ž   |        O   ‚      clock-controller@1800f000             mediatek,mt8188-vdecsys-soc         ~     ð                Ü           O   3      smi@1802e000              mediatek,mt8188-smi-larb            ~    à                Š   4       4            ‘apb smi         €   D           }           Ž   „        O   ¤      clock-controller@1802f000             mediatek,mt8188-vdecsys         ~    ð                Ü           O   4      clock-controller@1a000000             mediatek,mt8188-vencsys         ~                      Ü           O   <      smi@1a010000              mediatek,mt8188-smi-larb            ~                     Š   <      <           ‘apb smi         €   D           }           Ž   „        O   £      video-encoder@1a020000            mediatek,mt8188-vcodec-enc          ~                                  +           $   -   3        4   -   p        Š   <         	  ‘venc_sel            -      a             X  =   ƒ      ƒ  ¡   ƒ  ¢   ƒ  £   ƒ  ¤   ƒ  ¶   ƒ  ·   ƒ  ¸   ƒ  ¹   ƒ  ª   ƒ  º        €   D           p   {      jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc          ~                     Š   <           ‘jpgenc          -      b                =   ƒ  §   ƒ  ¨   ƒ  ©   ƒ  ¬        €   D         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec           ~                     Š   <       <           ‘jpgdec-smi jpgdec           -      c             0  =   ƒ  ­   ƒ  ®   ƒ  ²   ƒ  ³   ƒ  ´   ƒ  µ        €   D         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl           ~                      Š   1            -      |               =   ƒ           €   D           D   x             ports                        +       port@0          ~       endpoint            ª   …        O   Ÿ         port@1          ~      endpoint            ª   †        O   ‡               rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma         ~                      Š   1           -      ~               =   y            €   D           D   x             ports                        +       port@0          ~       endpoint            ª   ‡        O   †         port@1          ~      endpoint            ª   ˆ        O   ‰               color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color           ~     0                Š   1           -                     €   D           D   x     0       ports                        +       port@0          ~       endpoint            ª   ‰        O   ˆ         port@1          ~      endpoint            ª   Š        O   ‹               ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr           ~     @                Š   1           -      €               €   D           D   x     @       ports                        +       port@0          ~       endpoint            ª   ‹        O   Š         port@1          ~      endpoint            ª   Œ        O   �               aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal           ~     P                Š   1           -      �               €   D           D   x     P       ports                        +       port@0          ~       endpoint            ª   �        O   Œ         port@1          ~      endpoint            ª   Ž        O   �               gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma           ~     `                Š   1           -      ‚               €   D           D   x     `       ports                        +       port@0          ~       endpoint            ª   �        O   Ž         port@1          ~      endpoint            ª   �        O   �               dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither         ~     p                Š   1           -      ƒ               €   D           D   x     p       ports                        +       port@0          ~       endpoint            ª   ‘        O   ž         port@1          ~      endpoint            ª   ’        O   š               dsi@1c008000              mediatek,mt8188-dsi         ~     €                Š   1      1      “        ‘engine digital hs           -      „               ð   “        Ídphy            €   D           Ž   1           Jokay                         +       panel@0         ~            º   *               Qdefault         _   ”        Ç   •        Ñ   –        Ý   —        é   ˜        ÷          Jokay              ivo,t109nw41 himax,hx83102     port       endpoint            ª   ™        O   ›            ports                        +       port@0          ~       endpoint            ª   š        O   ’         port@1          ~      endpoint            ª   ›        O   ™               dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc           ~     �                Š   1   
        -      …               €   D           D   x     �          dsi@1c012000              mediatek,mt8188-dsi         ~                     Š   1   	   1      œ        ‘engine digital hs           -      Ž               ð   œ        Ídphy            €   D           Ž   1   	      	  Jdisabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~    @                Š   1      ;           ‘merge merge_async           -      �               €   D           D   x     @          dp-intf@1c015000              mediatek,mt8188-dp-intf         ~    P                Š   1       1      ,           ‘pixel engine pll            -      ‘               €   D         	  Jdisabled          mutex@1c016000            mediatek,mt8188-disp-mutex          ~    `                Š   1           -      ’               €   D           D   x     `            \  >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask         ~                     Š   1           -      •               €   D           D   x             ports                        +       port@0          ~       endpoint            ª   �        O   �         port@1          ~      endpoint            ª   ž        O   ‘               syscon@1c01d000           mediatek,mt8188-vdosys0 syscon          ~    Ð                Ü           ¶           ô   x               D   x     Ð            O   1   port                         +       endpoint@0          ~            ª   Ÿ        O   …            smi@1c022000              mediatek,mt8188-smi-larb            ~                     Š   1      1           ‘apb smi         €   D           }            Ž   „        O          smi@1c023000              mediatek,mt8188-smi-larb            ~    0                Š   1      1           ‘apb smi         €   D           }           Ž   |        O   }      smi@1c024000              mediatek,mt8188-smi-common-vdo          ~    @                Š   1      1           ‘apb smi         €   D           O   „      iommu@1c028000            mediatek,mt8188-iommu-vdo           ~    €       P         Š   1           ‘bclk            -      ¡               €   D           K           ›       ¡   ¢   £   ¤        O   ƒ      syscon@1c100000           mediatek,mt8188-vdosys1 syscon          ~                     Ü           ¶           ô   x              D   x                  O   ;   port                         +       endpoint@1          ~           ª   ¥        O   ª            mutex@1c101000            mediatek,mt8188-disp-mutex          ~                    Š   ;           -      î               €   D           D   x                 \  Å      smi@1c102000              mediatek,mt8188-smi-larb            ~                     Š   ;       ;            ‘apb smi         €   D           }           Ž   „        O   ¡      smi@1c103000              mediatek,mt8188-smi-larb            ~    0                Š   ;      ;           ‘apb smi         €   D           }           Ž   |        O   ~      rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    @                Š   ;           -      ï               =   ƒ   @        €   D           2           D   x     @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    P                Š   ;           -      ð               =   y   `        €   D           2           D   x     P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    `                Š   ;           -      ñ               =   ƒ   A        €   D           2           D   x     `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    p                Š   ;           -      ò               =   y   a        €   D           2           D   x     p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    €                Š   ;           -      ó               =   ƒ   B        €   D           2           D   x     €          rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    �                Š   ;           -      ô               =   y   b        €   D           2           D   x     �          rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~                     Š   ;           -      õ               =   ƒ   C        €   D           2           D   x                rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ~    °                Š   ;           -      ö               =   y   c        €   D           2           D   x     °          merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~    À                Š   ;   	   ;           ‘merge merge_async           -      ÷               €   D           Ž   ;           D   x     À                    merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~    Ð                Š   ;   
   ;           ‘merge merge_async           -      ø               €   D           Ž   ;           D   x     Ð                    merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~    à                Š   ;      ;           ‘merge merge_async           -      ù               €   D           Ž   ;           D   x     à                    merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~    ð                Š   ;      ;           ‘merge merge_async           -      ú               €   D           Ž   ;           D   x     ð                    merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ~                     Š   ;      ;           ‘merge merge_async           -      û               €   D           Ž   ;           D   x                      ports                        +       port@0                       +            ~       endpoint@1          ~           ª   ¦        O   «         port@1                       +            ~      endpoint@1          ~           ª   §        O   ¨               dp-intf@1c113000              mediatek,mt8188-dp-intf         ~    0                Š   ;   :   ;      ,           ‘pixel engine pll            -                     €   D           Jokay       ports                        +       port@0                       +            ~       endpoint@1          ~           ª   ¨        O   §         port@1                       +            ~      endpoint@1          ~           ª   ©        O   ®               ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p  ~    @            P            p            �                         °            À              4  Ãmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h  Š   ;   0   ;   +   ;   .   ;   ,   ;   /   ;   -   ;   <   ;   1   ;   2   ;   3   ;   4   ;   5   -         ƒ  ‘mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          -      6               =   y   d   y   e        €   D         (  Ž   ;   1   ;   2   ;   3   ;   4   ;   5      p  D   x     @       x     P       x     p       x     �       x             x     °       x     À       ports                        +       port@0                       +            ~       endpoint@1          ~           ª   ª        O   ¥         port@1                       +            ~      endpoint@1          ~           ª   «        O   ¦               padding@1c11d000              mediatek,mt8188-disp-padding            ~    Ð                Š   ;           €   D           D   x     Ð          padding@1c11e000              mediatek,mt8188-disp-padding            ~    à                Š   ;            €   D           D   x     à          padding@1c11f000              mediatek,mt8188-disp-padding            ~    ð                Š   ;   !        €   D           D   x     ð          padding@1c120000              mediatek,mt8188-disp-padding            ~                     Š   ;   "        €   D           D   x                padding@1c121000              mediatek,mt8188-disp-padding            ~                    Š   ;   #        €   D           D   x               padding@1c122000              mediatek,mt8188-disp-padding            ~                     Š   ;   $        €   D           D   x                padding@1c123000              mediatek,mt8188-disp-padding            ~    0                Š   ;   %        €   D           D   x     0          padding@1c124000              mediatek,mt8188-disp-padding            ~    @                Š   ;   &        €   D           D   x     @          edp-tx@1c500000           mediatek,mt8188-edp-tx          ~    P        €         -      ¤               ²   ¬        ¾dp_calibration_data         €   D           +  ¤      	  Jdisabled          dp-tx@1c600000            mediatek,mt8188-dp-tx           ~    `        €         -      Ê               ²   ¬        ¾dp_calibration_data         €   D           +          Jokay            Qdefault         _   ­        Ç            O      ports                        +       port@0          ~       endpoint            ª   ®        O   ©         port@1          ~      endpoint            <                               backlight-lcd0            pwm-backlight           G      ÿ        Y  @        º   *               r  ÿ        ‰   ¯        –   °     ¡         O   •      chosen          ›serial0:115200n8          dmic-codec            dmic-codec          §           ´   d      memory@40000000         rmemory          ~    @                 regulator-pp1800-ldo-z1           regulator-fixed         9pp1800_ldo_z1            ”         Ä        H w@        ` w@        Ö   h      regulator-pp3300-s3           regulator-fixed       
  9pp3300_s3            ”         Ä        H 2Z         ` 2Z         Ö   h        O   X      regulator-pp3300-z1           regulator-fixed       
  9pp3300_z1            ”         Ä        H 2Z         ` 2Z         Ö   ¯        O   h      regulator-pp3300-wlan             regulator-fixed         9pp3300_wlan          ”        H 2Z         ` 2Z          á        ô   *               _   ±        Qdefault         Ö   h      regulator-pp4200-s5           regulator-fixed       
  9pp4200_s5            ”         Ä        H @@        ` @@        Ö   ¯      regulator-pp5000-z1           regulator-fixed       
  9pp5000_z1            ”         Ä        H LK@        ` LK@        Ö   ¯        O   ²      regulator-pp5000-usb-vbus             regulator-fixed         9pp5000_usb_vbus         H LK@        ` LK@         á        ô   *   –            Ö   ²        O   Y      regulator-ppvar-sys           regulator-fixed       
  9ppvar_sys            ”         Ä        O   ¯      regulator-ppvar-mipi-disp-avdd            regulator-fixed         9ppvar_mipi_disp_avdd             á        ô   *               Qdefault         _   ³        Ö   ²        O   –      regulator-ppvar-mipi-disp-avee            regulator-fixed         9ppvar_mipi_disp_avee            x  '         á        ô   *               Qdefault         _   ´        Ö   ²        O   —      reserved-memory                      +            O   memory@50000000           shared-dma-pool         ~    P        €           ù        O   B      memory@55000000           shared-dma-pool         ~    U       @        memory@60000000           shared-dma-pool         ~    `        ð           ù        O   J      memory@60f00000           shared-dma-pool         ~    `ð                  ù        O   F      memory@61000000           shared-dma-pool         ~    a                   ù        O   I            	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 dsi0 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 mmc0 serial0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status pinctrl-names pinctrl-0 pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 mediatek,adsp audio-routing link-name dai-format mediatek,clk-provider sound-dai polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux bias-pull-down input-enable drive-strength output-high bias-disable output-low bias-pull-up #power-domain-cells domain-supply clocks clock-names mediatek,infracfg mediatek,disable-extrst #sound-dai-cells interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread regulator-microvolt-offset assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells firmware-name memory-region power-domains resets reset-names mediatek,topckgen mediatek,etdm-out1-cowork-source mediatek,etdm-in2-cowork-source mboxes mbox-names spi-max-frequency google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells phys wakeup-source mediatek,syscon-wakeup dr_mode vusb33-supply vbus-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay mmc-hs200-1_8v mmc-hs400-1_8v mmc-hs400-enhanced-strobe no-sd no-sdio non-removable supports-cqe vmmc-supply vqmmc-supply clock-div everest,jack-pol everest,interrupt-clk reset-gpios usb2-lpm-disable bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names #phy-cells drive-strength-microamp bits operating-points-v2 power-domain-names mali-supply #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs remote-endpoint enable-gpios backlight avdd-supply avee-supply pp1800-supply rotation mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz data-lanes brightness-levels default-brightness-level num-interpolated-steps power-supply pwms stdout-path num-channels wakeup-delay-ms regulator-boot-on vin-supply enable-active-high gpio no-map 