Ðþí  ¯.   8  ¨ä   (            J  ¨¬                             $    mediatek,mt8192-evb mediatek,mt8192                                  +         !   7MediaTek MT8192 evaluation board       aliases          =/soc/ovl@14005000            B/soc/ovl@14006000            J/soc/ovl@14014000            R/soc/rdma@14007000           X/soc/rdma@14015000           ^/soc/serial@11002000          fixed-factor-clock-13m            fixed-factor-clock           f             s            z            „            �clk13m           ¢   $      oscillator0           fixed-clock          f             ªŒº€         �clk26m           ¢         oscillator1           fixed-clock          f             ª  €          �clk32k        cpus                         +       cpu@0            ºcpu           arm,cortex-a55           Æ             Êpsci             ªec3@         Ø               è  €          õ   @           €          €         !   @        3   €        @           Q               e  «        x            ¢   
      cpu@100          ºcpu           arm,cortex-a55           Æ            Êpsci             ªec3@         Ø               è  €          õ   @           €          €         !   @        3   €        @           Q               e  «        x            ¢         cpu@200          ºcpu           arm,cortex-a55           Æ            Êpsci             ªec3@         Ø               è  €          õ   @           €          €         !   @        3   €        @           Q               e  «        x            ¢         cpu@300          ºcpu           arm,cortex-a55           Æ            Êpsci             ªec3@         Ø               è  €          õ   @           €          €         !   @        3   €        @           Q               e  «        x            ¢         cpu@400          ºcpu           arm,cortex-a76           Æ            Êpsci             ª�fÔÀ         Ø               è            õ   @                              !   @        3           @   	        Q              e           x            ¢         cpu@500          ºcpu           arm,cortex-a76           Æ            Êpsci             ª�fÔÀ         Ø               è            õ   @                              !   @        3           @   	        Q              e           x            ¢         cpu@600          ºcpu           arm,cortex-a76           Æ            Êpsci             ª�fÔÀ         Ø               è            õ   @                              !   @        3           @   	        Q              e           x            ¢         cpu@700          ºcpu           arm,cortex-a76           Æ            Êpsci             ª�fÔÀ         Ø               è            õ   @                              !   @        3           @   	        Q              e           x            ¢         cpu-map    cluster0       core0           ‡   
      core1           ‡         core2           ‡         core3           ‡         core4           ‡         core5           ‡         core6           ‡         core7           ‡               l2-cache0             cache           ‹            ê            ÷   @        	           @            —         ¢         l2-cache1             cache           ‹            ê            ÷   @        	           @            —         ¢   	      l3-cache              cache           ‹            ê             ÷   @        	            —         ¢         idle-states         ¥psci       cpu-retention-l           arm,idle-state          ²           É        Ú   7        ë   Œ        û           ¢         cpu-retention-b           arm,idle-state          ²           É        Ú   #        ë   ‘        û  Ð         ¢         cpu-off-l             arm,idle-state          ²          É        Ú   <        ë   ›        û  \         ¢         cpu-off-b             arm,idle-state          ²          É        Ú   (        ë   ›        û           ¢               pmu-a55           arm,cortex-a55-pmu                                        pmu-a76           arm,cortex-a76-pmu                                        psci              arm,psci-1.0             Ñsmc       timer             arm,armv8-timer                   @                                               
                ª Æ]@      opp-table-0           operating-points-v2                   ¢   5   opp-358000000           "    V¥€        ) 	@*      opp-399000000           "    ÈAÀ        ) 	pþ      opp-440000000           "    9Þ         ) 	¡Ò      opp-482000000           "    º¼€        ) 	Ò¦      opp-523000000           "    ,XÀ        ) 
z      opp-564000000           "    !�õ         ) 
4N      opp-605000000           "    $‘@        ) 
e"      opp-647000000           "    &�oÀ        ) 
•ö      opp-688000000           "    )         ) 
ÆÊ      opp-724000000           "    +']         )       opp-748000000           "    ,•“         ) @Ü      opp-772000000           "    .É         ) q°      opp-795000000           "    /b¼À        ) ¢„      opp-819000000           "    0ÐòÀ        ) ÓX      opp-843000000           "    2?(À        ) ,      opp-866000000           "    3ž€        ) 5          soc                      +             simple-bus          7                                ;   performance-controller@11bc10             mediatek,cpufreq-hw           Æ     ¼            ½0               B            ¢         interrupt-controller@c000000              arm,gic-v3          \           m                        „          Æ                                          	                ¢      ppi-partitions     interrupt-partition-0           ™   
                  ¢         interrupt-partition-1           ™                     ¢               syscon@10000000            mediatek,mt8192-topckgen syscon          Æ                       f            ¢         syscon@10001000            mediatek,mt8192-infracfg syscon          Æ                      f           ¢            ¢         syscon@10003000           mediatek,mt8192-pericfg syscon           Æ     0                 f            ¢   *      pinctrl@10005000              mediatek,mt8192-pinctrl       °   Æ     P            Â             Ñ             Ó             Ô             â             ç             ê             ò             ó              °              ]  ¯iocfg0 iocfg_rm iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_lb iocfg_rt iocfg_lt iocfg_tl eint             ¹        É           Õ              Ü         „               Ô               \            ¢         syscon@10006000       )    mediatek,mt8192-scpsys syscon simple-mfd             Æ     `           power-controller          !    mediatek,mt8192-power-controller                         +            á            ¢   ,   power-domain@0           Æ             s            :      /        õaudio audio1 audio2                    á          power-domain@1           Æ            s              õconn                       á          power-domain@2           Æ            s                    õmfg alt                      +            á      power-domain@3           Æ                                   +            á      power-domain@4           Æ           á          power-domain@5           Æ           á          power-domain@6           Æ           á          power-domain@7           Æ           á          power-domain@8           Æ           á                power-domain@9           Æ   	      (   s                                    !  õdisp disp-0 disp-1 disp-2 disp-3                                    +            á      power-domain@10          Æ   
      (   s                                       õipe ipe-0 ipe-1 ipe-2 ipe-3                    á          power-domain@11          Æ            s                           õisp isp-0 isp-1                    á          power-domain@12          Æ            s                           õisp2 isp2-0 isp2-1                     á          power-domain@13          Æ            s                  
  õmdp mdp-0                      á          power-domain@14          Æ            s      3              õvenc venc-0                    á          power-domain@15          Æ             s      4                           õvdec vdec-0 vdec-1 vdec-2                                   +            á      power-domain@16          Æ            s                           õvdec2-0 vdec2-1 vdec2-2         á             power-domain@17          Æ         (   s      
                                     õcam cam-0 cam-1 cam-2 cam-3                                 +            á      power-domain@18          Æ            s   !            õcam_rawa-0          á          power-domain@19          Æ            s   "            õcam_rawb-0          á          power-domain@20          Æ            s   #            õcam_rawc-0          á                      watchdog@10007000             mediatek,mt8192-wdt          Æ     p                ¢            ¢   +      syscon@1000c000       "    mediatek,mt8192-apmixedsys syscon            Æ     À                 f            ¢   )      timer@10017000        ,    mediatek,mt8192-timer mediatek,mt6765-timer          Æ    p                       é                s   $      pwrap@10026000            mediatek,mt6873-pwrap            Æ    `                ¯pwrap                  Ü                s                   	  õspi wrap                          #      ƒ   pmic              mediatek,mt6359          „        \           :      adc           mediatek,mt6359-auxadc          K         audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            ]vs1         l 5         „ !‘À        œ             ¸      buck_vgpu11         ]vgpu11          l €        „ 7        Ì  ˆ        œ   È        á                buck_vmodem         ]vmodem          l €        „ Èà        Ì  *        œ   È      buck_vpu            ]vpu         l €        „ 7        Ì  ˆ        œ   È        á                buck_vcore          ]vcore           l €        „ Ö         Ì  ˆ        œ   È        á                buck_vs2            ]vs2         l 5         „ j         œ             ¸      buck_vpa            ]vpa         l ¡         „ 7±Ð        œ  ,      buck_vproc2         ]vproc2          l €        „ 7        Ì  L        œ   È        á                buck_vproc1         ]vproc1          l €        „ 7        Ì  L        œ   È        á                buck_vcore_sshub            ]vcore_sshub         l €        „ 7      buck_vgpu11_sshub           ]vgpu11_sshub            l €        „ 7      ldo_vaud18          ]vaud18          l w@        „ w@        œ   ð      ldo_vsim1           ]vsim1           l ð         „ /M`      ldo_vibr            ]vibr            l O€        „ 2Z       ldo_vrf12           ]vrf12           l Èà        „ Ö       ldo_vusb            ]vusb            l -ÆÀ        „ -ÆÀ        œ  À         ¸      ldo_vsram_proc2         ]vsram_proc2         l ¡         „ ½¶        Ì  L        œ   ð         ¸      ldo_vio18           ]vio18           l ð         „ ýà        œ  À         ¸      ldo_vcamio          ]vcamio          l ð         „ ýà      ldo_vcn18           ]vcn18           l w@        „ w@        œ   ð      ldo_vfe28           ]vfe28           l *¹€        „ *¹€        œ   x      ldo_vcn13           ]vcn13           l »         „ Ö       ldo_vcn33_1_bt          ]vcn33_1_bt          l *¹€        „ 5gà      ldo_vcn33_1_wifi            ]vcn33_1_wifi            l *¹€        „ 5gà      ldo_vaux18          ]vaux18          l w@        „ w@        œ   ð         ¸      ldo_vsram_others            ]vsram_others            l ¡         „ ½¶        Ì  ˆ        œ   ð      ldo_vefuse          ]vefuse          l ð         „ „€      ldo_vxo22           ]vxo22           l w@        „ !‘À         ¸      ldo_vrfck           ]vrfck           l ã`        „ ð       ldo_vrfck_1         ]vrfck           l ëÀ        „ j       ldo_vbif28          ]vbif28          l *¹€        „ *¹€        œ   ð      ldo_vio28           ]vio28           l *¹€        „ 2Z          ¸      ldo_vemc            ]vemc            l ,@         „ 2Z       ldo_vemc_1          ]vemc            l &%         „ 2Z       ldo_vcn33_2_bt          ]vcn33_2_bt          l *¹€        „ 5gà      ldo_vcn33_2_wifi            ]vcn33_2_wifi            l *¹€        „ 5gà      ldo_va12            ]va12            l O€        „ Ö          ¸      ldo_va09            ]va09            l 5         „ O€      ldo_vrf18           ]vrf18           l ð         „ žP      ldo_vsram_md          	  ]vsram_md            l ¡         „ ½¶        Ì  *        œ   ð      ldo_vufs            ]vufs            l ð         „ ýà      ldo_vm18            ]vm18            l ð         „ ýà         ¸      ldo_vbbck           ]vbbck           l Èà        „ O€      ldo_vsram_proc1         ]vsram_proc1         l ¡         „ ½¶        Ì  L        œ   ð         ¸      ldo_vsim2           ]vsim2           l ð         „ /M`      ldo_vsram_others_sshub          ]vsram_others_sshub          l ¡         „ ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt6873-spmi              Æ    p            �                ¯pmif spmimst             s                   8      (  õpmif_sys_ck pmif_tmr_ck spmimst_clk_mux                       #      ƒ      mailbox@10228000              mediatek,mt8192-gce          Æ    "€       @                Ë               ù            s              õgce          ¢   6      clock-controller@10720000             mediatek,mt8192-scp_adsp             Æ    r                  f           fail          serial@11002000       *    mediatek,mt8192-uart mediatek,mt6577-uart            Æ                             m                s               	  õbaud bus            okay          serial@11003000       *    mediatek,mt8192-uart mediatek,mt6577-uart            Æ     0                       n                s               	  õbaud bus          	  disabled          clock-controller@11007000             mediatek,mt8192-imp_iic_wrap_c           Æ     p                 f         spi@1100a000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             Æ                             Ÿ                s      M                    õparent-clk sel-clk spi-clk        	  disabled          thermal-sensor@1100b000           mediatek,mt8192-lvts-ap          Æ     °                       ©                s      	                          %        lvts-calib-data-1           0            ¢   S      svs@1100bc00              mediatek,mt8192-svs          Æ     ¼                       §                s      	        õmain               &   %      (  svs-calibration-data t-calibration-data                       Fsvs_rst       pwm@1100e000              mediatek,mt8183-disp-pwm             Æ     à                       «               R            s      !      8        õmain mm       	  disabled          spi@11010000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             Æ                                             s      M            <        õparent-clk sel-clk spi-clk        	  disabled          spi@11012000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             Æ                            ¡                s      M            >        õparent-clk sel-clk spi-clk        	  disabled          spi@11013000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             Æ    0                       ¢                s      M            ?        õparent-clk sel-clk spi-clk        	  disabled          spi@11018000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             Æ    €                       £                s      M            L        õparent-clk sel-clk spi-clk        	  disabled          spi@11019000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             Æ    �                       ¤                s      M            M        õparent-clk sel-clk spi-clk        	  disabled          spi@1101d000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             Æ    Ð                       ¥                s      M            m        õparent-clk sel-clk spi-clk        	  disabled          spi@1101e000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             Æ    à                       ¦                s      M            n        õparent-clk sel-clk spi-clk        	  disabled          scp@10500000              mediatek,mt8192-scp       0   Æ    P             r             p        €         ¯sram cfg l1tcm                ³                s              õmain          	  disabled             ¢   I      usb@11200000          '    mediatek,mt8192-xhci mediatek,mtk-xhci            Æ                   >              	  ¯mac ippc            ]          a               qhost            �   '      (                 "      #        #      ]      ]          s      7   )               R      $  õsys_ck ref_ck mcu_ck dma_ck xhci_ck          †        ”   *      f      	  disabled          syscon@11210000           mediatek,mt8192-audsys syscon            Æ    !                   f            ¢   -   mt8192-afe-pcm            mediatek,mt8192-audio                  Ê                  +         	  Faudiosys            «   )                   ¿           Ñ   ,         ¼   s   -       -      -      -      -      -      -      -      -      -      -   	   -   
   -      -      -      -      -      -      -      -         /      :                  H      /      e      0      i      +      g      ,      k      ;      <      =      >      ?      @      A      B      C      D      Ž      �      �      ‘      ’      “      ”      •      –      —      ˜      7        u  õaud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adda6_adc_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_tdm_clk aud_tml_clk aud_nle aud_dac_hires_clk aud_adc_hires_clk aud_adc_hires_tml aud_adda6_adc_hires_clk aud_3rd_dac_clk aud_3rd_dac_predis_clk aud_3rd_dac_tml aud_3rd_dac_hires_clk aud_infra_clk aud_infra_26m_clk top_mux_audio top_mux_audio_int top_mainpll_d4_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d4 top_mux_aud_eng2 top_apll2_d4 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_i2s6_m_sel top_i2s7_m_sel top_i2s8_m_sel top_i2s9_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_apll12_div5 top_apll12_div6 top_apll12_div7 top_apll12_div8 top_apll12_div9 top_mux_audio_h top_clk26m_clk             pcie@11230000             mediatek,mt8192-pcie             ºpci          Æ    #                	  ¯pcie-mac                         +         0   s      +      '      *      j      ^      \      /  õpl_250m tl_26m tl_96m tl_32k peri_26m top_133m                )        #      Q               û               ß       ÿ      8  ;‚                      €  �       €      €       €          \           é                     `  ü                  .                      .                     .                     .      interrupt-controller             „                     \            ¢   .         spi@11234000              mediatek,mt8192-nor          Æ    #@        à              ¯                s      :      w      ]        õspi sf axi                :        #                        +          	  disabled          thermal-sensor@11278000           mediatek,mt8192-lvts-mcu             Æ    '€                       ª                s      	                         %        lvts-calib-data-1           0            ¢   J      efuse@11c10000        %    mediatek,mt8192-efuse mediatek,efuse             Æ    Á                              +      socinfo-data1@44             Æ   D         socinfo-data2@50             Æ   P         data1@1c0            Æ  À   X         ¢   %      calib@580            Æ  €   h         ¢   &         i2c@11cb0000              mediatek,mt8192-i2c           Æ    Ë             !s        €               s                s   /          x      	  õmain dma             z                        +          	  disabled          clock-controller@11cb1000             mediatek,mt8192-imp_iic_wrap_e           Æ    Ë                 f            ¢   /      i2c@11d00000              mediatek,mt8192-i2c           Æ    Ð             !v       €               w                s   0          x      	  õmain dma             z                        +          	  disabled          i2c@11d01000              mediatek,mt8192-i2c           Æ    Ð            !w€      €               x                s   0         x      	  õmain dma             z                        +          	  disabled          i2c@11d02000              mediatek,mt8192-i2c           Æ    Ð             !y       €               y                s   0         x      	  õmain dma             z                        +          	  disabled          clock-controller@11d03000             mediatek,mt8192-imp_iic_wrap_s           Æ    Ð0                 f            ¢   0      i2c@11d20000              mediatek,mt8192-i2c           Æ    Ò             !q        €               q                s   1          x      	  õmain dma             z                        +          	  disabled          i2c@11d21000              mediatek,mt8192-i2c           Æ    Ò            !q€      €               r                s   1         x      	  õmain dma             z                        +          	  disabled          i2c@11d22000              mediatek,mt8192-i2c           Æ    Ò             !s€      €               t                s   1         x      	  õmain dma             z                        +          	  disabled          clock-controller@11d23000              mediatek,mt8192-imp_iic_wrap_ws          Æ    Ò0                 f            ¢   1      i2c@11e00000              mediatek,mt8192-i2c           Æ    à             !u        €               u                s   2          x      	  õmain dma             z                        +          	  disabled          clock-controller@11e01000             mediatek,mt8192-imp_iic_wrap_w           Æ    à                 f            ¢   2      t-phy@11e40000        .    mediatek,mt8192-tphy mediatek,generic-tphy-v2                        +           ;        ä        usb-phy@0            Æ                s           õref         
            ¢   '      usb-phy@700          Æ     	          s           õref         
            ¢   (         dsi-phy@11e50000              mediatek,mt8183-mipi-tx          Æ    å                  s   )   
         f            
             �mipi_tx0_pll          	  disabled             ¢   9      i2c@11f00000              mediatek,mt8192-i2c           Æ    ð             !p€       €               p                s   3          x      	  õmain dma             z                        +          	  disabled          i2c@11f01000              mediatek,mt8192-i2c           Æ    ð            !u€       €               v                s   3         x      	  õmain dma             z                        +          	  disabled          clock-controller@11f02000             mediatek,mt8192-imp_iic_wrap_n           Æ    ð                  f            ¢   3      clock-controller@11f10000             mediatek,mt8192-msdc_top             Æ    ñ                  f            ¢   4      mmc@11f60000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc           Æ    ö             õ                        c             8   s         4   	   4      4      4      4      4         3  õsource hclk source_cg sys_cg pclk_cg axi_cg ahb_cg        	  disabled          mmc@11f70000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc           Æ    ÷             Ç                        g             8   s         4   
   4      4      4      4      4         3  õsource hclk source_cg sys_cg pclk_cg axi_cg ahb_cg        	  disabled          gpu@13000000          )    mediatek,mt8192-mali arm,mali-valhall-jm             Æ             @       0        m             l             k               qjob mmu gpu          s   )         (  Ñ   ,      ,      ,      ,      ,           core0 core1 core2 core3 core4           (   5      	  disabled          clock-controller@13fbf000             mediatek,mt8192-mfgcfg           Æ    ûð                 f         syscon@14000000           mediatek,mt8192-mmsys syscon             Æ                       f           ¢           <   6          6              C   6                   ¢         mutex@14001000            mediatek,mt8192-disp-mutex           Æ                            ü                s               C   6                 [  ²  ³        Ñ   ,   	      smi@14002000              mediatek,mt8192-smi-common           Æ                        s                                õapb smi gals0 gals1         Ñ   ,   	         ¢   7      larb@14003000             mediatek,mt8192-smi-larb             Æ     0                o            €   7         s              õapb smi         Ñ   ,   	         ¢   :      larb@14004000             mediatek,mt8192-smi-larb             Æ     @                o           €   7         s              õapb smi         Ñ   ,   	         ¢   ;      ovl@14005000              mediatek,mt8192-disp-ovl             Æ     P                       þ                s              �   8      8           Ñ   ,   	        C   6     P          ovl@14006000              mediatek,mt8192-disp-ovl-2l          Æ     `                       ÿ               Ñ   ,   	         s              �   8   "   8            C   6     `          rdma@14007000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma          Æ     p                                       s              �   8           ”           Ñ   ,   	        C   6     p          color@14009000        6    mediatek,mt8192-disp-color mediatek,mt8173-disp-color            Æ     �                                     Ñ   ,   	         s              C   6     �          ccorr@1400a000            mediatek,mt8192-disp-ccorr           Æ                                           Ñ   ,   	         s      	        C   6                aal@1400b000          2    mediatek,mt8192-disp-aal mediatek,mt8183-disp-aal            Æ     °                                     Ñ   ,   	         s              C   6     °          gamma@1400c000        6    mediatek,mt8192-disp-gamma mediatek,mt8183-disp-gamma            Æ     À                                     Ñ   ,   	         s              C   6     À          postmask@1400d000             mediatek,mt8192-disp-postmask            Æ     Ð                                     Ñ   ,   	         s              C   6     Ð          dither@1400e000       8    mediatek,mt8192-disp-dither mediatek,mt8183-disp-dither          Æ     à                                     Ñ   ,   	         s      
        C   6     à          dsi@14010000              mediatek,mt8183-dsi          Æ                           	                s                9        õengine digital hs           �   9        ¬dphy            Ñ   ,   	                    	  disabled       port       endpoint                ovl@14014000              mediatek,mt8192-disp-ovl-2l          Æ    @                                     Ñ   ,   	         s              �   8   #   8   !        C   6     @          rdma@14015000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma          Æ    P                                     Ñ   ,   	         s              �   8   %        ”           C   6     P          dpi@14016000              mediatek,mt8192-dpi          Æ    `                                      s      !         )           õpixel engine pll          	  disabled          m4u@1401d000              mediatek,mt8192-m4u          Æ    Ð              <  ¶   :   ;   <   =   >   ?   @   A   B   C   D   E   F   G   H                              s              õbclk            Ñ   ,   	        Å            ¢   8      clock-controller@15020000             mediatek,mt8192-imgsys           Æ                      f            ¢         larb@1502e000             mediatek,mt8192-smi-larb             Æ    à                o   	        €   7         s                      õapb smi         Ñ   ,            ¢   @      clock-controller@15820000             mediatek,mt8192-imgsys2          Æ    ‚                  f            ¢         larb@1582e000             mediatek,mt8192-smi-larb             Æ    ‚à                o           €   7         s                      õapb smi         Ñ   ,            ¢   A      video-codec@16000000              mediatek,mt8192-vcodec-dec           Æ                      Ò   I        �   8   €                     +           ;                    `    video-codec@10000             mediatek,mtk-vcodec-lat          Æ                            ª             @  �   8       8   ¡   8   ¢   8   £   8   ¤   8   ¥   8   ¦   8   §      (   s      4                         F        õsel soc-vdec soc-lat vdec top                 4        #      F        Ñ   ,         video-codec@25000             mediatek,mtk-vcodec-core             Æ     P                      ©             X  �   8   €   8   �   8   ‚   8   ƒ   8   „   8   …   8   †   8   ‡   8   ˆ   8   ‰   8   Š      (   s      4                         F        õsel soc-vdec soc-lat vdec top                 4        #      F        Ñ   ,            larb@1600d000             mediatek,mt8192-smi-larb             Æ     Ð                o           €   7         s                      õapb smi         Ñ   ,            ¢   >      clock-controller@1600f000             mediatek,mt8192-vdecsys_soc          Æ     ð                 f            ¢         larb@1602e000             mediatek,mt8192-smi-larb             Æ    à                o           €   7         s                      õapb smi         Ñ   ,            ¢   =      clock-controller@1602f000             mediatek,mt8192-vdecsys          Æ    ð                 f            ¢         clock-controller@17000000             mediatek,mt8192-vencsys          Æ                       f            ¢         larb@17010000             mediatek,mt8192-smi-larb             Æ                     o           €   7         s                     õapb smi         Ñ   ,            ¢   ?      vcodec@17020000           mediatek,mt8192-vcodec-enc           Æ                    X  �   8   à   8   á   8   â   8   ã   8   ä   8   å   8   æ   8   ç   8   è   8   í   8   î              5               Ò   I        Ñ   ,            s            	  õvenc_sel                  3        #      W      clock-controller@1a000000             mediatek,mt8192-camsys           Æ                       f            ¢          larb@1a001000             mediatek,mt8192-smi-larb             Æ                     o           €   7         s                       õapb smi         Ñ   ,            ¢   B      larb@1a002000             mediatek,mt8192-smi-larb             Æ                      o           €   7         s                      õapb smi         Ñ   ,            ¢   C      larb@1a00f000             mediatek,mt8192-smi-larb             Æ     ð                o           €   7         s   !      !            õapb smi         Ñ   ,            ¢   D      larb@1a010000             mediatek,mt8192-smi-larb             Æ                     o           €   7         s   "      "            õapb smi         Ñ   ,            ¢   E      larb@1a011000             mediatek,mt8192-smi-larb             Æ                    o           €   7         s   #       #           õapb smi         Ñ   ,            ¢   F      clock-controller@1a04f000             mediatek,mt8192-camsys_rawa          Æ    ð                 f            ¢   !      clock-controller@1a06f000             mediatek,mt8192-camsys_rawb          Æ    ð                 f            ¢   "      clock-controller@1a08f000             mediatek,mt8192-camsys_rawc          Æ    ð                 f            ¢   #      clock-controller@1b000000             mediatek,mt8192-ipesys           Æ                       f            ¢         larb@1b00f000             mediatek,mt8192-smi-larb             Æ     ð                o           €   7         s                    õapb smi         Ñ   ,   
         ¢   H      larb@1b10f000             mediatek,mt8192-smi-larb             Æ    ð                o           €   7         s                     õapb smi         Ñ   ,   
         ¢   G      clock-controller@1f000000             mediatek,mt8192-mdpsys           Æ                       f            ¢         larb@1f002000             mediatek,mt8192-smi-larb             Æ                      o           €   7         s                    õapb smi         Ñ   ,            ¢   <         thermal-zones      cpu0-thermal            ß  è        í   ú           J      trips      trip-alert           L          Ð         Ápassive          ¢   K      trip-crit            †           Ð      	   Ácritical             cooling-maps       map0            *   K      0  /   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            ß  è        í   ú           J      trips      trip-alert           L          Ð         Ápassive          ¢   L      trip-crit            †           Ð      	   Ácritical             cooling-maps       map0            *   L      0  /   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            ß  è        í   ú           J      trips      trip-alert           L          Ð         Ápassive          ¢   M      trip-crit            †           Ð      	   Ácritical             cooling-maps       map0            *   M      0  /   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            ß  è        í   ú           J      trips      trip-alert           L          Ð         Ápassive          ¢   N      trip-crit            †           Ð      	   Ácritical             cooling-maps       map0            *   N      0  /   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            ß  è        í   ú           J       trips      trip-alert           L          Ð         Ápassive          ¢   O      trip-crit            †           Ð      	   Ácritical             cooling-maps       map0            *   O      0  /   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            ß  è        í   ú           J      trips      trip-alert           L          Ð         Ápassive          ¢   P      trip-crit            †           Ð      	   Ácritical             cooling-maps       map0            *   P      0  /   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            ß  è        í   ú           J      trips      trip-alert           L          Ð         Ápassive          ¢   Q      trip-crit            †           Ð      	   Ácritical             cooling-maps       map0            *   Q      0  /   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            ß  è        í   ú           J      trips      trip-alert           L          Ð         Ápassive          ¢   R      trip-crit            †           Ð      	   Ácritical             cooling-maps       map0            *   R      0  /   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            ß  è        í   ú           S      trips      trip-alert           L          Ð         Ápassive       trip-crit            †           Ð      	   Ácritical                vpu1-thermal            ß  è        í   ú           S   	   trips      trip-alert           L          Ð         Ápassive       trip-crit            †           Ð      	   Ácritical                gpu-thermal         ß  è        í   ú           S   
   trips      trip-alert           L          Ð         Ápassive       trip-crit            †           Ð      	   Ácritical                gpu1-thermal            ß  è        í   ú           S      trips      trip-alert           L          Ð         Ápassive       trip-crit            †           Ð      	   Ácritical                infra-thermal           ß  è        í   ú           S      trips      trip-alert           L          Ð         Ápassive       trip-crit            †           Ð      	   Ácritical                cam-thermal         ß  è        í   ú           S      trips      trip-alert           L          Ð         Ápassive       trip-crit            †           Ð      	   Ácritical                md0-thermal         ß  è        í   ú           S      trips      trip-alert           L          Ð         Ápassive       trip-crit            †           Ð      	   Ácritical                md1-thermal         ß  è        í   ú           S      trips      trip-alert           L          Ð         Ápassive       trip-crit            †           Ð      	   Ácritical                md2-thermal         ß  è        í   ú           S      trips      trip-alert           L          Ð         Ápassive       trip-crit            †           Ð      	   Ácritical                   chosen          >serial0:921600n8          memory@40000000          ºmemory           Æ    @       €            	compatible interrupt-parent #address-cells #size-cells model ovl0 ovl-2l0 ovl-2l2 rdma0 rdma4 serial0 #clock-cells clocks clock-div clock-mult clock-output-names phandle clock-frequency device_type reg enable-method cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains capacity-dmips-mhz #cooling-cells cpu cache-level cache-unified entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts opp-shared opp-hz opp-microvolt dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges #power-domain-cells clock-names mediatek,infracfg assigned-clocks assigned-clock-parents #sound-dai-cells #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #mbox-cells status resets nvmem-cells nvmem-cell-names #thermal-sensor-cells reset-names #pwm-cells interrupts-extended interrupt-names phys wakeup-source mediatek,syscon-wakeup mediatek,apmixedsys mediatek,topckgen power-domains bus-range interrupt-map-mask interrupt-map #phy-cells power-domain-names operating-points-v2 mboxes mediatek,gce-client-reg mediatek,gce-events mediatek,larb-id mediatek,smi iommus mediatek,rdma-fifo-size phy-names mediatek,larbs #iommu-cells mediatek,scp polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path 