Ðþí Ld   8 Aˆ   (            
Ü AP                             %    mediatek,mt8195-demo mediatek,mt8195                                     +            7MediaTek MT8195 demo board     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          ƒ/soc/vpp-merge@1c10f000          Š/soc/vpp-merge@1c110000          ‘/soc/dma-controller@1c104000             œ/soc/dma-controller@1c105000             §/soc/dma-controller@1c106000             ²/soc/dma-controller@1c107000             ½/soc/dma-controller@1c108000             È/soc/dma-controller@1c109000             Ó/soc/dma-controller@1c10a000             Þ/soc/dma-controller@1c10b000             é/soc/serial@11001100          cpus                         +       cpu@0            ñcpu           arm,cortex-a55           ý            psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î   	      cpu@100          ñcpu           arm,cortex-a55           ý           psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î   
      cpu@200          ñcpu           arm,cortex-a55           ý           psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î         cpu@300          ñcpu           arm,cortex-a55           ý           psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î         cpu@400          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu@500          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu@600          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu@700          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu-map    cluster0       core0           Ö   	      core1           Ö   
      core2           Ö         core3           Ö         core4           Ö         core5           Ö         core6           Ö         core7           Ö               idle-states         Úpsci       cpu-retention-l           arm,idle-state          ç           þ           2            _        0  D        Î         cpu-retention-b           arm,idle-state          ç           þ           -            Œ        0  ä        Î         cpu-off-l             arm,idle-state          ç          þ           7            ›        0  H        Î         cpu-off-b             arm,idle-state          ç          þ           2            È        0  è        Î            l2-cache0             cache           A           X           e   @        w           ®            M        Î         l2-cache1             cache           A           X           e   @        w           ®            M        Î         l3-cache              cache           A           X            e   @        w            M        Î            dsu-pmu           arm,dsu-pmu         [                       f   	   
                          kfail          dmic-codec            dmic-codec          r              2      mt8195-sound            �         	  kdisabled          fixed-factor-clock-13m            fixed-factor-clock          ¡            ®           µ           ¿           Êclk13m          Î   (      oscillator-26m            fixed-clock         ¡            #Œº€        Êclk26m          Î         oscillator-32k            fixed-clock         ¡            #  €         Êclk32k        performance-controller@11bc10             mediatek,cpufreq-hw           ý     ¼            ½0               Ý           Î         opp-table-gpu             operating-points-v2          ÷        Î   a   opp-390000000               >í€        	 	‰h      opp-410000000               p€        	 	¡Ò      opp-431000000               °‰À        	 	¡Ò      opp-473000000               1h@        	 	º<      opp-515000000               ²FÀ        	 	º<      opp-556000000               !#ã         	 	Ò¦      opp-598000000               #¤Á€        	 	ë      opp-640000000               &%          	 	ë      opp-670000000               'ïc€        	 
ä      opp-700000000               )¹'         	 
L¸      opp-730000000               +‚ê€        	 
}Œ      opp-760000000               -L®         	 
®`      opp-790000000               /q€        	 
ß4      opp-820000000               0à5         	       opp-850000000               2©ø€        	 @Ü      opp-880000000               4s¼         	 q°         pmu-a55           arm,cortex-a55-pmu                      [                  pmu-a78           arm,cortex-a78-pmu                      [                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  [                                             
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3          )           :                        Q          ý                                    [      	               Î      ppi-partitions     interrupt-partition-0           f   	   
              Î         interrupt-partition-1           f                    Î               syscon@10000000            mediatek,mt8195-topckgen syscon          ý                      ¡           Î         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon           ý                     ¡           o           Î         syscon@10003000           mediatek,mt8195-pericfg syscon           ý     0                ¡           Î   ;      pinctrl@10005000              mediatek,mt8195-pinctrl       €   ý     P            Ñ             Ó             Ô             â             ë             ô              °              B  |iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            †        –           ¢              �         Q        [       ë               )           Î      eth-default-pins            Î   7   pins-txd            ®  M  N  O  P        µ         pins-cc         ®  U  X  W  V        µ         pins-rxd            ®  Q  R  S  T      pins-mdio           ®  Y  Z         Ä      pins-power          ®  [   \          Ñ         eth-sleep-pins          Î   8   pins-txd            ®  M   N   O   P       pins-cc         ®  U   X   W   V       pins-rxd            ®  Q   R   S   T       pins-mdio           ®  Y   Z          Ý         ë         gpio-keys-pins          Î   ¬   pins            ®  j          Ä         i2c6-pins           Î   P   pins            ®             ø         mmc0-default-pins           Î   >   pins-clk            ®  z        µ              f      pins-cmd-dat          $  ®  ~  }  |  {  w  v  u  t  y         Ä        µ           ø   e      pins-rst            ®  x        µ           ø   e         mmc0-uhs-pins           Î   ?   pins-clk            ®  z        µ              f      pins-cmd-dat          $  ®  ~  }  |  {  w  v  u  t  y         Ä        µ           ø   e      pins-ds         ®          µ              f      pins-rst            ®  x        µ           ø   e         mmc1-default-pins           Î   B   pins-clk            ®  o        µ              f      pins-cmd-dat            ®  n  p  q  r  s         Ä        µ           ø   e      pins-insert         ®  �          ø         mmc1-uhs-pins           Î   C   pins-clk            ®  o        µ              f      pins-cmd-dat            ®  n  p  q  r  s         Ä        µ           ø   e         uart0-pins          Î   .   pins            ®  b  c         uart1-pins          Î   /   pins            ®  f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd             ý     `           power-controller          !    mediatek,mt8195-power-controller                         +                       Î   *   power-domain@8           ý                        +                  power-domain@9           ý   	        ®                    (mfg alt         4                        +                  power-domain@10          ý   
                  power-domain@11          ý                     power-domain@12          ý                     power-domain@13          ý                     power-domain@14          ý                           power-domain@15          ý         Ø  ®                        	      @      A      K      à                                                                                                                          (vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           4                        +                  power-domain@16          ý         8  ®      â      $      %      &      '      (      )      D  (vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         4                        +                  power-domain@17          ý           ®      á                    (vppsys1 vppsys1-0 vppsys1-1         4                     power-domain@22          ý            ®                              $  (wepsys-0 wepsys-1 wepsys-2 wepsys-3         4                     power-domain@23          ý           ®               (vdec0-0         4                        +                   power-domain@24          ý           ®               (vdec1-0         4                     power-domain@25          ý           ®                (vdec2-0         4                        power-domain@26          ý           ®   !            (venc0-larb          4                        +                   power-domain@27          ý           ®   "            (venc1-larb          4                        power-domain@18          ý            ®      ã   #       #      #         &  (vdosys1 vdosys1-0 vdosys1-1 vdosys1-2           4                        +                  power-domain@19          ý           4                     power-domain@20          ý           4                     power-domain@21          ý           ®      Q        (hdmi_tx                      power-domain@28          ý           ®   $       $   
        (img-0 img-1         4                        +                  power-domain@29          ý                     power-domain@30          ý           ®         $      %           (ipe ipe-0 ipe-1         4                        power-domain@31          ý         (  ®   &       &      &      &      &           (cam-0 cam-1 cam-2 cam-3 cam-4           4                        +                  power-domain@32          ý                      power-domain@33          ý   !                  power-domain@34          ý   "                           power-domain@0           ý            4                     power-domain@1           ý           4                     power-domain@2           ý                     power-domain@3           ý                     power-domain@4           ý           ®      5      7        (csi_rx_top csi_rx_top1                    power-domain@5           ý           ®   '           (ether                     power-domain@6           ý           ®      X      n        (adsp adsp1                       +            4                 power-domain@7           ý            ®      g      "      n      2        (audio audio1 audio2 audio3          4                              watchdog@10007000             mediatek,mt8195-wdt          F         ý     p                o           Î   -      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon            ý     À                ¡           Î         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer          ý    p                [      	               ®   (      pwrap@10024000            mediatek,mt8195-pwrap syscon             ý    @                |pwrap           [       ó               ®                   	  (spi wrap            ^      $        n      Ë   pmic              mediatek,mt6359          Q        )           …           –      Þ      adc           mediatek,mt6359-auxadc          ª         audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            ¼vs1         Ë 5         ã !‘À        û                   buck_vgpu11         ¼vgpu11          Ë €        ã 7        +  ˆ        û   È        @                         buck_vmodem         ¼vmodem          Ë €        ã Èà        +  *        û   È      buck_vpu            ¼vpu         Ë €        ã 7        +  ˆ        û   È        @                         buck_vcore          ¼vcore           Ë €        ã Ö         +  ˆ        û   È        @                         buck_vs2            ¼vs2         Ë 5         ã j         û                   buck_vpa            ¼vpa         Ë ¡         ã 7±Ð        û  ,      buck_vproc2         ¼vproc2          Ë €        ã 7        +  L        û   È        @                         buck_vproc1         ¼vproc1          Ë €        ã 7        +  L        û   È        @                         buck_vcore_sshub            ¼vcore_sshub         Ë €        ã 7      buck_vgpu11_sshub           ¼vgpu11_sshub            Ë €        ã 7      ldo_vaud18          ¼vaud18          Ë w@        ã w@        û   ð      ldo_vsim1           ¼vsim1           Ë ð         ã /M`      ldo_vibr            ¼vibr            Ë O€        ã 2Z       ldo_vrf12           ¼vrf12           Ë Èà        ã Ö                ldo_vusb            ¼vusb            Ë -ÆÀ        ã -ÆÀ        û  À                 Î   <      ldo_vsram_proc2         ¼vsram_proc2         Ë ¡         ã ½¶        +  L        û   ð               ldo_vio18           ¼vio18           Ë ð         ã ýà        û  À               ldo_vcamio          ¼vcamio          Ë ð         ã ýà      ldo_vcn18           ¼vcn18           Ë w@        ã w@        û   ð      ldo_vfe28           ¼vfe28           Ë *¹€        ã *¹€        û   x      ldo_vcn13           ¼vcn13           Ë »         ã Ö       ldo_vcn33_1_bt          ¼vcn33_1_bt          Ë *¹€        ã 5gà      ldo_vcn33_1_wifi            ¼vcn33_1_wifi            Ë *¹€        ã 5gà      ldo_vaux18          ¼vaux18          Ë w@        ã w@        û   ð               ldo_vsram_others            ¼vsram_others            Ë ¡         ã ½¶        +  ˆ        û   ð               ldo_vefuse          ¼vefuse          Ë ð         ã „€      ldo_vxo22           ¼vxo22           Ë w@        ã !‘À               ldo_vrfck           ¼vrfck           Ë ã`        ã ð       ldo_vrfck_1         ¼vrfck           Ë ëÀ        ã j       ldo_vbif28          ¼vbif28          Ë *¹€        ã *¹€        û   ð      ldo_vio28           ¼vio28           Ë *¹€        ã 2Z                ldo_vemc            ¼vemc            Ë ,@         ã 2Z       ldo_vemc_1          ¼vemc            Ë &%         ã 2Z         Î   @      ldo_vcn33_2_bt          ¼vcn33_2_bt          Ë *¹€        ã 5gà      ldo_vcn33_2_wifi            ¼vcn33_2_wifi            Ë *¹€        ã 5gà      ldo_va12            ¼va12            Ë O€        ã Ö                ldo_va09            ¼va09            Ë 5         ã O€      ldo_vrf18           ¼vrf18           Ë ð         ã žP      ldo_vsram_md          	  ¼vsram_md            Ë ¡         ã ½¶        +  *        û   ð               ldo_vufs            ¼vufs            Ë ð         ã ýà        Î   A      ldo_vm18            ¼vm18            Ë ð         ã ýà               ldo_vbbck           ¼vbbck           Ë Èà        ã O€               ldo_vsram_proc1         ¼vsram_proc1         Ë ¡         ã ½¶        +  L        û   ð               ldo_vsim2           ¼vsim2           Ë ð         ã /M`      ldo_vsram_others_sshub          ¼vsram_others_sshub          Ë ¡         ã ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi              ý    p            �                |pmif spmimst            ®                   E      (  (pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         ^      $        n      Ë      infra-iommu@10315000              mediatek,mt8195-iommu-infra          ý    1P       P       P  [                                                                         X           Î   K      mailbox@10320000              mediatek,mt8195-gce          ý    2        @         [       â               e           ®              Î   „      mailbox@10330000              mediatek,mt8195-gce          ý    3        @         [       ä               e           ®              Î   b      scp@10500000              mediatek,mt8195-scp       0   ý    P             r             p        €         |sram cfg l1tcm          [      Î             	  kdisabled            Î   c      clock-controller@10720000             mediatek,mt8195-scp_adsp             ý    r                 ¡           Î   )      dsp@10803000              mediatek,mt8195-dsp           ý    €0            „               	  |cfg sram          ,  ®      X         n      Š   )          #      K  (adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          q   *           rx tx           Š   +   ,      	  kdisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           e             ý    �`                [      ¾               Î   +      mailbox@10817000              mediatek,mt8195-adsp-mbox           e             ý    �p                [      ¿               Î   ,      mt8195-afe-pcm@10890000           mediatek,mt8195-audio            ý    ‰                 ‘           q   *           [      6               £   -         	  ªaudiosys          ”  ®                     Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d      2   )          ó  (clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  kdisabled            Î         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [       �               ®               	  (baud bus            kokay            ¶default         Ä   .      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [       Ž               ®               	  (baud bus            kokay            ¶default         Ä   /      serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [       �               ®               	  (baud bus          	  kdisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [      Ó               ®               	  (baud bus          	  kdisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [      Ô               ®               	  (baud bus          	  kdisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [      Õ               ®               	  (baud bus          	  kdisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc            ý                      ®              (main            ª         	  kdisabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon            ý     0                ¡           Î   '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý                      [       ¿               ®      ™                    (parent-clk sel-clk spi-clk        	  kdisabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap          ý     °                [       ©               ®              £               Î   0   1      $  Úlvts-calib-data-1 lvts-calib-data-2         ë           Î   «      svs@1100bc00              mediatek,mt8195-svs          ý     ¼                [       Ç               ®              (main            Î   2   0      (  Úsvs-calibration-data t-calibration-data         £              ªsvs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm            ý     à                [       Ë               q   *                      ®      *      0        (main mm       	  kdisabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm            ý     ð                [                                ®      +      N        (main mm       	  kdisabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý                     [       À               ®      ™            3        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý                     [       Á               ®      ™            4        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý    0                [       Â               ®      ™            5        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý    €                [       Ã               ®      ™            <        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý    �                [       Ä               ®      ™            =        (parent-clk sel-clk spi-clk        	  kdisabled          spi@1101d000              mediatek,mt8195-spi-slave            ý    Ð                [       Å               ®      R        (spi         ^              n      ˜      	  kdisabled          spi@1101e000              mediatek,mt8195-spi-slave            ý    à                [       Æ               ®      S        (spi         ^              n      ˜      	  kdisabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a            ý           @         [      Ì               macirq        .  (axi apb mac_main ptp_ref rmii_internal mac_cg         0  ®   '       '         R      S      T   '           ^      R      S      T        n      Â      Ã      Ä        q   *                      -   3        =   4        P   5        c           n           y            kokay          	  †rgmii-id            �   6        š      ]            ª      ' 8€        ¶default sleep           Ä   7        ¿   8         É   mdio              snps,dwmac-mdio                      +       ethernet-phy@1           ý           Î   6         stmmac-axi-config           Ú           ê           ú                                 Î   3      rx-queues-config                                Î   4   queue0           +        >          queue1           +        >          queue2           +        >          queue3           +        >             tx-queues-config            V            l        Î   5   queue0          ~            +        Š          queue1          ~            +        Š         queue2          ~            +        Š         queue3          ~            +        Š               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3            ý            -ÿ     >              	  |mac ippc                                 ?                      +           [       €               ®      /      í      B        (sys_ck ref_ck mcu_ck            ˜   9      :            �        «   ;      g        kokay            Â   <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci           ý                       |mac         [       �               ^      ,      -        n      –      –      $  ®      /      í               B      $  (sys_ck ref_ck mcu_ck dma_ck xhci_ck         kokay            Ð   =         mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           ý    #             õ                 [       ƒ               ®                          (source hclk source_cg           kokay            ¶default state_uhs           Ä   >        ¿   ?        Ü           æëÂ          ô                           $         5         =        C L        R   @        ^   A         k      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           ý    $             Ç                 [       ‡               ®                  $        (source hclk source_cg           ^              n      ¿        kokay            ¶default state_uhs           Ä   B        ¿   C        y      �           Ü           æëÂ          ‚         “                  R   D        ^   E      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           ý    %             æ                 [       ˆ               ®                   I        (source hclk source_cg           ^               n      ¿      	  kdisabled          ufshci@11270000           mediatek,mt8195-ufshci           ý    '        #         [       ‰               ˜   F      @  ®      ?      @      A      6      7      8      Z      ]      X  (ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  ®                                                                         ¼      	  kdisabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu             ý    '€                [       ª               ®              £              Î   0   1      $  Úlvts-calib-data-1 lvts-calib-data-2         ë           Î   ¢      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci            ý    )             )>              	  |mac ippc            [                     ˜   G      H           ^      .      /        n      –      –      $  ®   '         ï            '         $  (sys_ck ref_ck mcu_ck dma_ck xhci_ck         «   ;      h         �        kokay            Â   <      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3            ý    *       -ÿ    *>              	  |mac ippc                        *        ?                      +           [                     ^      0        n      –        ®   '         ñ   '           (sys_ck ref_ck mcu_ck            ˜   I            �        «   ;      i        kokay            Â   <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci           ý                       |mac         [                     ^      1        n      –        ®   '           (sys_ck          kokay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3            ý    +       -ÿ    +>              	  |mac ippc                        +        ?                      +           [                     ^      2        n      –        ®   '         ó   '   	        (sys_ck ref_ck mcu_ck            ˜   J            �        «   ;      j        kokay            Â   <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci           ý                       |mac         [                     ^      3        n      –        ®   '   	        (sys_ck          kokay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            ñpci                      +            ý    /        @       	  |pcie-mac            [                     Õ       ÿ      8  �                           ‚                       à          ß       K              é          0  ®      V      #      &      +      K   '         /  (pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ^      G        n              ˜   L      	  øpcie-phy            q   *            )           	                     `  	                  M                      M                     M                     M         	  kdisabled       interrupt-controller             Q                     )           Î   M         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            ñpci                      +            ý    /€       @       	  |pcie-mac            [                     Õ       ÿ      8  �       $       $           ‚       $       $       à          ß       K              é          (  ®      W         X         Q   '         /  (pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ^      H        n              ˜   H         	  øpcie-phy            q   *           )           	                     `  	                  N                      N                     N                     N         	  kdisabled       interrupt-controller             Q                     )           Î   N         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor          ý    2À                [      9               ®      o   '      '           (spi sf axi                       +          	  kdisabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse             ý    Á                              +      usb3-tx-imp@184,1            ý  „           	#               Î   X      usb3-rx-imp@184,2            ý  „           	#              Î   W      usb3-intr@185            ý  …           	#              Î   V      usb3-tx-imp@186,1            ý  †           	#               Î   U      usb3-rx-imp@186,2            ý  †           	#              Î   T      usb3-intr@187            ý  ‡           	#              Î   S      usb2-intr-p0@188,1           ý  ˆ           	#             usb2-intr-p1@188,2           ý  ˆ           	#            usb2-intr-p2@189,1           ý  ‰           	#            usb2-intr-p3@189,2           ý  ‰           	#            pciephy-rx-ln1@190,1             ý  �           	#               Î   _      pciephy-tx-ln1-nmos@190,2            ý  �           	#              Î   ^      pciephy-tx-ln1-pmos@191,1            ý  ‘           	#               Î   ]      pciephy-rx-ln0@191,2             ý  ‘           	#              Î   \      pciephy-tx-ln0-nmos@192,1            ý  ’           	#               Î   [      pciephy-tx-ln0-pmos@192,2            ý  ’           	#              Î   Z      pciephy-glb-intr@193             ý  “           	#               Î   Y      dp-data@1ac          ý  ¬           Î   ¡      lvts1-calib@1bc          ý  ¼           Î   0      lvts2-calib@1d0          ý  Ð   8        Î   1      svs-calib@580            ý  €   d        Î   2      socinfo-data1@7a0            ý               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   Ä             kokay       usb-phy@0            ý               ®      ò        (ref         	(           Î   I         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   Å             kokay       usb-phy@0            ý               ®      ô        (ref         	(           Î   J         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx          ý    È                 ®           Êmipi_tx0_pll            ¡            	(          	  kdisabled            Î   ‘      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx          ý    É                 ®           Êmipi_tx1_pll            ¡            	(          	  kdisabled            Î   ’      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    Ð             "€       €        [       š               µ           ®   O          ;      	  (main dma                         +          	  kdisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    Ð            "        €        [       ›               µ           ®   O         ;      	  (main dma                         +            kokay            # €        Ä   P        ¶default    pmic@34           mediatek,mt6360          ý   4         Q        )           –      e           IRQB       charger           mediatek,mt6360-chg         	3 Ý@    usb-otg-vbus-regulator          ¼usb-otg-vbus            Ë C…(        ã Xáè        Î   =         regulator             mediatek,mt6360-regulator           	L   Q   buck1           ¼mt6360,buck1            Ë “à        ã Ö         @                         buck2           ¼mt6360,buck2            Ë “à        ã Ö         @                           Î   Q      ldo1            ¼mt6360,ldo1         Ë O€        ã 6î€        @             ldo2            ¼mt6360,ldo2         Ë O€        ã 6î€        @             ldo3            ¼mt6360,ldo3         Ë O€        ã 6î€        @               Î   E      ldo5            ¼mt6360,ldo5         Ë )2à        ã 6î€        @               Î   D      ldo6            ¼mt6360,ldo6         Ë ¡         ã           @             ldo7            ¼mt6360,ldo7         Ë ¡         ã           @                               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    Ð             "€       €        [       œ               µ           ®   O         ;      	  (main dma                         +          	  kdisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s           ý    Ð0                ¡           Î   O      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à             " €       €        [       �               µ           ®   R          ;      	  (main dma                         +          	  kdisabled          i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à            "        €        [       “               µ           ®   R         ;      	  (main dma                         +          	  kdisabled          i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à             "€       €        [       –               µ           ®   R         ;      	  (main dma                         +          	  kdisabled          i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à0            "€       €        [       ˜               µ           ®   R         ;      	  (main dma                         +          	  kdisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à@            "        €        [       ™               µ           ®   R         ;      	  (main dma                         +          	  kdisabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w           ý    àP                ¡           Î   R      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   ã             q   *           kokay       usb-phy@0            ý               ®      ð           (ref da_ref          	(           Î   G      usb-phy@700          ý              ®            ð        (ref da_ref          Î   S   T   U        Úintr rx_imp tx_imp          	(           Î   H         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   ä             kokay       usb-phy@0            ý               ®      î           (ref da_ref          	(           Î   9      usb-phy@700          ý              ®            î        (ref da_ref          Î   V   W   X        Úintr rx_imp tx_imp          	(           Î   :         phy@11e80000              mediatek,mt8195-pcie-phy             ý    è                 |sif         Î   Y   Z   [   \   ]   ^   _      G  Úglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          q   *           	(          	  kdisabled            Î   L      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy            ý    ú        À         ®            
  (unipro mp           	(          	  kdisabled            Î   F      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm            ý             @         ®   `          0  [      �             Œ             ‹               job mmu gpu         	\   a      (  q   *   
   *      *      *      *           	pcore0 core1 core2 core3 core4         	  kdisabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg           ý    ûð                ¡           Î   `      syscon@14000000           mediatek,mt8195-vppsys0 syscon           ý                      ¡           	ƒ   b                   Î         dma-controller@14001000           mediatek,mt8195-mdp3-rdma            ý                     	ƒ   b                  	›              	¯   c        q   *           	¼   d   €        ®            <  Š   b         b         b         b         b              	Ã         display@14002000              mediatek,mt8195-mdp3-fg          ý                      	ƒ   b                   ®             display@14003000              mediatek,mt8195-mdp3-stitch          ý     0                	ƒ   b      0            ®            display@14004000              mediatek,mt8195-mdp3-hdr             ý     @                	ƒ   b      @            ®      "      display@14005000              mediatek,mt8195-mdp3-aal             ý     P                [      F               	ƒ   b      P            ®      
        q   *         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý     `                	ƒ   b      `            	›    %        ®            display@14007000              mediatek,mt8195-mdp3-tdshp           ý     p                	ƒ   b      p            ®      #      display@14008000              mediatek,mt8195-mdp3-color           ý     €                [      I               	ƒ   b      €            ®      $        q   *         display@14009000              mediatek,mt8195-mdp3-ovl             ý     �                [      J               	ƒ   b      �            ®      %        q   *           	¼   d   ‚      display@1400a000              mediatek,mt8195-mdp3-padding             ý                      	ƒ   b                   ®              q   *         display@1400b000              mediatek,mt8195-mdp3-tcc             ý     °                	ƒ   b      °            ®            dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý     À                	ƒ   b      À            	›    +        ®              	¼   d   ƒ        q   *           	Ã         mutex@1400f000            mediatek,mt8195-vpp-mutex            ý     ð                [      P               	ƒ   b      ð            ®              q   *         smi@14010000              mediatek,mt8195-smi-sub-common           ý                     ®                          (apb smi gals0           	Î   e        q   *           Î   f      smi@14011000              mediatek,mt8195-smi-sub-common           ý                    ®                          (apb smi gals0           	Î   e        q   *           Î   ƒ      smi@14012000              mediatek,mt8195-smi-common-vpp           ý                      ®                                (apb smi gals0 gals1         q   *           Î   e      larb@14013000             mediatek,mt8195-smi-larb             ý    0                	Û           	Î   f        ®                    (apb smi         q   *           Î   i      iommu@14018000            mediatek,mt8195-iommu-vpp            ý    €              8  	ì   g   h   i   j   k   l   m   n   o   p   q   r   s   t        [      R               ®              (bclk            X           q   *           Î   d      clock-controller@14e00000             mediatek,mt8195-wpesys           ý    à                 ¡           Î         clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0          ý    à                 ¡         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1          ý    à0                ¡         larb@14e04000             mediatek,mt8195-smi-larb             ý    à@                	Û           	Î   u        ®                    (apb smi         q   *           Î   –      larb@14e05000             mediatek,mt8195-smi-larb             ý    àP                	Û           	Î   e        ®                          (apb smi gals            q   *           Î   k      syscon@14f00000           mediatek,mt8195-vppsys1 syscon           ý    ð                 ¡           	ƒ   b   	               Î         mutex@14f01000            mediatek,mt8195-vpp-mutex            ý    ð                [      {               	ƒ   b   	              ®      '        q   *         larb@14f02000             mediatek,mt8195-smi-larb             ý    ð                 	Û           	Î   u        ®                          (apb smi gals            q   *           Î   •      larb@14f03000             mediatek,mt8195-smi-larb             ý    ð0                	Û           	Î   f        ®                          (apb smi gals            q   *           Î   j      display@14f06000              mediatek,mt8195-mdp3-split           ý    ð`                	ƒ   b   	  `            ®            +      ,        q   *         display@14f07000              mediatek,mt8195-mdp3-tcc             ý    ðp                	ƒ   b   	  p            ®            dma-controller@14f08000           mediatek,mt8195-mdp3-rdma            ý    ð€                	ƒ   b   	  €            	›  „  ¨        ®              	¼   v            q   *           	Ã         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma            ý    ð�                	ƒ   b   	  �            	›  …  ©        ®      
        	¼   v   ¤        q   *           	Ã         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma            ý    ð                 	ƒ   b   	               	›  †  ª        ®              	¼   d   À        q   *           	Ã         display@14f0b000              mediatek,mt8195-mdp3-fg          ý    ð°                	ƒ   b   	  °            ®      	      display@14f0c000              mediatek,mt8195-mdp3-fg          ý    ðÀ                	ƒ   b   	  À            ®            display@14f0d000              mediatek,mt8195-mdp3-fg          ý    ðÐ                	ƒ   b   	  Ð            ®            display@14f0e000              mediatek,mt8195-mdp3-hdr             ý    ðà                	ƒ   b   	  à            ®            display@14f0f000              mediatek,mt8195-mdp3-hdr             ý    ðð                	ƒ   b   	  ð            ®            display@14f10000              mediatek,mt8195-mdp3-hdr             ý    ñ                 	ƒ   b   
               ®             display@14f11000              mediatek,mt8195-mdp3-aal             ý    ñ                [      i               	ƒ   b   
              ®              q   *         display@14f12000              mediatek,mt8195-mdp3-aal             ý    ñ                 [      j               	ƒ   b   
               ®              q   *         display@14f13000              mediatek,mt8195-mdp3-aal             ý    ñ0                [      k               	ƒ   b   
  0            ®      !        q   *         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý    ñ@                	ƒ   b   
  @            	›  �  ¯        ®            display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý    ñP                	ƒ   b   
  P            	›  ‘  °        ®      $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý    ñ`                	ƒ   b   
  `            	›  ’  ±        ®      %      display@14f17000              mediatek,mt8195-mdp3-tdshp           ý    ñp                	ƒ   b   
  p            ®            display@14f18000              mediatek,mt8195-mdp3-tdshp           ý    ñ€                	ƒ   b   
  €            ®      (      display@14f19000              mediatek,mt8195-mdp3-tdshp           ý    ñ�                	ƒ   b   
  �            ®      )      display@14f1a000              mediatek,mt8195-mdp3-merge           ý    ñ                 	ƒ   b   
               ®              q   *         display@14f1b000              mediatek,mt8195-mdp3-merge           ý    ñ°                	ƒ   b   
  °            ®              q   *         display@14f1c000              mediatek,mt8195-mdp3-color           ý    ñÀ                [      t               	ƒ   b   
  À            ®              q   *         display@14f1d000              mediatek,mt8195-mdp3-color           ý    ñÐ                	ƒ   b   
  Ð            [      u               ®              q   *         display@14f1e000              mediatek,mt8195-mdp3-color           ý    ñà                [      v               	ƒ   b   
  à            ®              q   *         display@14f1f000              mediatek,mt8195-mdp3-ovl             ý    ñð                [      w               	ƒ   b   
  ð            ®               q   *           	¼   v   ¢      display@14f20000              mediatek,mt8195-mdp3-padding             ý    ò                 	ƒ   b                  ®              q   *         display@14f21000              mediatek,mt8195-mdp3-padding             ý    ò                	ƒ   b                 ®              q   *         display@14f22000              mediatek,mt8195-mdp3-padding             ý    ò                 	ƒ   b                  ®              q   *         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý    ò0                	ƒ   b     0            	›  Ÿ  «        ®              	¼   v   £        q   *           	Ã         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý    ò@                	ƒ   b     @            	›     ¬        ®              	¼   v   ¦        q   *           	Ã         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý    òP                	ƒ   b     P            	›  ¡  ­        ®              	¼   d   Â        q   *           	Ã         clock-controller@15000000             mediatek,mt8195-imgsys           ý                      ¡           Î   $      larb@15001000             mediatek,mt8195-smi-larb             ý                     	Û   	        	Î   w        ®   $       $       $   
        (apb smi gals            q   *           Î   —      smi@15002000              mediatek,mt8195-smi-sub-common           ý                      ®   $      $                 (apb smi gals0           	Î   e        q   *           Î   z      smi@15003000              mediatek,mt8195-smi-sub-common           ý     0                ®   $       $       $   
        (apb smi gals0           	Î   u        q   *           Î   w      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top          ý                     ¡           Î   x      larb@15120000             mediatek,mt8195-smi-larb             ý                     	Û   
        	Î   w        ®   $      x            (apb smi         q   *           Î   ˜      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr           ý                     ¡         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe          ý    "                 ¡           Î   y      larb@15230000             mediatek,mt8195-smi-larb             ý    #                 	Û           	Î   w        ®   $      y            (apb smi         q   *           Î   ™      clock-controller@15330000             mediatek,mt8195-ipesys           ý    3                 ¡           Î   %      larb@15340000             mediatek,mt8195-smi-larb             ý    4                 	Û           	Î   z        ®   %      %           (apb smi         q   *           Î   l      clock-controller@16000000             mediatek,mt8195-camsys           ý                      ¡           Î   &      larb@16001000             mediatek,mt8195-smi-larb             ý                     	Û           	Î   {        ®   &       &       &           (apb smi gals            q   *           Î   š      larb@16002000             mediatek,mt8195-smi-larb             ý                      	Û           	Î   |        ®   &      &           (apb smi         q   *           Î   m      smi@16004000              mediatek,mt8195-smi-sub-common           ý     @                ®   &       &       &           (apb smi gals0           	Î   u        q   *           Î   {      smi@16005000              mediatek,mt8195-smi-sub-common           ý     P                ®   &      &                 (apb smi gals0           	Î   e        q   *           Î   |      larb@16012000             mediatek,mt8195-smi-larb             ý                     	Û           	Î   |        ®   }       }            (apb smi         q   *            Î   n      larb@16013000             mediatek,mt8195-smi-larb             ý    0                	Û           	Î   {        ®   ~       ~            (apb smi         q   *            Î   ›      larb@16014000             mediatek,mt8195-smi-larb             ý    @                	Û           	Î   |        ®                      (apb smi         q   *   !        Î   t      larb@16015000             mediatek,mt8195-smi-larb             ý    P                	Û           	Î   {        ®   €       €            (apb smi         q   *   !        Î          clock-controller@1604f000             mediatek,mt8195-camsys_rawa          ý    ð                ¡           Î   }      clock-controller@1606f000             mediatek,mt8195-camsys_yuva          ý    ð                ¡           Î   ~      clock-controller@1608f000             mediatek,mt8195-camsys_rawb          ý    ð                ¡           Î         clock-controller@160af000             mediatek,mt8195-camsys_yuvb          ý    
ð                ¡           Î   €      clock-controller@16140000             mediatek,mt8195-camsys_mraw          ý                     ¡           Î   �      larb@16141000             mediatek,mt8195-smi-larb             ý                    	Û           	Î   {        ®   &       �       &           (apb smi gals            q   *   "        Î   Ÿ      larb@16142000             mediatek,mt8195-smi-larb             ý                     	Û           	Î   |        ®   �       �            (apb smi         q   *   "        Î   s      clock-controller@17200000             mediatek,mt8195-ccusys           ý                      ¡           Î   ‚      larb@17201000             mediatek,mt8195-smi-larb             ý                     	Û           	Î   |        ®   ‚       ‚            (apb smi         q   *           Î   o      video-codec@18000000              mediatek,mt8195-vcodec-dec          	¯   c        	¼   v                        +             ý                   @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc          ý                       	¼   d  à   d  á         ®      A                  �        (sel vdec lat top            ^      A        n      �        q   *         video-codec@10000             mediatek,mtk-vcodec-lat          ý                      [      Ä             0  	¼   v      v     v     v     v     v           ®      A                  �        (sel vdec lat top            ^      A        n      �        q   *         video-codec@25000             mediatek,mtk-vcodec-core             ý     P                [      Ã             P  	¼   v      v  ¡   v  ¢   v  £   v  ¤   v  ¥   v  ¦   v  §   v  ¨   v  ©         ®      A                  �        (sel vdec lat top            ^      A        n      �        q   *            larb@1800d000             mediatek,mt8195-smi-larb             ý     Ð                	Û           	Î   u        ®                      (apb smi         q   *           Î   ž      larb@1800e000             mediatek,mt8195-smi-larb             ý     à                	Û           	Î   ƒ        ®                     (apb smi         q   *           Î   r      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc          ý     ð                ¡           Î         larb@1802e000             mediatek,mt8195-smi-larb             ý    à                	Û           	Î   u        ®                      (apb smi         q   *           Î   �      clock-controller@1802f000             mediatek,mt8195-vdecsys          ý    ð                ¡           Î         larb@1803e000             mediatek,mt8195-smi-larb             ý    à                	Û           	Î   ƒ        ®                      (apb smi         q   *           Î   q      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1            ý    ð                ¡           Î          clock-controller@190f3000             mediatek,mt8195-apusys_pll           ý    0                ¡         clock-controller@1a000000             mediatek,mt8195-vencsys          ý                      ¡           Î   !      larb@1a010000             mediatek,mt8195-smi-larb             ý                     	Û           	Î   u        ®   !      !           (apb smi         q   *           Î   œ      video-codec@1a020000              mediatek,mt8195-vcodec-enc           ý                   H  	¼   v  `   v  a   v  b   v  c   v  d   v  v   v  w   v  x   v  y        [      U               	¯   c        ®   !         	  (venc_sel            ^      @        n      �        q   *                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec          q   *         0  	¼   v  m   v  n   v  r   v  s   v  t   v  u                     +         0                                              jpgdec@0,0            mediatek,mt8195-jpgdec-hw            ý                     0  	¼   v  m   v  n   v  r   v  s   v  t   v  u        [      W               ®   !           (jpgdec          q   *         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw            ý                    0  	¼   v  m   v  n   v  r   v  s   v  t   v  u        [      X               ®   !           (jpgdec          q   *         jpgdec@1,0            mediatek,mt8195-jpgdec-hw            ý                    0  	¼   d  �   d  Ž   d  ’   d  “   d  ”   d  •        [      \               ®   "           (jpgdec          q   *            clock-controller@1b000000             mediatek,mt8195-vencsys_core1            ý                      ¡           Î   "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon             ý                     Š   „               ¡           	ƒ   „                  Î         jpeg-encoder@1a030000             mediatek,mt8195-jpgenc          q   *            	¼   d  ‡   d  ˆ   d  ‰   d  Œ                     +         0                                              jpgenc@0,0            mediatek,mt8195-jpgenc-hw            ý                        	¼   v  g   v  h   v  i   v  l        [      V               ®   !           (jpgenc          q   *         jpgenc@1,0            mediatek,mt8195-jpgenc-hw            ý                       	¼   d  ‡   d  ˆ   d  ‰   d  Œ        [      [               ®   "           (jpgenc          q   *            larb@1b010000             mediatek,mt8195-smi-larb             ý                     	Û           	Î   e        ®   "      "                  (apb smi gals            q   *           Î   p      ovl@1c000000              mediatek,mt8195-disp-ovl             ý                      [      |               q   *           ®               	¼   v           	ƒ   „             ports                        +       port@0           ý       endpoint             port@1           ý      endpoint            	û   …        Î   †               rdma@1c002000             mediatek,mt8195-disp-rdma            ý                      [      ~               q   *           ®              	¼   v            	ƒ   „             ports                        +       port@0           ý       endpoint            	û   †        Î   …         port@1           ý      endpoint            	û   ‡        Î   ˆ               color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color            ý     0                [                     q   *           ®              	ƒ   „     0       ports                        +       port@0           ý       endpoint            	û   ˆ        Î   ‡         port@1           ý      endpoint            	û   ‰        Î   Š               ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr            ý     @                [      €               q   *           ®              	ƒ   „     @       ports                        +       port@0           ý       endpoint            	û   Š        Î   ‰         port@1           ý      endpoint            	û   ‹        Î   Œ               aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal            ý     P                [      �               q   *           ®              	ƒ   „     P       ports                        +       port@0           ý       endpoint            	û   Œ        Î   ‹         port@1           ý      endpoint            	û   �        Î   Ž               gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma            ý     `                [      ‚               q   *           ®              	ƒ   „     `       ports                        +       port@0           ý       endpoint            	û   Ž        Î   �         port@1           ý      endpoint            	û   �        Î   �               dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither          ý     p                [      ƒ               q   *           ®      	        	ƒ   „     p       ports                        +       port@0           ý       endpoint            	û   �        Î   �         port@1           ý      endpoint                   dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi          ý     €                [      „               q   *           ®            *   ‘        (engine digital hs           ˜   ‘        ødphy          	  kdisabled          dsc@1c009000              mediatek,mt8195-disp-dsc             ý     �                [      …               q   *           ®              	ƒ   „     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi          ý                     [      Ž               q   *           ®            +   ’        (engine digital hs           ˜   ’        ødphy          	  kdisabled          merge@1c014000            mediatek,mt8195-disp-merge           ý    @                [      �               q   *           ®              	ƒ   „     @          dp-intf@1c015000              mediatek,mt8195-dp-intf          ý    P                [      ‘               q   *           ®      ,                    (pixel engine pll          	  kdisabled          mutex@1c016000            mediatek,mt8195-disp-mutex           ý    `                [      ’               q   *           ®              	ƒ   „     `            	›  U      larb@1c018000             mediatek,mt8195-smi-larb             ý    €                	Û            	Î   u        ®      (      (              (apb smi gals            q   *           Î   “      larb@1c019000             mediatek,mt8195-smi-larb             ý    �                	Û           	Î   e        ®      (                     (apb smi gals            q   *           Î   g      syscon@1c100000           mediatek,mt8195-vdosys1 syscon           ý                     Š   „              	ƒ   „                  ¡           o           Î   #      smi@1c01b000              mediatek,mt8195-smi-common-vdo           ý    °                 ®      %      &      )      $        (apb smi gals0 gals1         q   *           Î   u      iommu@1c01f000            mediatek,mt8195-iommu-vdo            ý    ð              8  	ì   “   ”   •   –   —   ˜   ™   š   ›   œ   �   ž   Ÿ            [      �               X           ®      '        (bclk            q   *           Î   v      mutex@1c101000            mediatek,mt8195-disp-mutex           ý                    [      î               q   *           ®   #           	ƒ   „                 	›  À      larb@1c102000             mediatek,mt8195-smi-larb             ý                     	Û           	Î   u        ®   #       #       #           (apb smi gals            q   *           Î   ”      larb@1c103000             mediatek,mt8195-smi-larb             ý    0                	Û           	Î   e        ®   #      #                  (apb smi gals            q   *           Î   h      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma            ý    @                [      ï               ®   #           q   *           	¼   v   @        	ƒ   „     @            	Ã         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma            ý    P                [      ð               ®   #           q   *           	¼   d   `        	ƒ   „     P            	Ã         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma            ý    `                [      ñ               ®   #           q   *           	¼   v   A        	ƒ   „     `            	Ã         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma            ý    p                [      ò               ®   #           q   *           	¼   d   a        	ƒ   „     p            	Ã         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma            ý    €                [      ó               ®   #           q   *           	¼   v   B        	ƒ   „     €            	Ã         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma            ý    �                [      ô               ®   #           q   *           	¼   d   b        	ƒ   „     �            	Ã         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma            ý                     [      õ               ®   #           q   *           	¼   v   C        	ƒ   „                  	Ã         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma            ý    °                [      ö               ®   #           q   *           	¼   d   c        	ƒ   „     °            	Ã         vpp-merge@1c10c000            mediatek,mt8195-disp-merge           ý    À                [      ÷               ®   #   	   #           (merge merge_async           q   *           	ƒ   „     À             
        £   #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge           ý    Ð                [      ø               ®   #   
   #           (merge merge_async           q   *           	ƒ   „     Ð             
        £   #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge           ý    à                [      ù               ®   #      #           (merge merge_async           q   *           	ƒ   „     à             
        £   #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge           ý    ð                [      ú               ®   #      #           (merge merge_async           q   *           	ƒ   „     ð             
        £   #         vpp-merge@1c110000            mediatek,mt8195-disp-merge           ý                     [      û               ®   #      #           (merge merge_async           q   *           	ƒ   „                   
        £   #         dp-intf@1c113000              mediatek,mt8195-dp-intf          ý    0                [                     q   *           ®   #   /   #                 (pixel engine pll          	  kdisabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p   ý    @            P            p            �                         °            À              4  |mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  	ƒ   „     @       „     P       „     p       „     �       „             „     °       „     À          h  ®   #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *            ƒ  (mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          q   *           	¼   d   d   d   e        [                   (  £   #   3   #   4   #   5   #   6   #   7      E  ªvdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx           ý    P        €         Î   ¡        Údp_calibration_data         q   *           [      ¤               
6  ¤      	  kdisabled          dp-tx@1c600000            mediatek,mt8195-dp-tx            ý    `        €         Î   ¡        Údp_calibration_data         q   *           [      Ê               
6  ¤      	  kdisabled             thermal-zones      cpu0-thermal            
G  è        
U   ú        
k   ¢      trips      trip-alert          
{ L        
‡  Ð         øpassive         Î   £      trip-crit           
{ †         
‡  Ð      	   øcritical             cooling-maps       map0            
’   £      0  
—   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            
G  è        
U   ú        
k   ¢      trips      trip-alert          
{ L        
‡  Ð         øpassive         Î   ¤      trip-crit           
{ †         
‡  Ð      	   øcritical             cooling-maps       map0            
’   ¤      0  
—   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            
G  è        
U   ú        
k   ¢      trips      trip-alert          
{ L        
‡  Ð         øpassive         Î   ¥      trip-crit           
{ †         
‡  Ð      	   øcritical             cooling-maps       map0            
’   ¥      0  
—   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            
G  è        
U   ú        
k   ¢      trips      trip-alert          
{ L        
‡  Ð         øpassive         Î   ¦      trip-crit           
{ †         
‡  Ð      	   øcritical             cooling-maps       map0            
’   ¦      0  
—   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            
G  è        
U   ú        
k   ¢       trips      trip-alert          
{ L        
‡  Ð         øpassive         Î   §      trip-crit           
{ †         
‡  Ð      	   øcritical             cooling-maps       map0            
’   §      0  
—   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            
G  è        
U   ú        
k   ¢      trips      trip-alert          
{ L        
‡  Ð         øpassive         Î   ¨      trip-crit           
{ †         
‡  Ð      	   øcritical             cooling-maps       map0            
’   ¨      0  
—   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            
G  è        
U   ú        
k   ¢      trips      trip-alert          
{ L        
‡  Ð         øpassive         Î   ©      trip-crit           
{ †         
‡  Ð      	   øcritical             cooling-maps       map0            
’   ©      0  
—   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            
G  è        
U   ú        
k   ¢      trips      trip-alert          
{ L        
‡  Ð         øpassive         Î   ª      trip-crit           
{ †         
‡  Ð      	   øcritical             cooling-maps       map0            
’   ª      0  
—   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            
G  è        
U   ú        
k   «      trips      trip-alert          
{ L        
‡  Ð         øpassive       trip-crit           
{ †         
‡  Ð      	   øcritical                vpu1-thermal            
G  è        
U   ú        
k   «   	   trips      trip-alert          
{ L        
‡  Ð         øpassive       trip-crit           
{ †         
‡  Ð      	   øcritical                gpu-thermal         
G  è        
U   ú        
k   «   
   trips      trip-alert          
{ L        
‡  Ð         øpassive       trip-crit           
{ †         
‡  Ð      	   øcritical                gpu1-thermal            
G  è        
U   ú        
k   «      trips      trip-alert          
{ L        
‡  Ð         øpassive       trip-crit           
{ †         
‡  Ð      	   øcritical                vdec-thermal            
G  è        
U   ú        
k   «      trips      trip-alert          
{ L        
‡  Ð         øpassive       trip-crit           
{ †         
‡  Ð      	   øcritical                img-thermal         
G  è        
U   ú        
k   «      trips      trip-alert          
{ L        
‡  Ð         øpassive       trip-crit           
{ †         
‡  Ð      	   øcritical                infra-thermal           
G  è        
U   ú        
k   «      trips      trip-alert          
{ L        
‡  Ð         øpassive       trip-crit           
{ †         
‡  Ð      	   øcritical                cam0-thermal            
G  è        
U   ú        
k   «      trips      trip-alert          
{ L        
‡  Ð         øpassive       trip-crit           
{ †         
‡  Ð      	   øcritical                cam1-thermal            
G  è        
U   ú        
k   «      trips      trip-alert          
{ L        
‡  Ð         øpassive       trip-crit           
{ †         
‡  Ð      	   øcritical                   chosen          
¦serial0:921600n8          firmware       optee             linaro,optee-tz         smc          gpio-keys         
    gpio-keys           ¶default         Ä   ¬   key-0           |      j         
  
²volume_up           
¸   s         �        
Ã            memory@40000000          ñmemory           ý    @                reserved-memory                      +               optee@43200000           
Õ         ý    C        À        memory@50000000           shared-dma-pool          ý    P       �           
Õ      memory@53000000           shared-dma-pool          ý    S       @        memory@54600000          
Õ         ý    T`                memory@60000000           shared-dma-pool          ý    `                  
Õ      memory@62000000           shared-dma-pool          ý    b       @              	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux drive-strength input-enable output-high input-disable bias-disable bias-pull-up bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us pinctrl-1 mediatek,mac-wol snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup vusb33-supply vbus-supply bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 freq-table-hz mediatek,ufs-disable-mcq bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply operating-points-v2 power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path label linux,code debounce-interval no-map 