Ðþí (î   8 ¬   (            B t                             4    grinn,genio-510-sbc mediatek,mt8370 mediatek,mt8188                                  +         	   7embedded             DGrinn GenioSBC-510     aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/dsc@1c009000            a/soc/ethdr@1c114000          h/soc/mailbox@10320000            m/soc/mailbox@10330000            r/soc/merge0@1c014000             y/soc/merge@1c10c000          €/soc/merge@1c10d000          ‡/soc/merge@1c10e000          Ž/soc/merge@1c10f000          •/soc/merge@1c110000          œ/soc/mutex@1c016000          £/soc/mutex@1c101000          ª/soc/padding@1c11d000            ³/soc/padding@1c11e000            ¼/soc/padding@1c11f000            Å/soc/padding@1c120000            Î/soc/padding@1c121000            ×/soc/padding@1c122000            à/soc/padding@1c123000            é/soc/padding@1c124000            ò/soc/rdma@1c104000           ý/soc/rdma@1c105000          /soc/rdma@1c106000          /soc/rdma@1c107000          /soc/rdma@1c108000          )/soc/rdma@1c109000          4/soc/rdma@1c10a000          ?/soc/rdma@1c10b000          J/soc/i2c@11e00000           O/soc/mmc@11230000           T/soc/ethernet@11021000          ^/soc/i2c@11280000           c/soc/i2c@11281000           h/soc/i2c@11282000           m/soc/i2c@11ec0000           r/soc/i2c@11ec1000           w/soc/serial@11001100          cpus                         +       cpu@0           cpu           arm,cortex-a55          ‹            �psci            �w5”         ­          À              Ð  €         Ý   @        ï   €        ü  €         	   @           €        (           9               M           \   	      cpu@100         cpu           arm,cortex-a55          ‹           �psci            �w5”         ­          À              Ð  €         Ý   @        ï   €        ü  €         	   @           €        (           9               M           \   
      cpu@200         cpu           arm,cortex-a55          ‹           �psci            �w5”         ­          À              Ð  €         Ý   @        ï   €        ü  €         	   @           €        (           9               M           \         cpu@300         cpu           arm,cortex-a55          ‹           �psci            �w5”         ­          À              Ð  €         Ý   @        ï   €        ü  €         	   @           €        (           9               M           \         cpu@600         cpu           arm,cortex-a78          ‹           �psci            �ƒ!V         ­           À              Ð           Ý   @        ï           ü           	   @                   (           9              M           \         cpu@700         cpu           arm,cortex-a78          ‹           �psci            �ƒ!V         ­           À              Ð           Ý   @        ï           ü           	   @                   (           9              M           \         cpu-map    cluster0       core0           d   	      core1           d   
      core2           d         core3           d         core6           d         core7           d               idle-states         hpsci       cpu-off-l             arm,idle-state          u            Œ        �   2        ®   _        ¾  D        \         cpu-off-b             arm,idle-state          u            Œ        �   -        ®   Œ        ¾  ä        \         cluster-off-l             arm,idle-state          u          Œ        �   7        ®   ›        ¾  H        \         cluster-off-b             arm,idle-state          u          Œ        �   2        ®   È        ¾  è        \            l2-cache0             cache           Ï           Ò           ß   @        ñ           (            Û        \         l2-cache1             cache           Ï           Ò           ß   @        ñ           (            Û        \         l3-cache              cache           Ï           Ò            ß   @        ñ            Û        \            oscillator-13m            fixed-clock         é            � Æ]@        öclk13m          \   5      oscillator-26m            fixed-clock         é            �Œº€        öclk26m          \   7      oscillator-32k            fixed-clock         é            �  €         öclk32k        opp-table-gpu             operating-points-v2          	        \   g   opp-390000000               >í€         Æ        )   ÿ      opp-431000000               °‰À         öì        )   ÿ      opp-473000000               1h@         	'À        )   ÿ      opp-515000000               ²FÀ         	X”        )   ÿ      opp-556000000               !#ã          	‰h        )   ÿ      opp-598000000               #¤Á€         	º<        )   ÿ      opp-640000000               &%           	ë        )   ÿ      opp-670000000               'ïc€         
ä        )   ÿ      opp-700000000               )¹'          
L¸        )   ÿ      opp-730000000               +‚ê€         
}Œ        )   ÿ      opp-760000000               -L®          
®`        )   ÿ      opp-790000000               /q€         
ß4        )   ÿ      opp-835000000               1ÅÀ         (r        )   ÿ      opp-880000000               4s¼          q°        )   ÿ      opp-915000000               6‰ÊÀ         ÓX        )   �      opp-915000000-5             6‰ÊÀ         ¢„        )   0      opp-915000000-6             6‰ÊÀ         q°        )   p      opp-950000000               8ŸÙ€         5         )   �      opp-950000000-5             8ŸÙ€         ÓX        )   0      opp-950000000-6             8ŸÙ€         q°        )   p         pmu-a55           arm,cortex-a55-pmu                      :                  pmu-a78           arm,cortex-a78-pmu                      :                  psci              arm,psci-1.0            –smc       sound           E           Wokay          6    mediatek,mt8390-mt6359-evk mediatek,mt8188-mt6359-evb            Dmt8390-evk          ^default         l         t  vHeadphone Headphone L Headphone Headphone R AP DMIC AUDGLB AP DMIC MIC_BIAS_0 AP DMIC MIC_BIAS_2 DMIC_INPUT AP DMIC         „         thermal-zones      cpu-little0-thermal         ’  è            –        ¶          trips      trip-alert0         Æ L        Ò  Ð         ?passive         \         trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical             cooling-maps       map0            Ý         0  â   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little1-thermal         ’  è            –        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive         \         trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical             cooling-maps       map0            Ý         0  â   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little2-thermal         ’  è            –        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive         \         trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical             cooling-maps       map0            Ý         0  â   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-little3-thermal         ’  è            –        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive         \         trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical             cooling-maps       map0            Ý         0  â   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-big0-thermal            ’  è            d        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive         \         trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical             cooling-maps       map0            Ý           â   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu-big1-thermal            ’  è            d        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive         \         trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical             cooling-maps       map0            Ý           â   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            apu-thermal         ’  è            ú        ¶          trips      trip-alert0         Æ L        Ò  Ð         ?passive       trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical                gpu-thermal         ’  è            ú        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive         \         trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical             cooling-maps       map0            Ý           â   ÿÿÿÿÿÿÿÿ            gpu1-thermal            ’  è            ú        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive         \         trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical             cooling-maps       map0            Ý           â   ÿÿÿÿÿÿÿÿ            adsp-thermal            ’  è            ú        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive       trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical                vdo-thermal         ’  è            ú        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive       trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical                infra-thermal           ’  è            ú        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive       trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical                cam1-thermal            ’  è            ú        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive       trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical                cam2-thermal            ’  è            ú        ¶         trips      trip-alert0         Æ L        Ò  Ð         ?passive       trip-alert1         Æ s        Ò  Ð         ?hot       trip-crit           Æ †         Ò          	   ?critical                   timer             arm,armv8-timer                   @  :                                             
               � Æ]@      soc                      +             simple-bus          ñ                                õ   performance-controller@11bc10             mediatek,cpufreq-hw          ‹     ¼            ½0               ü           \         interrupt-controller@c000000              arm,gic-v3                     '                        >         ‹                                    :      	               \      ppi-partitions     interrupt-partition-0           S   	   
              \         interrupt-partition-1           S              \               syscon@10000000            mediatek,mt8188-topckgen syscon         ‹                      é           \   #      syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon          ‹                     é           \           \   $      syscon@10003000           mediatek,mt8188-pericfg syscon          ‹     0                é           \   F      pinctrl@10005000              mediatek,mt8188-pinctrl       `  ‹     P            À             á             â             ê              °              0  iiocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint          s        ƒ           �               °         >        :       ë                       ”  ›RPI_GPIO0 RPI_GPIO1   RPI_GPIO4  RPI_GPIO6   RPI_GPIO9 RPI_GPIO10 RPI_GPIO11          RPI_GPIO21  RPI_GPIO23       RPI_GPIO30     RPI_GPIO35 RPI_GPIO36                   RPI_GPIO55 RPI_GPIO56   RPI_GPIO59 RPI_GPIO60         RPI_GPIO69   RPI_GPIO72 RPI_GPIO73 RPI_GPIO74     RPI_GPIO79 RPI_GPIO80 RPI_GPIO81 RPI_GPIO82                                       RPI_GPIO121 RPI_GPIO122 RPI_GPIO123 RPI_GPIO124         \       i2c1-pins           \   a   pins            «  :  9        ²   Ë        ¿  è         mmc0-default-pins           \   Q   pins-clk            «  �        ×           æ   f      pins-cmd-dat          $  «  ¡     Ÿ  ž  š  ™  ˜  —  œ         õ        ×           ²   e      pins-rst            «  ›        ×           ²   e         mmc0-uhs-pins           \   R   pins-clk            «  �        ×           æ   f      pins-cmd-dat          $  «  ¡     Ÿ  ž  š  ™  ˜  —  œ         õ        ×           ²   e      pins-ds         «  ¢        ×           æ   f      pins-rst            «  ›        ×           ²   e         i2c0-pins           \   V   pins            «  8  7        ²   Ë        ¿  è         i2c2-pins           \   W   pins            «  <  ;        ²   Ë        ¿  è         i2c3-pins           \   X   pins            «  >  =        ²   Ë        ¿  è         i2c5-pins           \   c   pins            «  B  A        ²   Ë        ¿  è         i2c6-pins           \   d   pins            «  D  C        ²   Ë        ¿  è         uart0-pins          \   ?   pins            «              ²         uart1-pins          \   @   pins            «  V  W         ²         uart2-pins          \   A   pins            «  #  $         ²         pcie-default            \   _   mux         «  /  0  1         ²         eth-default-pins            \   O   pins-cc         «  ‹  Œ  �  Ž        ×         pins-mdio           «  �  �        ×            õ      pins-power          «  ‘   ’                pins-rxd            «  ‡  ˆ  ‰  Š        ×         pins-txd            «  ƒ  „  …  †        ×            eth-sleep-pins          \   P   pins-cc         «  ‹   Œ   �   Ž       pins-mdio           «  �   �                         pins-rxd            «  ‡   ˆ   ‰   Š       pins-txd            «  ƒ   „   …   †          spi2-pins           \   C   pins-spi            «  O  P  Q  R                  audio-default-pins          \      pins-cmd-dat            «  y  z  {  |         usb-default-pins            \   [   pins-valid          «  U         õ            syscon@10006000       )    mediatek,mt8188-scpsys syscon simple-mfd            ‹     `           power-controller          !    mediatek,mt8188-power-controller                         +            )           \   8   power-domain@0          ‹                         +            )           =   !   power-domain@1          ‹           K   "      #           Rmfg alt         ^   $                     +            )           =   %   power-domain@2          ‹           )          power-domain@3          ‹           )          power-domain@4          ‹           )                power-domain@15         ‹         à  K   #      #      #      #   
   #   3   #   4   #   =   #   ¹   #   ¾   &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &      &          û  Rtop cam ccu img venc vdec wpe cfgck cfgxo ss-sram-cmn ss-sram-v0l0 ss-sram-v0l1 ss-sram-ve0 ss-sram-ve1 ss-sram-ifa ss-sram-cam ss-sram-v1l5 ss-sram-v1l6 ss-sram-rdr ss-iommu ss-imgcam ss-emi ss-subcmn-rdr ss-rsi ss-cmn-l4 ss-vdec1 ss-wpe ss-cvdo-ve1          ^   $                     +            )      power-domain@16         ‹         H  K   #   »   #   À   '      '      '      '      '      '      '         A  Rcfgck cfgxo ss-gals ss-cmn ss-emi ss-iommu ss-larb ss-rsi ss-bus            ^   $                     +            )      power-domain@20         ‹         0  K   #   º   #   ¿   (      (      (      (         8  Rcfgck cfgxo ss-vpp1-g5 ss-vpp1-g6 ss-vpp1-l5 ss-vpp1-l6         ^   $        )          power-domain@22         ‹           K   )            Rss-vdec1-soc-l1         ^   $                     +            )      power-domain@23         ‹           K   *            Rss-vdec2-l1         ^   $        )             power-domain@29         ‹            K   #      #      #   	   #   ½        Rcam ccu bus cfgck           ^   $                     +            )      power-domain@30         ‹         (  K   +       +      +      +      +         6  Rss-cam-l13 ss-cam-l14 ss-cam-mm0 ss-cam-mm1 ss-camsys           ^   $                     +            )      power-domain@32         ‹            K   +      ,       -          $  Rss-camb-sub ss-camb-raw ss-camb-yuv         )          power-domain@31         ‹           K   +      .       /          $  Rss-cama-sub ss-cama-raw ss-cama-yuv         )                power-domain@17         ‹         (  K   #   ¼   #   Á   0       0      0         &  Rcfgck cfgxo ss-larb2 ss-larb3 ss-gals           ^   $                     +            )      power-domain@9          ‹   	        K   #   @   #   ?      	  Rbus hdcp            ^   $        )          power-domain@18         ‹           ^   $        )          power-domain@19         ‹           ^   $        )             power-domain@24         ‹            K   1       1      1      1         0  Rss-ve1-larb ss-ve1-core ss-ve1-gals ss-ve1-sram         ^   $        )          power-domain@21         ‹           K   2      2           Rss-wpe-l7 ss-wpe-l7pce          ^   $        )                power-domain@5          ‹           ^   $        K   3           Rss-pextp-fmem           )          power-domain@7          ‹           K   #   0   #   1        Rseninf0 seninf1         )          power-domain@6          ‹           )          power-domain@10         ‹   
        K   #   E   #   D      	  Rbus main            ^   $                     +            )      power-domain@11         ‹           ^   $                     +            )      power-domain@14         ‹           K   #   F        Rasm         ^   $        )          power-domain@13         ‹           K   #   S   #      4            Ra1sys intbus adspck         ^   $        )          power-domain@12         ‹           ^   $        )                power-domain@8          ‹           K   3         	  Rethermac            ^   $        )                watchdog@10007000             mediatek,mt8188-wdt         ‹     p                 p        \           \   9      syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon           ‹     À                é           \   "      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer         ‹    p                :      	               K   5      pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon          ‹    @                ipwrap           :       ó               K   $      $          	  Rspi wrap       pmic              mediatek,mt6359          >                   ˆ                        :   Þ           ™       Þ      adc           mediatek,mt6359-auxadc          ­         audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            ¿vs1         Î 5         æ !‘À        þ                   buck_vgpu11       
  ¿dvdd_core           Î €        æ 7        .  ˆ        þ   È        C                         buck_vmodem         ¿vmodem          Î €        æ Èà        .  *        þ   È      buck_vpu          
  ¿dvdd_adsp           Î €        æ 7        .  ˆ        þ   È        C                         buck_vcore          ¿dvdd_proc_l         Î €        æ Ö         .  ˆ        þ   È        C                         buck_vs2            ¿vs2         Î 5         æ j         þ                   buck_vpa            ¿vpa_pmu         Î ¡         æ /M`        þ  ,      buck_vproc2         ¿vgpu            Î dp        æ 5         .  L        þ   È        C                  [   %        r  j        \   !      buck_vproc1         ¿vproc1          Î €        æ 7        .  L        þ   È        C                buck_vcore_sshub            ¿vcore_sshub         Î €        æ 7      buck_vgpu11_sshub           ¿vgpu11_sshub            Î €        æ 7      ldo_vaud18          ¿vaud18          Î w@        æ w@        þ   ð      ldo_vsim1         
  ¿vsim1_pmu           Î ð         æ /M`        þ  à      ldo_vibr            ¿vibr            Î O€        æ 2Z       ldo_vrf12           ¿va12_abb2_pmu           Î Èà        æ Ö                ldo_vusb            ¿vusb            Î -ÆÀ        æ -ÆÀ        þ  À                 \   G      ldo_vsram_proc2         ¿vsram_proc2         Î ¡         æ ½¶        .  L        þ   ð               ldo_vio18           ¿vio18           Î ð         æ ýà        þ  À               ldo_vcamio          ¿vcamio          Î ð         æ ýà      ldo_vcn18         
  ¿vcn18_pmu           Î w@        æ w@        þ   ð               ldo_vfe28           ¿vfe28           Î *¹€        æ *¹€        þ   x      ldo_vcn13           ¿vcn13           Î »         æ Ö       ldo_vcn33_1_bt          ¿vcn33_1_bt          Î *¹€        æ 5gà      ldo_vcn33_1_wifi            ¿vcn33_1_wifi            Î *¹€        æ 5gà      ldo_vaux18          ¿vaux18          Î w@        æ w@        þ   ð               ldo_vsram_others          
  ¿vsram_gpu           Î q°        æ 5         .  ˆ        þ   ð        [   !        r  j        \   %      ldo_vefuse          ¿vefuse          Î ð         æ „€      ldo_vxo22           ¿vxo22           Î w@        æ !‘À               ldo_vrfck           ¿vrfck           Î ã`        æ ð       ldo_vrfck_1         ¿vrfck           Î ëÀ        æ j       ldo_vbif28          ¿vbif28          Î *¹€        æ *¹€        þ   ð      ldo_vio28           ¿vio28           Î *¹€        æ 2Z                ldo_vemc            ¿vemc            Î ,@         æ 2Z       ldo_vemc_1          ¿vemc            Î &%         æ 2Z         \   S      ldo_vcn33_2_bt          ¿vcn33_2_pmu         Î *¹€        æ 5gà               ldo_vcn33_2_wifi            ¿vcn33_2_wifi            Î *¹€        æ 5gà      ldo_va12            ¿va12            Î O€        æ Ö                ldo_va09            ¿va09            Î 5         æ O€      ldo_vrf18           ¿vrf18           Î ð         æ žP      ldo_vsram_md          	  ¿vsram_md            Î ¡         æ ½¶        .  *        þ   ð      ldo_vufs            ¿vufs18_pmu          Î ð         æ ýà                 \   T      ldo_vm18            ¿vm18            Î ð         æ ýà               ldo_vbbck           ¿vbbck           Î Èà        æ O€               ldo_vsram_proc1         ¿vsram_proc1         Î ¡         æ ½¶        .  L        þ   ð               ldo_vsim2           ¿vsim2           Î ð         æ /M`      ldo_vsram_others_sshub          ¿vsram_others_sshub          Î ¡         æ ½¶         rtc           mediatek,mt6358-rtc       keys              mediatek,mt6359-keys            �           ¨       power-key           »   t         Ê               spmi@10027000         *    mediatek,mt8188-spmi mediatek,mt8195-spmi            ‹    p            �                ipmif spmimst            Ø   #   8        è   #   ¬        K   $      $       #   8      (  Rpmif_sys_ck pmif_tmr_ck spmimst_clk_mux       iommu@10315000            mediatek,mt8188-iommu-infra         ‹    1P                :                     ÿ           \   ]      mailbox@10320000              mediatek,mt8188-gce         ‹    2        @         :       â                          K   $           \   h      mailbox@10330000              mediatek,mt8188-gce         ‹    3        @         :       ä                          K   $           \   j      scp@10720000              mediatek,mt8188-scp-dual            ‹    r                 icfg                      +           õ        P             Wokay       scp@0             mediatek,scp-core           ‹               isram            :      Î               Wokay               6        \   k      scp@d0000             mediatek,scp-core           ‹    ð         isram            :      Ï             	  Wdisabled             audio-controller@10b10000             mediatek,mt8188-afe         ‹    ±                 Ø   #   S        è   #   „      ´  K   7   "   	   "   
   #   ³   #   ´   #   µ   #   ¶   #   ¸   #   S   #      #       #   E   #   Q   #   M   #   N   #   O   #   P   4       #   „   #   †   #   ·   #   T   #   R      ÿ  Rclk26m apll1 apll2 apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 top_a1sys_hp top_aud_intbus top_audio_h top_audio_local_bus top_dptx top_i2so1 top_i2so2 top_i2si1 top_i2si2 adsp_audio_26m apll1_d4 apll2_d4 apll12_div4 top_a2sys top_aud_iec          :      6               &   8           4   9         	  ;audiosys            ^   $        G   #        Wokay               :        \         adsp@10b80000             mediatek,mt8188-dsp       @  ‹    ¸              Ð             ¸°            ¸ð                icfg sram sec bus            Ø   #   D        K   #   D   #   E        Raudiodsp adsp_bus           Y   ;   <        `rx tx           &   8           Wokay               =   >        \         mailbox@10b86100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         ‹    ¸a                :      Þ                           \   ;      mailbox@10b87100          4    mediatek,mt8188-adsp-mbox mediatek,mt8186-adsp-mbox         ‹    ¸q                :      ß                           \   <      clock-controller@10b91100             mediatek,mt8188-adsp-audio26m           ‹    ¹                é           \   4      serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart           ‹                     :       �               K   7   $         	  Rbaud bus            Wokay            ^default         l   ?      serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart           ‹                     :       Ž               K   7   $         	  Rbaud bus            Wokay            ^default         l   @      serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart           ‹                     :       �               K   7   $         	  Rbaud bus            Wokay            ^default         l   A      serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart           ‹                     :      Ó               K   7   $         	  Rbaud bus          	  Wdisabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc           ‹                      K   $           Rmain            ­         	  Wdisabled          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon           ‹     0                é           \   3      spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ‹                      :       ¿               K   #   y   #      $           Rparent-clk sel-clk spi-clk        	  Wdisabled          thermal-sensor@1100b000           mediatek,mt8188-lvts-ap         ‹     °                :       È               K   $           4   $           k   B        wlvts-calib-data-1           ˆ           \         pwm@1100e000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           ‹     à                K   #   '   $   /        Rmain mm         :       Ë               ž         	  Wdisabled          pwm@1100f000          2    mediatek,mt8188-disp-pwm mediatek,mt8183-disp-pwm           ‹     ð                K   #   (   $   F        Rmain mm         :                     ž         	  Wdisabled          spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ‹                     :       À               K   #   y   #      $   2        Rparent-clk sel-clk spi-clk        	  Wdisabled          spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ‹                     :       Á               K   #   y   #      $   3        Rparent-clk sel-clk spi-clk          Wokay            ^default         l   C        ©          spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ‹    0                :       Â               K   #   y   #      $   4        Rparent-clk sel-clk spi-clk        	  Wdisabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ‹    €                :       Ã               K   #   y   #      $   8        Rparent-clk sel-clk spi-clk        	  Wdisabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +            ‹    �                :       Ä               K   #   y   #      $   9        Rparent-clk sel-clk spi-clk        	  Wdisabled          usb@11201000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ‹            -ÿ     >              	  imac ippc            õ                     ?                      +           :       €               Ø   #   )        è   #   v        K   3   	   #   Å   3   
        Rsys_ck ref_ck mcu_ck            ½   D      E            Ê        Â   F  h           Wokay            Ùhost            ásuper-speed         ï   G   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ‹                       imac         :       �               Ø   #   *        è   #   v        K   3   
        Rsys_ck          Wokay                         +            ï   G   hub@1             usb451,8027         ‹           ý   H                              I        \   J      hub@2             usb451,8025         ‹           ý   J                              I        \   H            ethernet@11021000         ;    mediatek,mt8188-gmac mediatek,mt8195-gmac snps,dwmac-5.10a          ‹           @         :      Ì               macirq        0  K   3       3      #   A   #   B   #   C   3         .  Raxi apb mac_main ptp_ref rmii_internal mac_cg           Ø   #   A   #   B   #   C        è   #       #   ¢   #   £        &   8           -   $        >   K        N   L        a   M        t                      Š            Wokay          	  —rgmii-id                N        ^default sleep           l   O        «   P         µ        Æ            Û        ñ      *ø @        	       “      mdio              snps,dwmac-mdio                      +       ethernet-phy@3            ethernet-phy-ieee802.3-c22          ‹           ™       ”            	        \   N         stmmac-axi-config           	'                                 	1           	A           \   K      rx-queues-config            	Q            	g        \   L   queue0           	x        	‹          queue1           	x        	‹          queue2           	x        	‹          queue3           	x        	‹             tx-queues-config            	£            	¹        \   M   queue0           	x        	Ë            	Ù         queue1           	x        	Ë           	Ù         queue2           	x        	Ë           	Ù         queue3           	x        	Ë           	Ù               mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ‹    #             õ                 :       ƒ                K   #      $      $      $   M      !  Rsource hclk source_cg crypto_clk            Wokay            ^default state_uhs           l   Q        «   R        	å           	ïëÂ          	ý         
         
         
-         
:         
K         
S        
Y H        
h   S        
t   T         
�      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ‹    $             ë                 :       ‡               K   #      $      $   $        Rsource hclk source_cg           Ø   #           è   #   �      	  Wdisabled          mmc@11250000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc          ‹    %             æ                 :       ˆ               K   #      $      $   A        Rsource hclk source_cg           Ø   #           è   #   �      	  Wdisabled          thermal-sensor@11278000           mediatek,mt8188-lvts-mcu            ‹    '€                :       Ê               K   $           4   $            k   B        wlvts-calib-data-1           ˆ           \         i2c@11280000              mediatek,mt8188-i2c          ‹    (             " €       €        :       —               
�           K   U       $   7      	  Rmain dma                         +            Wokay            ^default         l   V        � €      i2c@11281000              mediatek,mt8188-i2c          ‹    (            "€       €        :       ’               
�           K   U      $   7      	  Rmain dma                         +            Wokay            ^default         l   W        � €      i2c@11282000              mediatek,mt8188-i2c          ‹    (             "€       €        :       “               
�           K   U      $   7      	  Rmain dma                         +            Wokay            ^default         l   X        � €      clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c          ‹    (0                é           \   U      usb@112a1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ‹    *       -ÿ    *>              	  imac ippc            õ            *        ?                      +           :                     Ø   #   -        è   #   v        K   3      #   Ë   3           Rsys_ck ref_ck mcu_ck            ½   Y            Ê        Â   F  p           Wokay            Ùhost            áhigh-speed          ï   G   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ‹                       imac         :                     Ø   #   .        è   #   v        K   3           Rsys_ck          Wokay                         +            ï   G   hub@1             microchip,usb2513bi         ‹              I            usb@112b1000          #    mediatek,mt8188-mtu3 mediatek,mtu3           ‹    +       -ÿ    +>              	  imac ippc            õ            +        ?                      +           :                     Ø   #   ,        è   #   v        K   3      #   É   3           Rsys_ck ref_ck mcu_ck            ½   Z            Ê        Â   F  `           Wokay            Ùperipheral          ^default         l   [        ï   G   usb@0         '    mediatek,mt8188-xhci mediatek,mtk-xhci          ‹                       imac         :                     Ø   #   +        è   #   v        K   3           Rsys_ck        	  Wdisabled             pcie@112f0000         *    mediatek,mt8188-pcie mediatek,mt8192-pcie           ‹    /                	  ipcie-mac            õ‚                                  
™       ÿ        pci         
£                         +         0  K   $   L   $   #   $   &   $   +   $   C   3         /  Rpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                     :                   `  
´                  \                      \                     \                     \           
Â                       
Õ       ]      ÿÿ        
ß            ½   ^         	  
îpcie-phy            &   8           4   9           ;mac         Wokay            ^default         l   _   interrupt-controller                                     >        \   \         spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor         ‹    2À                K   #   X   3      3           Rspi sf axi          Ø   #   X        :      9                            +          	  Wdisabled          t-phy@11c20700        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3           õ        Â                         +           &   8           Wokay       pcie-phy@0          ‹               K   #   Ä        Rref         
ø           \   ^         dsi-phy@11c80000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         ‹    È                 K   7        ömipi_tx0_pll            é            
ø          	  Wdisabled            \         dsi-phy@11c90000          0    mediatek,mt8188-mipi-tx mediatek,mt8183-mipi-tx         ‹    É                 K   7        ömipi_tx0_pll            é            
ø          	  Wdisabled            \   €      i2c@11e00000              mediatek,mt8188-i2c          ‹    à             "        €        :       ˜               
�           K   `       $   7      	  Rmain dma                         +            Wokay            ^default         l   a        � €      i2c@11e01000              mediatek,mt8188-i2c          ‹    à            "€       €        :       ”               
�           K   `      $   7      	  Rmain dma                         +          	  Wdisabled          clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w          ‹    à                 é           \   `      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           õ        ã             Wokay       usb-phy@0           ‹               K   #   Ê   "           Rref da_ref          
ø           \   Z         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           õ        ä             Wokay       usb-phy@0           ‹               K   #   Æ   "           Rref da_ref          
ø           \   D      usb-phy@700         ‹              K   "      7        Rref da_ref          
ø           \   E         t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +           õ        è             Wokay       usb-phy@0           ‹               K   #   Ì   "           Rref da_ref          
ø           \   Y         i2c@11ec0000              mediatek,mt8188-i2c          ‹    ì             "€       €        :       •               
�           K   b       $   7      	  Rmain dma                         +            Wokay            ^default         l   c        � €      i2c@11ec1000              mediatek,mt8188-i2c          ‹    ì            "        €        :       –               
�           K   b      $   7      	  Rmain dma                         +            Wokay            ^default         l   d        � €      clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en         ‹    ì                 é           \   b      efuse@11f20000        ,    mediatek,mt8188-efuse mediatek,mt8186-efuse         ‹    ò                              +      dp-calib@1a0            ‹              \   †      lvts1-calib@1ac         ‹  ¬   @        \   B      gpu-speedbin@581            ‹  �                          \   f      socinfo-data1@7a0           ‹            socinfo-data2@7e0           ‹  à            gpu@13000000          )    mediatek,mt8370-mali arm,mali-valhall-jm            ‹             @         K   e          0  :                   ~             }               job mmu gpu         k   f      
  wspeed-bin              g        &   8      8           core0 core1         M           Wokay            /   !        \         clock-controller@13fbf000             mediatek,mt8188-mfgcfg          ‹    ûð                é           \   e      syscon@14000000           mediatek,mt8188-vppsys0 syscon          ‹                      é           \   &      dma-controller@14001000           mediatek,mt8188-mdp3-rdma           ‹                     ;           K   &         <  Y   h         h         h         h         h              F   i   €        &   8           M   j                  e              y   k      display@14002000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ‹                      K   &            M   j                 display@14004000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ‹     @                K   &   "        M   j      @          display@14005000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ‹     P                :      F               K   &   
        &   8           M   j      P          display@14006000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ‹     `                K   &           M   j      `            e    %      display@14007000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ‹     p                K   &   #        M   j      p          display@14008000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ‹     €                :      I               K   &   $        &   8           M   j      €          display@14009000          2    mediatek,mt8188-mdp3-ovl mediatek,mt8195-mdp3-ovl           ‹     �                :      J               K   &   %        &   8           M   j      �            F   i   ‚      display@1400a000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ‹                      K   &           &   8           M   j                 display@1400b000          2    mediatek,mt8188-mdp3-tcc mediatek,mt8195-mdp3-tcc           ‹     °                K   &           M   j      °          display@1400c000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ‹     À                ;           K   &           F   i   ƒ        &   8           M   j      À            e    +      mutex@1400f000            mediatek,mt8188-vpp-mutex           ‹     ð                :      P               K   &           &   8           M   j      ð          smi@14012000              mediatek,mt8188-smi-common-vpp          ‹                     K   &      &           Rapb smi         &   8           \   l      smi@14013000              mediatek,mt8188-smi-larb            ‹    0                K   &      &           Rapb smi         &   8           †           —   l        \   o      iommu@14018000            mediatek,mt8188-iommu-vpp           ‹    €       P         K   &           Rbclk            :      R               &   8           ÿ           ¤   m   n   o   p   q   r        \   i      dma-controller@14f09000           mediatek,mt8188-mdp3-rdma           ‹    ð�                ;           K   (   
        F   s   ¤        &   8           M   j   	  �            e  …  ©      dma-controller@14f0a000           mediatek,mt8188-mdp3-rdma           ‹    ð                 ;           K   (           F   i   À        &   8           M   j   	               e  †  ª      display@14f0c000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ‹    ðÀ                K   (           M   j   	  À          display@14f0d000          0    mediatek,mt8188-mdp3-fg mediatek,mt8195-mdp3-fg         ‹    ðÐ                K   (           M   j   	  Ð          display@14f0f000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ‹    ðð                K   (   "        M   j   	  ð          display@14f10000          2    mediatek,mt8188-mdp3-hdr mediatek,mt8195-mdp3-hdr           ‹    ñ                 K   (   $        M   j   
             display@14f12000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ‹    ñ                 :      j               K   (   #        &   8           M   j   
             display@14f13000          2    mediatek,mt8188-mdp3-aal mediatek,mt8195-mdp3-aal           ‹    ñ0                :      k               K   (   %        &   8           M   j   
  0          display@14f15000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ‹    ñP                K   (           M   j   
  P            e  ‘  °      display@14f16000          2    mediatek,mt8188-mdp3-rsz mediatek,mt8183-mdp3-rsz           ‹    ñ`                K   (           M   j   
  `            e  ’  ±      display@14f18000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ‹    ñ€                K   (           M   j   
  €          display@14f19000          6    mediatek,mt8188-mdp3-tdshp mediatek,mt8195-mdp3-tdshp           ‹    ñ�                K   (           M   j   
  �          display@14f1a000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           ‹    ñ                 K   (           &   8           M   j   
             display@14f1b000          6    mediatek,mt8188-mdp3-merge mediatek,mt8195-mdp3-merge           ‹    ñ°                K   (           &   8           M   j   
  °          display@14f1d000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ‹    ñÐ                :      u               K   (           &   8           M   j   
  Ð          display@14f1e000          6    mediatek,mt8188-mdp3-color mediatek,mt8195-mdp3-color           ‹    ñà                :      v               K   (           &   8           M   j   
  à          display@14f21000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ‹    ò                K   (           &   8           M   j               display@14f22000          :    mediatek,mt8188-mdp3-padding mediatek,mt8195-mdp3-padding           ‹    ò                 K   (           &   8           M   j                display@14f24000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ‹    ò@                ;           K   (           F   s   ¦        &   8           M   j     @            e     ¬      display@14f25000          4    mediatek,mt8188-mdp3-wrot mediatek,mt8183-mdp3-wrot         ‹    òP                ;           K   (           F   i   Â        &   8           M   j     P            e  ¡  ­      clock-controller@14e00000             mediatek,mt8188-wpesys          ‹    à                 é           \   2      clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0         ‹    à                 é         smi@14e04000              mediatek,mt8188-smi-larb            ‹    à@                K   2      2           Rapb smi         &   8           †           —   l        \   q      syscon@14f00000           mediatek,mt8188-vppsys1 syscon          ‹    ð                 é           \   (      mutex@14f01000            mediatek,mt8188-vpp-mutex           ‹    ð                :      {               K   (   &        &   8           M   j   	            smi@14f02000              mediatek,mt8188-smi-larb            ‹    ð                 K   (      (           Rapb smi         &   8           †           —   t        \   ƒ      smi@14f03000              mediatek,mt8188-smi-larb            ‹    ð0                K   (      (           Rapb smi         &   8           †           —   l        \   p      clock-controller@15000000             mediatek,mt8188-imgsys          ‹                      é         clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top         ‹                     é           \         clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr          ‹                     é           \         clock-controller@15220000             mediatek,mt8188-imgsys-wpe1         ‹    "                 é           \         clock-controller@15330000             mediatek,mt8188-ipesys          ‹    3                 é           \         clock-controller@15520000             mediatek,mt8188-imgsys-wpe2         ‹    R                 é           \         clock-controller@15620000             mediatek,mt8188-imgsys-wpe3         ‹    b                 é           \         clock-controller@16000000             mediatek,mt8188-camsys          ‹                      é           \   +      clock-controller@1604f000             mediatek,mt8188-camsys-rawa         ‹    ð                é           \           \   .      clock-controller@1606f000             mediatek,mt8188-camsys-yuva         ‹    ð                é           \           \   /      clock-controller@1608f000             mediatek,mt8188-camsys-rawb         ‹    ð                é           \           \   ,      clock-controller@160af000             mediatek,mt8188-camsys-yuvb         ‹    
ð                é           \           \   -      clock-controller@17200000             mediatek,mt8188-ccusys          ‹                      é         video-decoder@18000000            mediatek,mt8188-vcodec-dec           ‹                   @                õ                    `         F   i  æ                     +           y   k   video-codec@10000             mediatek,mtk-vcodec-lat         ‹                      Ø   #   4        è   #   x         K   #   4   )      )      #   x        Rsel vdec lat top            :      Ä             H  F   i  à   i  á   i  â   i  ã   i  ä   i  å   i  æ   i  ç   i  è        &   8         video-codec@25000             mediatek,mtk-vcodec-core            ‹     P                Ø   #   4        è   #   x         K   #   4   *      *      #   x        Rsel vdec lat top            :      Ã             X  F   s  À   s  Á   s  Â   s  Ã   s  Ä   s  Å   s  Æ   s  Ç   s  È   s  É   s  Ê        &   8            smi@1800d000              mediatek,mt8188-smi-larb            ‹     Ð                K   )       )            Rapb smi         &   8           †           —   l        \   r      clock-controller@1800f000             mediatek,mt8188-vdecsys-soc         ‹     ð                é           \   )      smi@1802e000              mediatek,mt8188-smi-larb            ‹    à                K   *       *            Rapb smi         &   8           †           —   t        \   …      clock-controller@1802f000             mediatek,mt8188-vdecsys         ‹    ð                é           \   *      clock-controller@1a000000             mediatek,mt8188-vencsys         ‹                      é           \   1      smi@1a010000              mediatek,mt8188-smi-larb            ‹                     K   1      1           Rapb smi         &   8           †           —   t        \   „      video-encoder@1a020000            mediatek,mt8188-vcodec-enc          ‹                                  +           Ø   #   3        è   #   p        K   1         	  Rvenc_sel            :      a             X  F   s      s  ¡   s  ¢   s  £   s  ¤   s  ¶   s  ·   s  ¸   s  ¹   s  ª   s  º        &   8           y   k      jpeg-encoder@1a030000         +    mediatek,mt8188-jpgenc mediatek,mtk-jpgenc          ‹                     K   1           Rjpgenc          :      b                F   s  §   s  ¨   s  ©   s  ¬        &   8         jpeg-decoder@1a040000         .    mediatek,mt8188-jpgdec mediatek,mt2701-jpgdec           ‹                     K   1       1           Rjpgdec-smi jpgdec           :      c             0  F   s  ­   s  ®   s  ²   s  ³   s  ´   s  µ        &   8         ovl@1c000000          2    mediatek,mt8188-disp-ovl mediatek,mt8195-disp-ovl           ‹                      K   '            :      |               F   s           &   8           M   h             ports                        +       port@0          ‹       endpoint             port@1          ‹      endpoint            ³   u        \   v               rdma@1c002000         4    mediatek,mt8188-disp-rdma mediatek,mt8195-disp-rdma         ‹                      K   '           :      ~               F   i            &   8           M   h             ports                        +       port@0          ‹       endpoint            ³   v        \   u         port@1          ‹      endpoint            ³   w        \   x               color@1c003000        6    mediatek,mt8188-disp-color mediatek,mt8173-disp-color           ‹     0                K   '           :                     &   8           M   h     0       ports                        +       port@0          ‹       endpoint            ³   x        \   w         port@1          ‹      endpoint            ³   y        \   z               ccorr@1c004000        6    mediatek,mt8188-disp-ccorr mediatek,mt8192-disp-ccorr           ‹     @                K   '           :      €               &   8           M   h     @       ports                        +       port@0          ‹       endpoint            ³   z        \   y         port@1          ‹      endpoint            ³   {        \   |               aal@1c005000          2    mediatek,mt8188-disp-aal mediatek,mt8183-disp-aal           ‹     P                K   '           :      �               &   8           M   h     P       ports                        +       port@0          ‹       endpoint            ³   |        \   {         port@1          ‹      endpoint            ³   }        \   ~               gamma@1c006000        6    mediatek,mt8188-disp-gamma mediatek,mt8195-disp-gamma           ‹     `                K   '           :      ‚               &   8           M   h     `       ports                        +       port@0          ‹       endpoint            ³   ~        \   }         port@1          ‹      endpoint                   dither@1c007000       8    mediatek,mt8188-disp-dither mediatek,mt8183-disp-dither         ‹     p                K   '           :      ƒ               &   8           M   h     p       ports                        +       port@0          ‹       endpoint             port@1          ‹      endpoint                   dsi@1c008000              mediatek,mt8188-dsi         ‹     €                K   '      '              Rengine digital hs           :      „               ½           
îdphy            &   8           4   '         	  Wdisabled          dsc@1c009000          2    mediatek,mt8188-disp-dsc mediatek,mt8195-disp-dsc           ‹     �                K   '   
        :      …               &   8           M   h     �          dsi@1c012000              mediatek,mt8188-dsi         ‹                     K   '   	   '      €        Rengine digital hs           :      Ž               ½   €        
îdphy            &   8           4   '   	      	  Wdisabled          merge0@1c014000       6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ‹    @                K   '      0           Rmerge merge_async           :      �               &   8           M   h     @          dp-intf@1c015000              mediatek,mt8188-dp-intf         ‹    P                K   '       '      "           Rpixel engine pll            :      ‘               &   8         	  Wdisabled          mutex@1c016000            mediatek,mt8188-disp-mutex          ‹    `                K   '           :      ’               &   8           M   h     `            e  >      postmask@1c01a000         <    mediatek,mt8188-disp-postmask mediatek,mt8192-disp-postmask         ‹                     K   '           :      •               &   8           M   h             ports                        +       port@0          ‹       endpoint             port@1          ‹      endpoint                   syscon@1c01d000           mediatek,mt8188-vdosys0 syscon          ‹    Ð                é           \           Y   h               M   h     Ð            \   '      smi@1c022000              mediatek,mt8188-smi-larb            ‹                     K   '      '           Rapb smi         &   8           †            —   t        \   �      smi@1c023000              mediatek,mt8188-smi-larb            ‹    0                K   '      '           Rapb smi         &   8           †           —   l        \   m      smi@1c024000              mediatek,mt8188-smi-common-vdo          ‹    @                K   '      '           Rapb smi         &   8           \   t      iommu@1c028000            mediatek,mt8188-iommu-vdo           ‹    €       P         K   '           Rbclk            :      ¡               &   8           ÿ           ¤   �   ‚   ƒ   „   …        \   s      syscon@1c100000           mediatek,mt8188-vdosys1 syscon          ‹                     é           \           Y   h              M   h                  \   0      mutex@1c101000            mediatek,mt8188-disp-mutex          ‹                    K   0           :      î               &   8           M   h                 e  Å      smi@1c102000              mediatek,mt8188-smi-larb            ‹                     K   0       0            Rapb smi         &   8           †           —   t        \   ‚      smi@1c103000              mediatek,mt8188-smi-larb            ‹    0                K   0      0           Rapb smi         &   8           †           —   l        \   n      rdma@1c104000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ‹    @                K   0           :      ï               F   s   @        &   8           ;           M   h     @          rdma@1c105000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ‹    P                K   0           :      ð               F   i   `        &   8           ;           M   h     P          rdma@1c106000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ‹    `                K   0           :      ñ               F   s   A        &   8           ;           M   h     `          rdma@1c107000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ‹    p                K   0           :      ò               F   i   a        &   8           ;           M   h     p          rdma@1c108000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ‹    €                K   0           :      ó               F   s   B        &   8           ;           M   h     €          rdma@1c109000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ‹    �                K   0           :      ô               F   i   b        &   8           ;           M   h     �          rdma@1c10a000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ‹                     K   0           :      õ               F   s   C        &   8           ;           M   h                rdma@1c10b000         4    mediatek,mt8188-vdo1-rdma mediatek,mt8195-vdo1-rdma         ‹    °                K   0           :      ö               F   i   c        &   8           ;           M   h     °          merge@1c10c000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ‹    À                K   0   	   0           Rmerge merge_async           :      ÷               &   8           4   0           M   h     À             Ã      merge@1c10d000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ‹    Ð                K   0   
   0           Rmerge merge_async           :      ø               &   8           4   0           M   h     Ð             Ã      merge@1c10e000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ‹    à                K   0      0           Rmerge merge_async           :      ù               &   8           4   0           M   h     à             Ã      merge@1c10f000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ‹    ð                K   0      0           Rmerge merge_async           :      ú               &   8           4   0           M   h     ð             Ã      merge@1c110000        6    mediatek,mt8188-disp-merge mediatek,mt8195-disp-merge           ‹                     K   0      0           Rmerge merge_async           :      û               &   8           4   0           M   h                   ×      dp-intf@1c113000              mediatek,mt8188-dp-intf         ‹    0                K   0   :   0      "           Rpixel engine pll            :                     &   8         	  Wdisabled          ethdr@1c114000        6    mediatek,mt8188-disp-ethdr mediatek,mt8195-disp-ethdr         p  ‹    @            P            p            �                         °            À              4  imixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       h  K   0   0   0   +   0   .   0   ,   0   /   0   -   0   <   0   1   0   2   0   3   0   4   0   5   #         ƒ  Rmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          :      6               F   i   d   i   e        &   8         (  4   0   1   0   2   0   3   0   4   0   5      p  M   h     @       h     P       h     p       h     �       h             h     °       h     À          padding@1c11d000              mediatek,mt8188-disp-padding            ‹    Ð                K   0           &   8           M   h     Ð          padding@1c11e000              mediatek,mt8188-disp-padding            ‹    à                K   0            &   8           M   h     à          padding@1c11f000              mediatek,mt8188-disp-padding            ‹    ð                K   0   !        &   8           M   h     ð          padding@1c120000              mediatek,mt8188-disp-padding            ‹                     K   0   "        &   8           M   h                padding@1c121000              mediatek,mt8188-disp-padding            ‹                    K   0   #        &   8           M   h               padding@1c122000              mediatek,mt8188-disp-padding            ‹                     K   0   $        &   8           M   h                padding@1c123000              mediatek,mt8188-disp-padding            ‹    0                K   0   %        &   8           M   h     0          padding@1c124000              mediatek,mt8188-disp-padding            ‹    @                K   0   &        &   8           M   h     @          edp-tx@1c500000           mediatek,mt8188-edp-tx          ‹    P        €         :      ¤               k   †        wdp_calibration_data         &   8           î  ¤      	  Wdisabled          dp-tx@1c600000            mediatek,mt8188-dp-tx           ‹    `        €         :      Ê               k   †        wdp_calibration_data         &   8           î        	  Wdisabled             chosen          ÿserial0:921600n8          firmware       optee             linaro,optee-tz         –smc          reserved-memory                      +            õ   optee@43200000                   ‹    C        À        memory@50000000           shared-dma-pool         ‹    P       �                   \   6      memory@54600000                  ‹    T`                memory@55000000           shared-dma-pool         ‹    U       @        memory@57000000           shared-dma-pool         ‹    W       @        memory@60000000           shared-dma-pool         ‹    `        ð                   \   >      memory@60f00000           shared-dma-pool         ‹    `ð                          \   :      memory@61000000           shared-dma-pool         ‹    a                           \   =         regulator-vsys            regulator-fixed         ¿vsys                              \   ‡      regulator-0           regulator-fixed       
  ¿fixed-5v0           Î LK@        æ LK@         $                 7   ‡      regulator-1           regulator-fixed       
  ¿fixed-4v2           Î @@        æ @@         $                 7   ‡      regulator-2           regulator-fixed       
  ¿fixed-3v3           Î 2Z         æ 2Z          $                 7   ‡        \   I      memory@40000000         memory          ‹    @                   	compatible interrupt-parent #address-cells #size-cells chassis-type model dp-intf0 dp-intf1 dsc0 ethdr0 gce0 gce1 merge0 merge1 merge2 merge3 merge4 merge5 mutex0 mutex1 padding0 padding1 padding2 padding3 padding4 padding5 padding6 padding7 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c1 mmc0 ethernet0 i2c0 i2c2 i2c3 i2c5 i2c6 serial0 device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names opp-shared opp-hz opp-microvolt opp-supported-hw interrupts mediatek,platform status pinctrl-names pinctrl-0 audio-routing mediatek,adsp polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux bias-pull-up drive-strength-microamp drive-strength bias-pull-down input-enable output-high input-disable bias-disable #power-domain-cells domain-supply clocks clock-names mediatek,infracfg mediatek,disable-extrst #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells memory-region power-domains resets reset-names mediatek,topckgen mboxes mbox-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select phys mediatek,syscon-wakeup dr_mode maximum-speed vusb33-supply peer-hub reset-gpios vdd-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,mac-wol mediatek,tx-delay-ps snps,reset-active-low snps,reset-delays-us snps,reset-gpio eee-broken-1000t snps,blen snps,rd_osr_lmt snps,wr_osr_lmt snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,priority snps,weight bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable clock-div bus-range linux,pci-domain interrupt-map interrupt-map-mask iommu-map iommu-map-mask phy-names #phy-cells bits operating-points-v2 power-domain-names mali-supply #dma-cells iommus mediatek,gce-client-reg mediatek,gce-events mediatek,scp mediatek,larb-id mediatek,smi mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz stdout-path no-map regulator-boot-on enable-active-high vin-supply 