Ðþí kÒ   8 ^   (            ¶ ]ä                             8    mediatek,mt8395-evk-ufs mediatek,mt8395 mediatek,mt8195                                  +         !   7MediaTek Genio 1200 EVK-P1V2-UFS       aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          ƒ/soc/vpp-merge@1c10f000          Š/soc/vpp-merge@1c110000          ‘/soc/dma-controller@1c104000             œ/soc/dma-controller@1c105000             §/soc/dma-controller@1c106000             ²/soc/dma-controller@1c107000             ½/soc/dma-controller@1c108000             È/soc/dma-controller@1c109000             Ó/soc/dma-controller@1c10a000             Þ/soc/dma-controller@1c10b000             é/soc/serial@11001100             ñ/soc/ethernet@11021000        cpus                         +       cpu@0            ûcpu           arm,cortex-a55                      psci                           -ec3@        =  4        P              `  €         m   @           €        Œ  €         ™   @        «   €        ¸           É           Ø           ã         cpu@100          ûcpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `  €         m   @           €        Œ  €         ™   @        «   €        ¸           É           Ø           ã         cpu@200          ûcpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `  €         m   @           €        Œ  €         ™   @        «   €        ¸           É           Ø           ã         cpu@300          ûcpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `  €         m   @           €        Œ  €         ™   @        «   €        ¸           É           Ø           ã         cpu@400          ûcpu           arm,cortex-a78                     psci                          -�fÔÀ        =           P              `           m   @                   Œ           ™   @        «           ¸   	        É           Ø   
        ã         cpu@500          ûcpu           arm,cortex-a78                     psci                          -�fÔÀ        =           P              `           m   @                   Œ           ™   @        «           ¸   	        É           Ø   
        ã         cpu@600          ûcpu           arm,cortex-a78                     psci                          -�fÔÀ        =           P              `           m   @                   Œ           ™   @        «           ¸   	        É           Ø   
        ã         cpu@700          ûcpu           arm,cortex-a78                     psci                          -�fÔÀ        =           P              `           m   @                   Œ           ™   @        «           ¸   	        É           Ø   
        ã         cpu-map    cluster0       core0           ë         core1           ë         core2           ë         core3           ë         core4           ë         core5           ë         core6           ë         core7           ë               idle-states         ïpsci       cpu-retention-l           arm,idle-state          ü                   $   2        5   _        E  D        ã         cpu-retention-b           arm,idle-state          ü                   $   -        5   Œ        E  ä        ã         cpu-off-l             arm,idle-state          ü                  $   7        5   ›        E  H        ã         cpu-off-b             arm,idle-state          ü                  $   2        5   È        E  è        ã            l2-cache0             cache           V           b           o   @        �           ¸            b        ã         l2-cache1             cache           V           b           o   @        �           ¸            b        ã   	      l3-cache              cache           V           b            o   @        �            b        ã            dsu-pmu           arm,dsu-pmu         p                       {                                €fail          dmic-codec            dmic-codec          ‡           ”   È      mt8195-sound            ¤           €okay              mediatek,mt8195_mt6359           7mt8395-evk          ¶default         Ä         ,  ÎHeadphone Headphone L Headphone Headphone R         Ü      headphone-dai-link        
  êDL_SRC_BE      codec           ô                   fixed-factor-clock-13m            fixed-factor-clock          þ                                             'clk13m          ã   /      oscillator-26m            fixed-clock         þ            -Œº€        'clk26m          ã         oscillator-32k            fixed-clock         þ            -  €         'clk32k        performance-controller@11bc10             mediatek,cpufreq-hw               ¼            ½0               :           ã         opp-table-gpu             operating-points-v2          T        ã   �   opp-390000000           _    >í€        f 	‰h      opp-410000000           _    p€        f 	¡Ò      opp-431000000           _    °‰À        f 	¡Ò      opp-473000000           _    1h@        f 	º<      opp-515000000           _    ²FÀ        f 	º<      opp-556000000           _    !#ã         f 	Ò¦      opp-598000000           _    #¤Á€        f 	ë      opp-640000000           _    &%          f 	ë      opp-670000000           _    'ïc€        f 
ä      opp-700000000           _    )¹'         f 
L¸      opp-730000000           _    +‚ê€        f 
}Œ      opp-760000000           _    -L®         f 
®`      opp-790000000           _    /q€        f 
ß4      opp-820000000           _    0à5         f       opp-850000000           _    2©ø€        f @Ü      opp-880000000           _    4s¼         f q°         pmu-a55           arm,cortex-a55-pmu                      p                  pmu-a78           arm,cortex-a78-pmu                      p                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  p                                             
             soc                      +             simple-bus           t        {                          interrupt-controller@c000000              arm,gic-v3          †           —                        ®                                             p      	               ã      ppi-partitions     interrupt-partition-0           Ã                    ã         interrupt-partition-1           Ã                    ã               syscon@10000000            mediatek,mt8195-topckgen syscon                               þ           ã         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                               þ           Ì           ã         syscon@10003000           mediatek,mt8195-pericfg syscon               0                þ           ã   K      pinctrl@10005000              mediatek,mt8195-pinctrl       €       P            Ñ             Ó             Ô             â             ë             ô              °              B  Ùiocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            ã        ó           ÿ              �         ®        p       ë               †           ã      audio-default-pins          ã      pins-cmd-dat          4    =  >  A  B  C  D  E  F  G  H  I  J  K         disp-pwm1-default-pins     pins1             h         edp-panel-12v-en-pins           ã   Ù   pins1             `                   edp-panel-3v3-en-pins           ã   Ø   pins1                                eth-default-pins            ã   G   pins-cc           U  V  W  X                 pins-mdio             Y  Z         -      pins-power            [   \                pins-rxd              Q  R  S  T      pins-txd              M  N  O  P                    eth-sleep-pins          ã   H   pins-cc           U   V   W   X       pins-mdio             Y   Z          :         H      pins-rxd              Q   R   S   T       pins-txd              M   N   O   P          gpio-keys-pins     pins              j          U         -         i2c0-pins           ã   l   pins                	        U   Ï        b  è         i2c1-pins           ã   m   pins              
          U   Ï        b  è         i2c2-pins           ã   p   pins                        U   Ï                    i2c6-pins           ã   e   pins                         U         mmc0-default-pins           ã   P   pins-clk              z                   z   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y         -                   U   e      pins-rst              x                   U   e         mmc0-uhs-pins           ã   Q   pins-clk              z                   z   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y         -                   U   e      pins-ds                              z   f      pins-rst              x                   U   e         mmc1-default-pins           ã   T   pins-clk              o                   z   f      pins-cmd-dat              n  p  q  r  s         -                   U   e         mmc1-uhs-pins           ã   U   pins-clk              o                   z   f      pins-cmd-dat              n  p  q  r  s         -                   U   e         mt6360-pins         ã   f   pins                 €          -         U         dsi0-vreg-en-pins           ã   Ú   pins-pwr-en           /          ‰         panel-default-pins          ã   ¸   pins-rst              l                pins-en           0          ‰         pcie0-default-pins          ã   `   pins                           U         pcie0-idle-pins         ã   a   pins                        H         ‰         pcie1-default-pins          ã   c   pins                           U         disp-pwm0-pins          ã   >   pins-disp-pwm             a         spi1-pins           ã   ?   pins              ˆ  ‰  Š  ‹         H         spi-pins            ã   B   pins              Œ  �  Ž  �         H         touch-pins          ã   o   pins-irq              „          -         H      pins-reset            …                   u3-p0-vbus-default-pins         ã   L   pins-vbus             ?         -         uart0-pins          ã   9   pins              b  c         uart1-pins          ã   :   pins              d  e  f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8195-power-controller                         +            ”           ã   2   power-domain@8                                  +            ”           ¨      power-domain@9             	                            ¶mfg alt         Â                        +            ”           ¨       power-domain@10            
        ”          power-domain@11                    ”          power-domain@12                    ”          power-domain@13                    ”          power-domain@14                    ”                power-domain@15                  Ø                          	      @      A      K      à   !      !      !      !      !      !      !      !      !      !      !      !      !      !      !      !      !      !      !           ¶vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           Â                        +            ”      power-domain@16                  8        â   "   $   "   %   "   &   "   '   "   (   "   )      D  ¶vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         Â                        +            ”      power-domain@17                          á   #      #           ¶vppsys1 vppsys1-0 vppsys1-1         Â           ”          power-domain@22                        $      $      $      $         $  ¶wepsys-0 wepsys-1 wepsys-2 wepsys-3         Â           ”          power-domain@23                       %            ¶vdec0-0         Â                        +            ”       power-domain@24                       &            ¶vdec1-0         Â           ”          power-domain@25                       '            ¶vdec2-0         Â           ”             power-domain@26                       (            ¶venc0-larb          Â                        +            ”       power-domain@27                       )            ¶venc1-larb          Â           ”             power-domain@18                           ã   *       *      *         &  ¶vdosys1 vdosys1-0 vdosys1-1 vdosys1-2           Â                        +            ”      power-domain@19                    Â           ”          power-domain@20                    Â           ”          power-domain@21                          Q        ¶hdmi_tx         ”             power-domain@28                       +       +   
        ¶img-0 img-1         Â                        +            ”      power-domain@29                    ”          power-domain@30                             +      ,           ¶ipe ipe-0 ipe-1         Â           ”             power-domain@31                  (     -       -      -      -      -           ¶cam-0 cam-1 cam-2 cam-3 cam-4           Â                        +            ”      power-domain@32                     ”          power-domain@33            !        ”          power-domain@34            "        ”                   power-domain@0                      Â           ”          power-domain@1                     Â           ”          power-domain@2                     ”          power-domain@3                     ”          power-domain@4                           5      7        ¶csi_rx_top csi_rx_top1          ”          power-domain@5                        .           ¶ether           ”          power-domain@6                           X      n        ¶adsp adsp1                       +            Â           ”      power-domain@7                            g      "      n      2        ¶audio audio1 audio2 audio3          Â           ”                   watchdog@10007000             mediatek,mt8195-wdt          Ô             p                Ì           ã   7      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                À                þ           ã         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer             p                p      	                  /      pwrap@10024000            mediatek,mt8195-pwrap syscon                @                Ùpwrap           p       ó                                  	  ¶spi wrap            ì      $        ü      Ë   pmic              mediatek,mt6359          ®        †                      $      Þ           ã      adc           mediatek,mt6359-auxadc          8         audio-codec           mediatek,mt6359-codec           J           ^           r         regulators            mediatek,mt6359-regulator      buck_vs1            †vs1         • 5         ­ !‘À        Å             á      buck_vgpu11         †vgpu11          • €        ­ 7        õ  ˆ        Å   È        
                   á      buck_vmodem         †vmodem          • €        ­ Èà        õ  *        Å   È      buck_vpu            †vpu         • €        ­ 7        õ  ˆ        Å   È        
                   á      buck_vcore          †vcore           • €        ­ Ö         õ  ˆ        Å   È        
                   á        ã         buck_vs2            †vs2         • 5         ­ j         Å             á      buck_vpa            †vpa         • ¡         ­ 7±Ð        Å  ,      buck_vproc2         †vproc2          • €        ­ 7        õ  L        Å   È        
                buck_vproc1         †vproc1          • €        ­ 7        õ  L        Å   È        
                buck_vcore_sshub            †vcore_sshub         • €        ­ 7      buck_vgpu11_sshub           †vgpu11_sshub            • €        ­ 7      ldo_vaud18          †vaud18          • w@        ­ w@        Å   ð         á      ldo_vsim1           †vsim1           • ð         ­ /M`      ldo_vibr            †vibr            • O€        ­ 2Z         ã   q      ldo_vrf12           †vrf12           • Èà        ­ Ö          á      ldo_vusb            †vusb            • -ÆÀ        ­ -ÆÀ        Å  À         á        ã   M      ldo_vsram_proc2         †vsram_proc2         • ¡         ­ ½¶        õ  L        Å   ð         á      ldo_vio18           †vio18           • ð         ­ ýà        Å  À         á      ldo_vcamio          †vcamio          • ð         ­ ýà         á      ldo_vcn18           †vcn18           • w@        ­ w@        Å   ð      ldo_vfe28           †vfe28           • *¹€        ­ *¹€        Å   x      ldo_vcn13           †vcn13           • »         ­ Ö       ldo_vcn33_1_bt          †vcn33_1_bt          • *¹€        ­ 5gà      ldo_vcn33_1_wifi            †vcn33_1_wifi            • *¹€        ­ 5gà      ldo_vaux18          †vaux18          • w@        ­ w@        Å   ð         á      ldo_vsram_others            †vsram_others            • q°        ­ q°        õ  ˆ        Å   ð        ã          ldo_vefuse          †vefuse          • ð         ­ „€      ldo_vxo22           †vxo22           • w@        ­ !‘À         á      ldo_vrfck           †vrfck           • ã`        ­ ð       ldo_vrfck_1         †vrfck           • ëÀ        ­ j       ldo_vbif28          †vbif28          • *¹€        ­ *¹€        Å   ð      ldo_vio28           †vio28           • *¹€        ­ 2Z          á      ldo_vemc            †vemc            • ,@         ­ 2Z       ldo_vemc_1          †vemc            • &%         ­ 2Z         ã   R      ldo_vcn33_2_bt          †vcn33_2_bt          • 2Z         ­ 2Z         ã   A      ldo_vcn33_2_wifi            †vcn33_2_wifi            • *¹€        ­ 5gà      ldo_va12            †va12            • O€        ­ Ö          á      ldo_va09            †va09            • 5         ­ O€      ldo_vrf18           †vrf18           • ð         ­ žP      ldo_vsram_md          	  †vsram_md            • ¡         ­ ½¶        õ  *        Å   ð      ldo_vufs            †vufs            • ð         ­ ýà        ã   S      ldo_vm18            †vm18            • ð         ­ ýà         á      ldo_vbbck           †vbbck           • Èà        ­ O€         á      ldo_vsram_proc1         †vsram_proc1         • ¡         ­ ½¶        õ  L        Å   ð         á      ldo_vsim2           †vsim2           • ð         ­ /M`      ldo_vsram_others_sshub          †vsram_others_sshub          • ¡         ­ ½¶         rtc           mediatek,mt6358-rtc       keys              mediatek,mt6359-keys            "           ;       power-key           N   t         ]      home            N   f               spmi@10027000             mediatek,mt8195-spmi                 p            �                Ùpmif spmimst                               E      (  ¶pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         ì      $        ü      Ë                     +       pmic@6            mediatek,mt6315-regulator                     regulators     vbuck1          †Vbcpu           • “à        ­ 7        Å           
                   á        ã   
            pmic@7            mediatek,mt6315-regulator                     regulators     vbuck1          †Vgpu            • TÐ        ­ 8        Å           
                  ã                  infra-iommu@10315000              mediatek,mt8195-iommu-infra             1P       P       P  p                                                                         k           ã   ]      mailbox@10320000              mediatek,mt8195-gce             2        @         p       â               x                         ã   ¤      mailbox@10330000              mediatek,mt8195-gce             3        @         p       ä               x                         ã   ‚      scp@10500000              mediatek,mt8195-scp       0      P             r             p        €         Ùsram cfg l1tcm          p      Î               €okay            „   0        ’mediatek/mt8195/scp.img         ã   ƒ      clock-controller@10720000             mediatek,mt8195-scp_adsp                r                 þ           ã   1      dsp@10803000              mediatek,mt8195-dsp              €0            „               	  Ùcfg sram          ,        X         n      Š   1          #      K  ¶adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h              2           ®rx tx           ¹   3   4        €okay            „   5   6        ã         mailbox@10816000              mediatek,mt8195-adsp-mbox           x                �`                p      ¾               ã   3      mailbox@10817000              mediatek,mt8195-adsp-mbox           x                �p                p      ¿               ã   4      mt8195-afe-pcm@10890000           mediatek,mt8195-audio               ‰                 À               2           p      6               Ò   7         	  Ùaudiosys          ”                       Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d      2   1          ó  ¶clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          €okay            „   8        ã         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                p       �                              	  ¶baud bus            €okay            Ä   9        ¶default       serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                p       Ž                              	  ¶baud bus            €okay            Ä   :        ¶default       serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                p       �                              	  ¶baud bus          	  €disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                p      Ó                              	  ¶baud bus          	  €disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                p      Ô                              	  ¶baud bus          	  €disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                p      Õ                              	  ¶baud bus          	  €disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                               ¶main            8         	  €disabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                0                þ           ã   .      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  p       ¿                     ™                    ¶parent-clk sel-clk spi-clk        	  €disabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap              °                p       ©                             Ò               å   ;   <      $  ñlvts-calib-data-1 lvts-calib-data-2                    ã   Õ      svs@1100bc00              mediatek,mt8195-svs              ¼                p       Ç                             ¶main            å   =   ;      (  ñsvs-calibration-data t-calibration-data         Ò              Ùsvs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                à                p       Ë                   2                            *      0        ¶main mm         €okay            ¶default         Ä   >        ã   Ö      pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                ð                p                                      +      N        ¶main mm       	  €disabled            ã   ×      spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 p       À                     ™            3        ¶parent-clk sel-clk spi-clk          €okay            Ä   ?        ¶default         #            7      @      can@0             microchip,mcp2518fd                        @        @1-         $                 R   A        ]   A         spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 p       Á                     ™            4        ¶parent-clk sel-clk spi-clk          €okay            Ä   B        ¶default         #          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                0                p       Â                     ™            5        ¶parent-clk sel-clk spi-clk        	  €disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                €                p       Ã                     ™            <        ¶parent-clk sel-clk spi-clk        	  €disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                �                p       Ä                     ™            =        ¶parent-clk sel-clk spi-clk        	  €disabled          spi@1101d000              mediatek,mt8195-spi-slave               Ð                p       Å                     R        ¶spi         ì              ü      ˜      	  €disabled          spi@1101e000              mediatek,mt8195-spi-slave               à                p       Æ                     S        ¶spi         ì              ü      ˜      	  €disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                      @         p      Ì               lmacirq        .  ¶axi apb mac_main ptp_ref rmii_internal mac_cg         0     .       .         R      S      T   .           ì      R      S      T        ü      Â      Ã      Ä            2           |           �   C        �   D        °   E        Ã           Î           Ù            €okay            ærgmii-rxid          ï   F        ú      ]            
      '  '          î         4        ¶default sleep           Ä   G        E   H   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916                       ã   F         stmmac-axi-config           O           _           o                                 ã   C      rx-queues-config            y            �        ã   D   queue0                    ³          queue1                    ³          queue2                    ³          queue3                    ³             tx-queues-config            Ë            á        ã   E   queue0          ó                     ÿ          queue1          ó                     ÿ         queue2          ó                     ÿ         queue3          ó                     ÿ               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                       -ÿ     >              	  Ùmac ippc            t                     ?                      +           p       €                     /      í      B        ¶sys_ck ref_ck mcu_ck            	   I      J            ]        	   K      g        €okay            	)otg         ¶default         Ä   L         	1        	A   M   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 Ùmac         p       �               ì      ,      -        ü      –      –      $        /      í               B      $  ¶sys_ck ref_ck mcu_ck dma_ck xhci_ck         €okay          ports                        +       port@0                 endpoint            	O   N        ã   h         port@1                endpoint            	O   O        ã   i               mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              #             õ                 p       ƒ                                         ¶source hclk source_cg         	  €disabled            ¶default state_uhs           Ä   P        E   Q        	_           DëÂ          	i         	{         	Š         	™         	ª         	²        	¸ L        	Ç   R        	Ó   S         	à      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              $             Ç                 p       ‡                                 $        ¶source hclk source_cg           ì              ü      ¿        €okay            ¶default state_uhs           Ä   T        E   U        	_           DëÂ          	î         	ÿ         
         
         	ª        	Ç   V        	Ó   W         	à      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              %             æ                 p       ˆ                                  I        ¶source hclk source_cg           ì               ü      ¿      	  €disabled          ufshci@11270000           mediatek,mt8195-ufshci              '        #         p       ‰               	   X      @        ?      @      A      6      7      8      Z      ]      X  ¶ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  
!                                                                         
/        €okay            
H   R        
S   S      thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                '€                p       ª                             Ò              å   ;   <      $  ñlvts-calib-data-1 lvts-calib-data-2                    ã   Ì      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci               )             )>              	  Ùmac ippc            p                     	   Y      Z           ì      .      /        ü      –      –      $     .         ï            .         $  ¶sys_ck ref_ck mcu_ck dma_ck xhci_ck         	   K      h         ]        €okay            	A   M      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               *       -ÿ    *>              	  Ùmac ippc            t            *        ?                      +           p                     ì      0        ü      –           .         ñ   .           ¶sys_ck ref_ck mcu_ck            	   [            ]        	   K      i        €okay            	A   M   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 Ùmac         p                     ì      1        ü      –           .           ¶sys_ck          €okay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               +       -ÿ    +>              	  Ùmac ippc            t            +        ?                      +           p                     ì      2        ü      –           .         ó   .   	        ¶sys_ck ref_ck mcu_ck            	   \            ]        	   K      j        €okay            	A   M   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 Ùmac         p                     ì      3        ü      –           .   	        ¶sys_ck          €okay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            ûpci                      +               /        @       	  Ùpcie-mac            p                     
`       ÿ      8  t�                           ‚                       à          
j       ]              
t          0        V      #      &      +      K   .         /  ¶pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ì      G        ü              	   ^      	  
ƒpcie-phy                2            †           
�                     `  
                   _                      _                     _                     _           €okay            ¶default idle            Ä   `        E   a   interrupt-controller             ®                     †           ã   _         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            ûpci                      +               /€       @       	  Ùpcie-mac            p                     
`       ÿ      8  t�       $       $           ‚       $       $       à          
j       ]              
t          (        W         X         Q   .         /  ¶pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ì      H        ü              	   Z         	  
ƒpcie-phy                2           †           
�                     `  
                   b                      b                     b                     b         	  €disabled            ¶default         Ä   c   interrupt-controller             ®                     †           ã   b         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor             2À                p      9                     o   .      .           ¶spi sf axi                       +          	  €disabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                Á                              +      usb3-tx-imp@184,1             „           
®               ã   x      usb3-rx-imp@184,2             „           
®              ã   w      usb3-intr@185             …           
®              ã   v      usb3-tx-imp@186,1             †           
®               ã   u      usb3-rx-imp@186,2             †           
®              ã   t      usb3-intr@187             ‡           
®              ã   s      usb2-intr-p0@188,1            ˆ           
®             usb2-intr-p1@188,2            ˆ           
®            usb2-intr-p2@189,1            ‰           
®            usb2-intr-p3@189,2            ‰           
®            pciephy-rx-ln1@190,1              �           
®               ã         pciephy-tx-ln1-nmos@190,2             �           
®              ã   ~      pciephy-tx-ln1-pmos@191,1             ‘           
®               ã   }      pciephy-rx-ln0@191,2              ‘           
®              ã   |      pciephy-tx-ln0-nmos@192,1             ’           
®               ã   {      pciephy-tx-ln0-pmos@192,2             ’           
®              ã   z      pciephy-glb-intr@193              “           
®               ã   y      dp-data@1ac           ¬           ã   Ë      lvts1-calib@1bc           ¼           ã   ;      lvts2-calib@1d0           Ð   8        ã   <      svs-calib@580             €   d        ã   =      socinfo-data1@7a0                          t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           t        Ä             €okay       usb-phy@0                                ò        ¶ref         
³           ã   [         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           t        Å             €okay       usb-phy@0                                ô        ¶ref         
³           ã   \         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             È                            'mipi_tx0_pll            þ            
³            €okay            ã   ´      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             É                            'mipi_tx1_pll            þ            
³          	  €disabled            ã   ¼      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        p       š                             d          ;      	  ¶main dma                         +          	  €disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð            "        €        p       ›                             d         ;      	  ¶main dma                         +            €okay            - €        Ä   e        ¶default    pmic@34           mediatek,mt6360            4                    p   €           lIRQB             ®        †           Ä   f   charger           mediatek,mt6360-chg         
¾ Ý@    usb-otg-vbus-regulator          †usb-otg-vbus            • C…(        ­ Xáè         regulator             mediatek,mt6360-regulator           
×   g   buck1         	  †emi_vdd2            • “à        ­ Ö         
                   á      buck2         	  †emi_vddq            • “à        ­ Ö         
                   á        ã   g      ldo1          	  †tp1_p3v0            • 2Z         ­ 2Z         
                á        ã   n      ldo2            †panel1_p1v8         • w@        ­ w@        
               ã   Û      ldo3            †vmc_pmu         • O€        ­ 6î€        
               ã   W      ldo5          	  †vmch_pmu            • )2à        ­ 6î€        
               ã   V      ldo6            †mt6360_ldo1         • ¡         ­           
             ldo7            †emi_vmddr_en            • ¡         ­           
                á         tcpc              mediatek,mt6360-tcpc            $                 lPD_IRQB    connector             usb-c-connector         
çUSB-C           
ídual            
÷ ˜–€        	dual            sink            #"�d        /"�È        9   altmodes       displayport         Eÿ          J  F         ports                        +       port@0                 endpoint            	O   h        ã   N         port@1                endpoint            	O   i        ã   O         port@2                endpoint            	O   j        ã   r                        i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        p       œ                             d         ;      	  ¶main dma                         +          	  €disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s              Ð0                þ           ã   d      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             " €       €        p       �                             k          ;      	  ¶main dma                         +            €okay            - €        Ä   l        ¶default       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à            "        €        p       “                             k         ;      	  ¶main dma                         +            €okay            - €        Ä   m        ¶default    touchscreen@5d            goodix,gt9271              ]        $      „           N      „            X      …            d   n        ¶default         Ä   o         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             "€       €        p       –                             k         ;      	  ¶main dma                         +            €okay            - €        Ä   p        ¶default    typec-mux@48              ite,it5205             H        
H   q         r         ~        €okay       port       endpoint            	O   r        ã   j               i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à0            "€       €        p       ˜                             k         ;      	  ¶main dma                         +          	  €disabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à@            "        €        p       ™                             k         ;      	  ¶main dma                         +          	  €disabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w              àP                þ           ã   k      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           t        ã                 2           €okay       usb-phy@0                                ð           ¶ref da_ref          
³           ã   Y      usb-phy@700                                   ð        ¶ref da_ref          å   s   t   u        ñintr rx_imp tx_imp          
³            ‘        ã   Z         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           t        ä             €okay       usb-phy@0                                î           ¶ref da_ref          
³           ã   I      usb-phy@700                                   î        ¶ref da_ref          å   v   w   x        ñintr rx_imp tx_imp          
³           ã   J         phy@11e80000              mediatek,mt8195-pcie-phy                è                 Ùsif         å   y   z   {   |   }   ~         G  ñglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1              2           
³            €okay            ã   ^      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy               ú        À                     
  ¶unipro mp           
³            €okay            ã   X      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                        @            €          0  p      �             Œ             ‹               ljob mmu gpu         ¥   �      (      2   
   2      2      2      2           ¹core0 core1 core2 core3 core4           €okay            Ì         clock-controller@13fbf000             mediatek,mt8195-mfgcfg              ûð                þ           ã   €      syscon@14000000           mediatek,mt8195-vppsys0 syscon                                þ           Ø   ‚                   ã   !      dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                Ø   ‚                  ð                 ƒ            2              „   €           !         <  ¹   ‚         ‚         ‚         ‚         ‚                       display@14002000              mediatek,mt8195-mdp3-fg                               Ø   ‚                      !          display@14003000              mediatek,mt8195-mdp3-stitch              0                Ø   ‚      0               !         display@14004000              mediatek,mt8195-mdp3-hdr                 @                Ø   ‚      @               !   "      display@14005000              mediatek,mt8195-mdp3-aal                 P                p      F               Ø   ‚      P               !   
            2         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                Ø   ‚      `            ð    %           !         display@14007000              mediatek,mt8195-mdp3-tdshp               p                Ø   ‚      p               !   #      display@14008000              mediatek,mt8195-mdp3-color               €                p      I               Ø   ‚      €               !   $            2         display@14009000              mediatek,mt8195-mdp3-ovl                 �                p      J               Ø   ‚      �               !   %            2              „   ‚      display@1400a000              mediatek,mt8195-mdp3-padding                                  Ø   ‚                      !               2         display@1400b000              mediatek,mt8195-mdp3-tcc                 °                Ø   ‚      °               !         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              À                Ø   ‚      À            ð    +           !              „   ƒ            2                    mutex@1400f000            mediatek,mt8195-vpp-mutex                ð                p      P               Ø   ‚      ð               !               2         smi@14010000              mediatek,mt8195-smi-sub-common                                  !      !      !           ¶apb smi gals0           #   …            2           ã   †      smi@14011000              mediatek,mt8195-smi-sub-common                                 !      !      !           ¶apb smi gals0           #   …            2           ã   £      smi@14012000              mediatek,mt8195-smi-common-vpp                                   !      !      !      !           ¶apb smi gals0 gals1             2           ã   …      larb@14013000             mediatek,mt8195-smi-larb                0                0           #   †           !      !           ¶apb smi             2           ã   ‰      iommu@14018000            mediatek,mt8195-iommu-vpp               €              8  A   ‡   ˆ   ‰   Š   ‹   Œ   �   Ž   �   �   ‘   ’   “   ”        p      R                  !           ¶bclk            k               2           ã   „      clock-controller@14e00000             mediatek,mt8195-wpesys              à                 þ           ã   $      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0             à                 þ         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1             à0                þ         larb@14e04000             mediatek,mt8195-smi-larb                à@                0           #   •           $      $           ¶apb smi             2           ã   À      larb@14e05000             mediatek,mt8195-smi-larb                àP                0           #   …           $      $      !           ¶apb smi gals                2           ã   ‹      syscon@14f00000           mediatek,mt8195-vppsys1 syscon              ð                 þ           Ø   ‚   	               ã   #      mutex@14f01000            mediatek,mt8195-vpp-mutex               ð                p      {               Ø   ‚   	                 #   '            2         larb@14f02000             mediatek,mt8195-smi-larb                ð                 0           #   •           #      #      !           ¶apb smi gals                2           ã   ¿      larb@14f03000             mediatek,mt8195-smi-larb                ð0                0           #   †           #      #      !           ¶apb smi gals                2           ã   Š      display@14f06000              mediatek,mt8195-mdp3-split              ð`                Ø   ‚   	  `               #      #   +   #   ,            2         display@14f07000              mediatek,mt8195-mdp3-tcc                ðp                Ø   ‚   	  p               #         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma               ð€                Ø   ‚   	  €            ð  „  ¨           #              –                2                    dma-controller@14f09000           mediatek,mt8195-mdp3-rdma               ð�                Ø   ‚   	  �            ð  …  ©           #   
           –   ¤            2                    dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma               ð                 Ø   ‚   	               ð  †  ª           #              „   À            2                    display@14f0b000              mediatek,mt8195-mdp3-fg             ð°                Ø   ‚   	  °               #   	      display@14f0c000              mediatek,mt8195-mdp3-fg             ðÀ                Ø   ‚   	  À               #         display@14f0d000              mediatek,mt8195-mdp3-fg             ðÐ                Ø   ‚   	  Ð               #         display@14f0e000              mediatek,mt8195-mdp3-hdr                ðà                Ø   ‚   	  à               #         display@14f0f000              mediatek,mt8195-mdp3-hdr                ðð                Ø   ‚   	  ð               #         display@14f10000              mediatek,mt8195-mdp3-hdr                ñ                 Ø   ‚   
                  #          display@14f11000              mediatek,mt8195-mdp3-aal                ñ                p      i               Ø   ‚   
                 #               2         display@14f12000              mediatek,mt8195-mdp3-aal                ñ                 p      j               Ø   ‚   
                  #               2         display@14f13000              mediatek,mt8195-mdp3-aal                ñ0                p      k               Ø   ‚   
  0               #   !            2         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ@                Ø   ‚   
  @            ð  �  ¯           #         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñP                Ø   ‚   
  P            ð  ‘  °           #   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ`                Ø   ‚   
  `            ð  ’  ±           #   %      display@14f17000              mediatek,mt8195-mdp3-tdshp              ñp                Ø   ‚   
  p               #         display@14f18000              mediatek,mt8195-mdp3-tdshp              ñ€                Ø   ‚   
  €               #   (      display@14f19000              mediatek,mt8195-mdp3-tdshp              ñ�                Ø   ‚   
  �               #   )      display@14f1a000              mediatek,mt8195-mdp3-merge              ñ                 Ø   ‚   
                  #               2         display@14f1b000              mediatek,mt8195-mdp3-merge              ñ°                Ø   ‚   
  °               #               2         display@14f1c000              mediatek,mt8195-mdp3-color              ñÀ                p      t               Ø   ‚   
  À               #               2         display@14f1d000              mediatek,mt8195-mdp3-color              ñÐ                Ø   ‚   
  Ð            p      u                  #               2         display@14f1e000              mediatek,mt8195-mdp3-color              ñà                p      v               Ø   ‚   
  à               #               2         display@14f1f000              mediatek,mt8195-mdp3-ovl                ñð                p      w               Ø   ‚   
  ð               #                2              –   ¢      display@14f20000              mediatek,mt8195-mdp3-padding                ò                 Ø   ‚                     #               2         display@14f21000              mediatek,mt8195-mdp3-padding                ò                Ø   ‚                    #               2         display@14f22000              mediatek,mt8195-mdp3-padding                ò                 Ø   ‚                     #               2         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò0                Ø   ‚     0            ð  Ÿ  «           #              –   £            2                    dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò@                Ø   ‚     @            ð     ¬           #              –   ¦            2                    dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             òP                Ø   ‚     P            ð  ¡  ­           #              „   Â            2                    clock-controller@15000000             mediatek,mt8195-imgsys                                þ           ã   +      larb@15001000             mediatek,mt8195-smi-larb                                 0   	        #   —           +       +       +   
        ¶apb smi gals                2           ã   Á      smi@15002000              mediatek,mt8195-smi-sub-common                                   +      +      !           ¶apb smi gals0           #   …            2           ã   š      smi@15003000              mediatek,mt8195-smi-sub-common               0                   +       +       +   
        ¶apb smi gals0           #   •            2           ã   —      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                              þ           ã   ˜      larb@15120000             mediatek,mt8195-smi-larb                                 0   
        #   —           +      ˜            ¶apb smi             2           ã   Â      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                               þ         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe             "                 þ           ã   ™      larb@15230000             mediatek,mt8195-smi-larb                #                 0           #   —           +      ™            ¶apb smi             2           ã   Ã      clock-controller@15330000             mediatek,mt8195-ipesys              3                 þ           ã   ,      larb@15340000             mediatek,mt8195-smi-larb                4                 0           #   š           ,      ,           ¶apb smi             2           ã   Œ      clock-controller@16000000             mediatek,mt8195-camsys                                þ           ã   -      larb@16001000             mediatek,mt8195-smi-larb                                 0           #   ›           -       -       -           ¶apb smi gals                2           ã   Ä      larb@16002000             mediatek,mt8195-smi-larb                                  0           #   œ           -      -           ¶apb smi             2           ã   �      smi@16004000              mediatek,mt8195-smi-sub-common               @                   -       -       -           ¶apb smi gals0           #   •            2           ã   ›      smi@16005000              mediatek,mt8195-smi-sub-common               P                   -      -      !           ¶apb smi gals0           #   …            2           ã   œ      larb@16012000             mediatek,mt8195-smi-larb                                 0           #   œ           �       �            ¶apb smi             2            ã   Ž      larb@16013000             mediatek,mt8195-smi-larb                0                0           #   ›           ž       ž            ¶apb smi             2            ã   Å      larb@16014000             mediatek,mt8195-smi-larb                @                0           #   œ           Ÿ       Ÿ            ¶apb smi             2   !        ã   ”      larb@16015000             mediatek,mt8195-smi-larb                P                0           #   ›                                ¶apb smi             2   !        ã   Ê      clock-controller@1604f000             mediatek,mt8195-camsys_rawa             ð                þ           ã   �      clock-controller@1606f000             mediatek,mt8195-camsys_yuva             ð                þ           ã   ž      clock-controller@1608f000             mediatek,mt8195-camsys_rawb             ð                þ           ã   Ÿ      clock-controller@160af000             mediatek,mt8195-camsys_yuvb             
ð                þ           ã          clock-controller@16140000             mediatek,mt8195-camsys_mraw                              þ           ã   ¡      larb@16141000             mediatek,mt8195-smi-larb                                0           #   ›           -       ¡       -           ¶apb smi gals                2   "        ã   É      larb@16142000             mediatek,mt8195-smi-larb                                 0           #   œ           ¡       ¡            ¶apb smi             2   "        ã   “      clock-controller@17200000             mediatek,mt8195-ccusys                                þ           ã   ¢      larb@17201000             mediatek,mt8195-smi-larb                                 0           #   œ           ¢       ¢            ¶apb smi             2           ã   �      video-codec@18000000              mediatek,mt8195-vcodec-dec             ƒ           –                        +                               @                t                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                   „  à   „  á               A   %      %         �        ¶sel vdec lat top            ì      A        ü      �            2         video-codec@10000             mediatek,mtk-vcodec-lat                               p      Ä             0     –      –     –     –     –     –                 A   %      %         �        ¶sel vdec lat top            ì      A        ü      �            2         video-codec@25000             mediatek,mtk-vcodec-core                 P                p      Ã             P     –      –  ¡   –  ¢   –  £   –  ¤   –  ¥   –  ¦   –  §   –  ¨   –  ©               A   &      &         �        ¶sel vdec lat top            ì      A        ü      �            2            larb@1800d000             mediatek,mt8195-smi-larb                 Ð                0           #   •           %       %            ¶apb smi             2           ã   È      larb@1800e000             mediatek,mt8195-smi-larb                 à                0           #   £           !      %            ¶apb smi             2           ã   ’      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc              ð                þ           ã   %      larb@1802e000             mediatek,mt8195-smi-larb                à                0           #   •           &       &            ¶apb smi             2           ã   Ç      clock-controller@1802f000             mediatek,mt8195-vdecsys             ð                þ           ã   &      larb@1803e000             mediatek,mt8195-smi-larb                à                0           #   £           !      '            ¶apb smi             2           ã   ‘      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1               ð                þ           ã   '      clock-controller@190f3000             mediatek,mt8195-apusys_pll              0                þ         clock-controller@1a000000             mediatek,mt8195-vencsys                               þ           ã   (      larb@1a010000             mediatek,mt8195-smi-larb                                 0           #   •           (      (           ¶apb smi             2           ã   Æ      video-codec@1a020000              mediatek,mt8195-vcodec-enc                             H     –  `   –  a   –  b   –  c   –  d   –  v   –  w   –  x   –  y        p      U                  ƒ           (         	  ¶venc_sel            ì      @        ü      �            2                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec              2         0     –  m   –  n   –  r   –  s   –  t   –  u                     +         0  t                                            jpgdec@0,0            mediatek,mt8195-jpgdec-hw                                0     –  m   –  n   –  r   –  s   –  t   –  u        p      W                  (           ¶jpgdec              2         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw                               0     –  m   –  n   –  r   –  s   –  t   –  u        p      X                  (           ¶jpgdec              2         jpgdec@1,0            mediatek,mt8195-jpgdec-hw                               0     „  �   „  Ž   „  ’   „  “   „  ”   „  •        p      \                  )           ¶jpgdec              2            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                 þ           ã   )      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                 ¹   ¤               þ           Ø   ¤                  ã   "   port                         +       endpoint@0                      	O   ¥        ã   ¦            jpeg-encoder@1a030000             mediatek,mt8195-jpgenc              2               „  ‡   „  ˆ   „  ‰   „  Œ                     +         0  t                                            jpgenc@0,0            mediatek,mt8195-jpgenc-hw                                      –  g   –  h   –  i   –  l        p      V                  (           ¶jpgenc              2         jpgenc@1,0            mediatek,mt8195-jpgenc-hw                                     „  ‡   „  ˆ   „  ‰   „  Œ        p      [                  )           ¶jpgenc              2            larb@1b010000             mediatek,mt8195-smi-larb                                 0           #   …           )      )      !            ¶apb smi gals                2           ã   �      ovl@1c000000              mediatek,mt8195-disp-ovl                                  p      |                   2              "               –           Ø   ¤             ports                        +       port@0                 endpoint            	O   ¦        ã   ¥         port@1                endpoint            	O   §        ã   ¨               rdma@1c002000             mediatek,mt8195-disp-rdma                                 p      ~                   2              "              –            Ø   ¤             ports                        +       port@0                 endpoint            	O   ¨        ã   §         port@1                endpoint            	O   ©        ã   ª               color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                0                p                         2              "           Ø   ¤     0       ports                        +       port@0                 endpoint            	O   ª        ã   ©         port@1                endpoint            	O   «        ã   ¬               ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                @                p      €                   2              "           Ø   ¤     @       ports                        +       port@0                 endpoint            	O   ¬        ã   «         port@1                endpoint            	O   ­        ã   ®               aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                P                p      �                   2              "           Ø   ¤     P       ports                        +       port@0                 endpoint            	O   ®        ã   ­         port@1                endpoint            	O   ¯        ã   °               gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                `                p      ‚                   2              "           Ø   ¤     `       ports                        +       port@0                 endpoint            	O   °        ã   ¯         port@1                endpoint            	O   ±        ã   ²               dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither              p                p      ƒ                   2              "   	        Ø   ¤     p       ports                        +       port@0                 endpoint            	O   ²        ã   ±         port@1                endpoint            	O   ³        ã   º               dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi              €                p      „                   2              "      "   *   ´        ¶engine digital hs           	   ´        
ƒdphy            €okay                         +       panel@0       #    startek,kd070fhfid078 himax,hx8279                      P   µ        Z      0            X      l            g   ¶        R   ·        ¶default         Ä   ¸   port       endpoint            	O   ¹        ã   »            ports                        +       port@0                 endpoint            	O   º        ã   ³         port@1                endpoint            	O   »        ã   ¹               dsc@1c009000              mediatek,mt8195-disp-dsc                 �                p      …                   2              "           Ø   ¤     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              p      Ž                   2              "      "   +   ¼        ¶engine digital hs           	   ¼        
ƒdphy          	  €disabled          merge@1c014000            mediatek,mt8195-disp-merge              @                p      �                   2              "           Ø   ¤     @          dp-intf@1c015000              mediatek,mt8195-dp-intf             P                p      ‘                   2              "   ,   "                 ¶pixel engine pll          	  €disabled          mutex@1c016000            mediatek,mt8195-disp-mutex              `                p      ’                   2              "           Ø   ¤     `            ð  U      larb@1c018000             mediatek,mt8195-smi-larb                €                0            #   •           "   (   "   (   !           ¶apb smi gals                2           ã   ½      larb@1c019000             mediatek,mt8195-smi-larb                �                0           #   …           "   (   !       !           ¶apb smi gals                2           ã   ‡      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                               ¹   ¤              Ø   ¤                  þ           Ì           ã   *      smi@1c01b000              mediatek,mt8195-smi-common-vdo              °                    "   %   "   &   "   )   "   $        ¶apb smi gals0 gals1             2           ã   •      iommu@1c01f000            mediatek,mt8195-iommu-vdo               ð              8  A   ½   ¾   ¿   À   Á   Â   Ã   Ä   Å   Æ   Ç   È   É   Ê        p      �               k              "   '        ¶bclk                2           ã   –      mutex@1c101000            mediatek,mt8195-disp-mutex                              p      î                   2              *           Ø   ¤                 ð  À      larb@1c102000             mediatek,mt8195-smi-larb                                 0           #   •           *       *       *           ¶apb smi gals                2           ã   ¾      larb@1c103000             mediatek,mt8195-smi-larb                0                0           #   …           *      *      !            ¶apb smi gals                2           ã   ˆ      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma               @                p      ï                  *               2              –   @        Ø   ¤     @                     dma-controller@1c105000           mediatek,mt8195-vdo1-rdma               P                p      ð                  *               2              „   `        Ø   ¤     P                     dma-controller@1c106000           mediatek,mt8195-vdo1-rdma               `                p      ñ                  *               2              –   A        Ø   ¤     `                     dma-controller@1c107000           mediatek,mt8195-vdo1-rdma               p                p      ò                  *               2              „   a        Ø   ¤     p                     dma-controller@1c108000           mediatek,mt8195-vdo1-rdma               €                p      ó                  *               2              –   B        Ø   ¤     €                     dma-controller@1c109000           mediatek,mt8195-vdo1-rdma               �                p      ô                  *               2              „   b        Ø   ¤     �                     dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma                                p      õ                  *               2              –   C        Ø   ¤                           dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma               °                p      ö                  *               2              „   c        Ø   ¤     °                     vpp-merge@1c10c000            mediatek,mt8195-disp-merge              À                p      ÷                  *   	   *           ¶merge merge_async               2           Ø   ¤     À             t        Ò   *         vpp-merge@1c10d000            mediatek,mt8195-disp-merge              Ð                p      ø                  *   
   *           ¶merge merge_async               2           Ø   ¤     Ð             t        Ò   *         vpp-merge@1c10e000            mediatek,mt8195-disp-merge              à                p      ù                  *      *           ¶merge merge_async               2           Ø   ¤     à             t        Ò   *         vpp-merge@1c10f000            mediatek,mt8195-disp-merge              ð                p      ú                  *      *           ¶merge merge_async               2           Ø   ¤     ð             t        Ò   *         vpp-merge@1c110000            mediatek,mt8195-disp-merge                               p      û                  *      *           ¶merge merge_async               2           Ø   ¤                   ˆ        Ò   *         dp-intf@1c113000              mediatek,mt8195-dp-intf             0                p                         2              *   /   *                 ¶pixel engine pll          	  €disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p      @            P            p            �                         °            À              4  Ùmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  Ø   ¤     @       ¤     P       ¤     p       ¤     �       ¤             ¤     °       ¤     À          h     *   %   *       *   #   *   !   *   $   *   "   *   1   *   &   *   '   *   (   *   )   *   *            ƒ  ¶mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top              2              „   d   „   e        p                   (  Ò   *   3   *   4   *   5   *   6   *   7      E  Ùvdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx              P        €         å   Ë        ñdp_calibration_data             2           p      ¤               Ÿ  ¤      	  €disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx               `        €         å   Ë        ñdp_calibration_data             2           p      Ê               Ÿ  ¤      	  €disabled             thermal-zones      cpu0-thermal            °  è        ¾   ú        Ô   Ì      trips      trip-alert          ä L        ð  Ð        passive         ã   Í      trip-crit           ä †         ð  Ð      	  critical             cooling-maps       map0            û   Í      0      ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            °  è        ¾   ú        Ô   Ì      trips      trip-alert          ä L        ð  Ð        passive         ã   Î      trip-crit           ä †         ð  Ð      	  critical             cooling-maps       map0            û   Î      0      ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            °  è        ¾   ú        Ô   Ì      trips      trip-alert          ä L        ð  Ð        passive         ã   Ï      trip-crit           ä †         ð  Ð      	  critical             cooling-maps       map0            û   Ï      0      ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            °  è        ¾   ú        Ô   Ì      trips      trip-alert          ä L        ð  Ð        passive         ã   Ð      trip-crit           ä †         ð  Ð      	  critical             cooling-maps       map0            û   Ð      0      ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            °  è        ¾   ú        Ô   Ì       trips      trip-alert          ä L        ð  Ð        passive         ã   Ñ      trip-crit           ä †         ð  Ð      	  critical             cooling-maps       map0            û   Ñ      0      ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            °  è        ¾   ú        Ô   Ì      trips      trip-alert          ä L        ð  Ð        passive         ã   Ò      trip-crit           ä †         ð  Ð      	  critical             cooling-maps       map0            û   Ò      0      ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            °  è        ¾   ú        Ô   Ì      trips      trip-alert          ä L        ð  Ð        passive         ã   Ó      trip-crit           ä †         ð  Ð      	  critical             cooling-maps       map0            û   Ó      0      ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            °  è        ¾   ú        Ô   Ì      trips      trip-alert          ä L        ð  Ð        passive         ã   Ô      trip-crit           ä †         ð  Ð      	  critical             cooling-maps       map0            û   Ô      0      ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            °  è        ¾   ú        Ô   Õ      trips      trip-alert          ä L        ð  Ð        passive       trip-crit           ä †         ð  Ð      	  critical                vpu1-thermal            °  è        ¾   ú        Ô   Õ   	   trips      trip-alert          ä L        ð  Ð        passive       trip-crit           ä †         ð  Ð      	  critical                gpu-thermal         °  è        ¾   ú        Ô   Õ   
   trips      trip-alert          ä L        ð  Ð        passive       trip-crit           ä †         ð  Ð      	  critical                gpu1-thermal            °  è        ¾   ú        Ô   Õ      trips      trip-alert          ä L        ð  Ð        passive       trip-crit           ä †         ð  Ð      	  critical                vdec-thermal            °  è        ¾   ú        Ô   Õ      trips      trip-alert          ä L        ð  Ð        passive       trip-crit           ä †         ð  Ð      	  critical                img-thermal         °  è        ¾   ú        Ô   Õ      trips      trip-alert          ä L        ð  Ð        passive       trip-crit           ä †         ð  Ð      	  critical                infra-thermal           °  è        ¾   ú        Ô   Õ      trips      trip-alert          ä L        ð  Ð        passive       trip-crit           ä †         ð  Ð      	  critical                cam0-thermal            °  è        ¾   ú        Ô   Õ      trips      trip-alert          ä L        ð  Ð        passive       trip-crit           ä †         ð  Ð      	  critical                cam1-thermal            °  è        ¾   ú        Ô   Õ      trips      trip-alert          ä L        ð  Ð        passive       trip-crit           ä †         ð  Ð      	  critical                   chosen          serial0:921600n8          firmware       optee             linaro,optee-tz         smc          memory@40000000          ûmemory              @                reserved-memory                      +            t   optee@43200000                       C        À        memory@50000000           shared-dma-pool             P       �                   ã   0      memory@53000000           shared-dma-pool             S       @        memory@54600000                      T`                memory@60000000           shared-dma-pool             `        ð                   ã   6      memory@60f00000           shared-dma-pool             `ð                          ã   8      memory@61000000           shared-dma-pool             a                           ã   5      memory@62000000           shared-dma-pool             b       @           backlight-lcm0            pwm-backlight           "      ÿ        4  @        M  ÿ        d   Ö     ¡         ã   µ      backlight-lcd1            pwm-backlight           d   ×     ¡         Z      .            "      ÿ        M  ÿ        4  @      	  €disabled          can-clk           fixed-clock         þ            -1-         'can-clk         ã   @      regulator-0           regulator-fixed         †edp_panel_3v3           • 2Z         ­ 2Z          i                          ¶default         Ä   Ø      regulator-1           regulator-fixed         †edp_backlight_12v           • ·         ­ ·          i              `            ¶default         Ä   Ù      gpio-keys         
    gpio-keys      button-volume-up             ]        |   d        :      j         
  
çvolume_up           Ž   s         regulator-vio18-lcm0              regulator-fixed         †vio18_lcm0           i              /            ¶default         Ä   Ú        ™   Û        ã   ¶      regulator-vsys-lcm0           regulator-fixed       
  †vsys_lcm0            á         ¤        ™   n        ã   ·      regulator-2           regulator-fixed       	  †wifi_3v3            • 2Z         ­ 2Z               ‡             i         á         	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 ethernet0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform pinctrl-names pinctrl-0 audio-routing mediatek,adsp link-name sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux output-high drive-strength input-enable input-disable bias-disable bias-pull-up drive-strength-microamp bias-pull-down output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells mediatek,mic-type-0 mediatek,mic-type-1 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes mediatek,long-press-mode power-off-time-sec linux,keycodes wakeup-source #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select cs-gpios spi-max-frequency vdd-supply xceiver-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us mediatek,tx-delay-ps mediatek,mac-wol pinctrl-1 snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup dr_mode usb-role-switch vusb33-supply remote-endpoint bus-width cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc freq-table-hz mediatek,ufs-disable-mcq vcc-supply vccq2-supply bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply label data-role op-sink-microwatt power-role try-power-role source-pdos sink-pdos pd-revision svid vdo irq-gpios reset-gpios AVDD28-supply mode-switch orientation-switch mediatek,force-mode operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs backlight enable-gpios iovcc-supply mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path no-map brightness-levels default-brightness-level num-interpolated-steps pwms enable-active-high debounce-interval linux,code vin-supply regulator-boot-on 