Ðþí d1   8 X   (             WÜ                             6    kontron,3-5-sbc-i1200 mediatek,mt8395 mediatek,mt8195                                    +            7Kontron 3.5"-SBC-i1200     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          ƒ/soc/vpp-merge@1c10f000          Š/soc/vpp-merge@1c110000          ‘/soc/dma-controller@1c104000             œ/soc/dma-controller@1c105000             §/soc/dma-controller@1c106000             ²/soc/dma-controller@1c107000             ½/soc/dma-controller@1c108000             È/soc/dma-controller@1c109000             Ó/soc/dma-controller@1c10a000             Þ/soc/dma-controller@1c10b000             é/soc/mmc@11230000            î/soc/mmc@11240000            ó/soc/serial@11001200             û/soc/serial@11001300            /soc/serial@11001400            /soc/serial@11001500            /soc/serial@11001100          cpus                         +       cpu@0           cpu           arm,cortex-a55          '            +psci            9               Mec3@        ]  4        p              €  €         �   @        Ÿ   €        ¬  €         ¹   @        Ë   €        Ø           é           ø   	      cpu@100         cpu           arm,cortex-a55          '           +psci            9               Mec3@        ]  4        p              €  €         �   @        Ÿ   €        ¬  €         ¹   @        Ë   €        Ø           é           ø   
      cpu@200         cpu           arm,cortex-a55          '           +psci            9               Mec3@        ]  4        p              €  €         �   @        Ÿ   €        ¬  €         ¹   @        Ë   €        Ø           é           ø         cpu@300         cpu           arm,cortex-a55          '           +psci            9               Mec3@        ]  4        p              €  €         �   @        Ÿ   €        ¬  €         ¹   @        Ë   €        Ø           é           ø         cpu@400         cpu           arm,cortex-a78          '           +psci            9              M�fÔÀ        ]           p              €           �   @        Ÿ           ¬           ¹   @        Ë           Ø           é           ø         cpu@500         cpu           arm,cortex-a78          '           +psci            9              M�fÔÀ        ]           p              €           �   @        Ÿ           ¬           ¹   @        Ë           Ø           é           ø         cpu@600         cpu           arm,cortex-a78          '           +psci            9              M�fÔÀ        ]           p              €           �   @        Ÿ           ¬           ¹   @        Ë           Ø           é           ø         cpu@700         cpu           arm,cortex-a78          '           +psci            9              M�fÔÀ        ]           p              €           �   @        Ÿ           ¬           ¹   @        Ë           Ø           é           ø         cpu-map    cluster0       core0               	      core1               
      core2                     core3                     core4                     core5                     core6                     core7                           idle-states         psci       cpu-retention-l           arm,idle-state                     (        9   2        J   _        Z  D        ø         cpu-retention-b           arm,idle-state                     (        9   -        J   Œ        Z  ä        ø         cpu-off-l             arm,idle-state                    (        9   7        J   ›        Z  H        ø         cpu-off-b             arm,idle-state                    (        9   2        J   È        Z  è        ø            l2-cache0             cache           k           ‚           �   @        ¡           Ø            w        ø         l2-cache1             cache           k           ‚           �   @        ¡           Ø            w        ø         l3-cache              cache           k           ‚            �   @        ¡            w        ø            dsu-pmu           arm,dsu-pmu         …                       �   	   
                          •fail          dmic-codec            dmic-codec          œ           ©   2      mt8195-sound            ¹         	  •disabled          fixed-factor-clock-13m            fixed-factor-clock          Ë            Ø           ß           é           ôclk13m          ø   (      oscillator-26m            fixed-clock         Ë            MŒº€        ôclk26m          ø         oscillator-32k            fixed-clock         Ë            M  €         ôclk32k        performance-controller@11bc10             mediatek,cpufreq-hw          '     ¼            ½0                          ø         opp-table-gpu             operating-points-v2          !        ø   n   opp-390000000           ,    >í€        3 	‰h      opp-410000000           ,    p€        3 	¡Ò      opp-431000000           ,    °‰À        3 	¡Ò      opp-473000000           ,    1h@        3 	º<      opp-515000000           ,    ²FÀ        3 	º<      opp-556000000           ,    !#ã         3 	Ò¦      opp-598000000           ,    #¤Á€        3 	ë      opp-640000000           ,    &%          3 	ë      opp-670000000           ,    'ïc€        3 
ä      opp-700000000           ,    )¹'         3 
L¸      opp-730000000           ,    +‚ê€        3 
}Œ      opp-760000000           ,    -L®         3 
®`      opp-790000000           ,    /q€        3 
ß4      opp-820000000           ,    0à5         3       opp-850000000           ,    2©ø€        3 @Ü      opp-880000000           ,    4s¼         3 q°         pmu-a55           arm,cortex-a55-pmu                      …                  pmu-a78           arm,cortex-a78-pmu                      …                  psci              arm,psci-1.0            2smc       timer             arm,armv8-timer                   @  …                                             
             soc                      +             simple-bus           A        H                          interrupt-controller@c000000              arm,gic-v3          S           d                        {         '                                    …      	               ø      ppi-partitions     interrupt-partition-0           �   	   
              ø         interrupt-partition-1           �                    ø               syscon@10000000            mediatek,mt8195-topckgen syscon         '                      Ë           ø         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          '                     Ë           ™           ø         syscon@10003000           mediatek,mt8195-pericfg syscon          '     0                Ë           ø   A      pinctrl@10005000              mediatek,mt8195-pinctrl       €  '     P            Ñ             Ó             Ô             â             ë             ô              °              B  ¦iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            °        À           Ì              �         {        …       ë               S           ø      eth-default-pins            ø   =   pins-txd            Ø  M  N  O  P        ß         pins-rxd            Ø  Q  R  S  T      pins-cc         Ø  U  V  W  X        ß         pins-mdio           Ø  Y  Z         î      pins-power          Ø  [   \          û      pins-reset          Ø  ]          û      pins-interrupt          Ø  ^          î         eth-sleep-pins          ø   >   pins-txd            Ø  M   N   O   P       pins-cc         Ø  U   X   W   V       pins-rxd            Ø  Q   R   S   T       pins-mdio           Ø  Y   Z                            gpio-keys-pins          ø   ½   pins            Ø  j          î         i2c0-pins           ø   [   pins            Ø    	        "   Ï        /  è         i2c1-pins           ø   \   pins            Ø  
          "   Ï        /  è         i2c2-default-pins           ø   ]   pins-bus            Ø            "   Ï        /  è         i2c3-pins           ø   ^   pins            Ø            "   Ï        /  è         i2c4-pins           ø   _   pins            Ø            "   Ï        /  è         i2c6-pins           ø   X   pins            Ø             "        /  è         mmc0-default-pins           ø   C   pins-clk            Ø  z        ß           G   f      pins-cmd-dat          $  Ø  ~  }  |  {  w  v  u  t  y         î        ß           "   e      pins-rst            Ø  x        ß           "   e         mmc0-uhs-pins           ø   D   pins-clk            Ø  z        ß           G   f      pins-cmd-dat          $  Ø  ~  }  |  {  w  v  u  t  y         î        ß           "   e      pins-ds         Ø          ß           G   f      pins-rst            Ø  x        ß           "   e         mmc1-default-pins           ø   G   pins-clk            Ø  o        ß           G   f      pins-cmd-dat            Ø  n  p  q  r  s         î        ß           "   e         mmc1-detect-pins            ø   H   pins-insert         Ø  �          "         nor-default-pins            ø   V   pins-ck-io          Ø  Ž  �  �        ß            G      pins-cs         Ø  Œ        ß            "         pcie0-default-pins          ø   R   pins-bus            Ø               "         pcie1-default-pins          ø   U   pins-bus            Ø               "   e         led-pins            ø   ¾   pins-power-en           Ø  k          û         spi0-default-pins           ø   4   pins-cs-mosi-clk            Ø  „  †  …               pins-miso           Ø  ‡         G         spi1-default-pins           ø   8   pins-cs-mosi-clk            Ø  ˆ  Š  ‰               pins-miso           Ø  ‹         G         uart0-pins          ø   /   pins-rx         Ø  c         î         "      pins-tx         Ø  b         uart1-pins          ø   0   pins-rx         Ø  g         î         "      pins-tx         Ø  f      pins-rts            Ø  d      pins-cts            Ø  e         î         uart2-pins          ø   1   pins-rx         Ø  D         î         "      pins-tx         Ø  C      pins-rts            Ø  B      pins-cts            Ø  A         î         uart3-pins          ø   2   pins-rx         Ø           î        "   e      pins-tx         Ø           uart4-pins          ø   3   pins-rx         Ø           î         "      pins-tx         Ø              syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            '     `           power-controller          !    mediatek,mt8195-power-controller                         +            V           ø   +   power-domain@8          '                        +            V      power-domain@9          '   	        Ø                    jmfg alt         v                        +            V      power-domain@10         '   
        V          power-domain@11         '           V          power-domain@12         '           V          power-domain@13         '           V          power-domain@14         '           V                power-domain@15         '         Ø  Ø                        	      @      A      K      à                                                                                                                          jvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           v                        +            V      power-domain@16         '         8  Ø      â      $      %      &      '      (      )      D  jvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         v                        +            V      power-domain@17         '           Ø      á                    jvppsys1 vppsys1-0 vppsys1-1         v           V          power-domain@22         '            Ø                              $  jwepsys-0 wepsys-1 wepsys-2 wepsys-3         v           V          power-domain@23         '           Ø               jvdec0-0         v                        +            V       power-domain@24         '           Ø               jvdec1-0         v           V          power-domain@25         '           Ø                jvdec2-0         v           V             power-domain@26         '           Ø   !            jvenc0-larb          v                        +            V       power-domain@27         '           Ø   "            jvenc1-larb          v           V             power-domain@18         '            Ø      ã   #       #      #         &  jvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           v                        +            V      power-domain@19         '           v           V          power-domain@20         '           v           V          power-domain@21         '           Ø      Q        jhdmi_tx         V             power-domain@28         '           Ø   $       $   
        jimg-0 img-1         v                        +            V      power-domain@29         '           V          power-domain@30         '           Ø         $      %           jipe ipe-0 ipe-1         v           V             power-domain@31         '         (  Ø   &       &      &      &      &           jcam-0 cam-1 cam-2 cam-3 cam-4           v                        +            V      power-domain@32         '            V          power-domain@33         '   !        V          power-domain@34         '   "        V                   power-domain@0          '            v           V          power-domain@1          '           v           V          power-domain@2          '           V          power-domain@3          '           V          power-domain@4          '           Ø      5      7        jcsi_rx_top csi_rx_top1          V          power-domain@5          '           Ø   '           jether           V          power-domain@6          '           Ø      X      n        jadsp adsp1                       +            v           V      power-domain@7          '            Ø      g      "      n      2        jaudio audio1 audio2 audio3          v           V                   watchdog@10007000             mediatek,mt8195-wdt          ˆ        '     p                ™           ø   .      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           '     À                Ë           ø         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         '    p                …      	               Ø   (      pwrap@10024000            mediatek,mt8195-pwrap syscon            '    @                ¦pwrap           …       ó               Ø                   	  jspi wrap                   $        °      Ë   pmic              mediatek,mt6359          {        S           Ç           Ø      Þ      adc           mediatek,mt6359-auxadc          ì         audio-codec           mediatek,mt6359-codec         regulators            mediatek,mt6359-regulator      buck_vs1            þvs1          5         % !‘À        =             Y      buck_vgpu11         þvgpu11           €        % 7        m  ˆ        =   È        ‚                   Y      buck_vmodem         þvmodem           €        % Èà        m  *        =   È      buck_vpu            þvpu          €        % 7        m  ˆ        =   È        ‚                   Y      buck_vcore          þvcore            €        % Ö         m  ˆ        =   È        ‚                   Y      buck_vs2            þvs2          5         % j         =             Y      buck_vpa            þvpa          ¡         % 7±Ð        =  ,      buck_vproc2         þvproc2           €        % 7        m  L        =   È        ‚                   Y      buck_vproc1         þvproc1           €        % 7        m  L        =   È        ‚                   Y      buck_vcore_sshub            þvcore_sshub          €        % 7      buck_vgpu11_sshub           þvgpu11_sshub             €        % 7      ldo_vaud18          þvaud18           w@        % w@        =   ð      ldo_vsim1           þvsim1            ð         % /M`      ldo_vibr            þvibr             O€        % 2Z       ldo_vrf12           þvrf12            Èà        % Ö          Y      ldo_vusb            þvusb             -ÆÀ        % -ÆÀ        =  À         Y        ø   B      ldo_vsram_proc2         þvsram_proc2          ¡         % ½¶        m  L        =   ð         Y      ldo_vio18           þvio18            ð         % ýà        =  À         Y      ldo_vcamio          þvcamio           ð         % ýà      ldo_vcn18           þvcn18            w@        % w@        =   ð      ldo_vfe28           þvfe28            *¹€        % *¹€        =   x      ldo_vcn13           þvcn13            »         % Ö       ldo_vcn33_1_bt          þvcn33_1_bt           *¹€        % 5gà      ldo_vcn33_1_wifi            þvcn33_1_wifi             *¹€        % 5gà      ldo_vaux18          þvaux18           w@        % w@        =   ð         Y      ldo_vsram_others            þvsram_others             ¡         % ½¶        m  ˆ        =   ð         Y      ldo_vefuse          þvefuse           ð         % „€      ldo_vxo22           þvxo22            w@        % !‘À         Y      ldo_vrfck           þvrfck            ã`        % ð       ldo_vrfck_1         þvrfck            ëÀ        % j       ldo_vbif28          þvbif28           *¹€        % *¹€        =   ð      ldo_vio28           þvio28            *¹€        % 2Z          Y      ldo_vemc            þvemc             ,@         % 2Z       ldo_vemc_1          þvemc             &%         % 2Z         ø   E      ldo_vcn33_2_bt          þvcn33_2_bt           *¹€        % 5gà      ldo_vcn33_2_wifi            þvcn33_2_wifi             *¹€        % 5gà      ldo_va12            þva12             O€        % Ö          Y      ldo_va09            þva09             5         % O€      ldo_vrf18           þvrf18            ð         % žP      ldo_vsram_md          	  þvsram_md             ¡         % ½¶        m  *        =   ð         Y      ldo_vufs            þvufs             ð         % ýà        ø   F      ldo_vm18            þvm18             ð         % ýà         Y      ldo_vbbck           þvbbck            Èà        % O€         Y      ldo_vsram_proc1         þvsram_proc1          ¡         % ½¶        m  L        =   ð         Y      ldo_vsim2           þvsim2            ð         % /M`      ldo_vsram_others_sshub          þvsram_others_sshub           ¡         % ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             '    p            �                ¦pmif spmimst            Ø                   E      (  jpmif_sys_ck pmif_tmr_ck spmimst_clk_mux                $        °      Ë                     +       mt6315@6              mediatek,mt6315-regulator           '          regulators     vbuck1          þVbcpu            “à        % 7        =           m  j        ‚                   Y            mt6315@7              mediatek,mt6315-regulator           '          regulators     vbuck1          þVgpu             	‰h        % 7        =           m  j        ‚                   Y        ø   o               infra-iommu@10315000              mediatek,mt8195-iommu-infra         '    1P       P       P  …                                                                         š           ø   O      mailbox@10320000              mediatek,mt8195-gce         '    2        @         …       â               §           Ø              ø   ’      mailbox@10330000              mediatek,mt8195-gce         '    3        @         …       ä               §           Ø              ø   p      scp@10500000              mediatek,mt8195-scp       0  '    P             r             p        €         ¦sram cfg l1tcm          …      Î               •okay            ³   )        Ámediatek/mt8195/scp.img         ø   q      clock-controller@10720000             mediatek,mt8195-scp_adsp            '    r                 Ë           ø   *      dsp@10803000              mediatek,mt8195-dsp          '    €0            „               	  ¦cfg sram          ,  Ø      X         n      Š   *          #      K  jadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          Ï   +           Ýrx tx           è   ,   -      	  •disabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           §            '    �`                …      ¾               ø   ,      mailbox@10817000              mediatek,mt8195-adsp-mbox           §            '    �p                …      ¿               ø   -      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           '    ‰                 ï           Ï   +           …      6                  .         	  audiosys          ”  Ø                     Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d      2   *          ó  jclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  •disabled            ø         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …       �               Ø               	  jbaud bus            •okay            default         "   /      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …       Ž               Ø               	  jbaud bus            •okay            default         "   0         ,      serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …       �               Ø               	  jbaud bus            •okay            default         "   1         ,      serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …      Ó               Ø               	  jbaud bus            •okay            default         "   2      serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …      Ô               Ø               	  jbaud bus            •okay            default         "   3      serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …      Õ               Ø               	  jbaud bus          	  •disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           '                      Ø              jmain            ì           •okay            ø   ¿      syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           '     0                Ë           ø   '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '                      …       ¿               Ø      ™                    jparent-clk sel-clk spi-clk          •okay            default         "   4        <       tpm@0         !    infineon,slb9670 tcg,tpm_tis-spi            '            PI          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         '     °                …       ©               Ø                             b   5   6      $  nlvts-calib-data-1 lvts-calib-data-2                    ø   ¹      svs@1100bc00              mediatek,mt8195-svs         '     ¼                …       Ç               Ø              jmain            b   7   5      (  nsvs-calibration-data t-calibration-data                       svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           '     à                …       Ë               Ï   +           •           Ø      *      0        jmain mm       	  •disabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           '     ð                …                     •           Ø      +      N        jmain mm       	  •disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '                     …       À               Ø      ™            3        jparent-clk sel-clk spi-clk          •okay            default         "   8        <          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '                     …       Á               Ø      ™            4        jparent-clk sel-clk spi-clk        	  •disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '    0                …       Â               Ø      ™            5        jparent-clk sel-clk spi-clk        	  •disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '    €                …       Ã               Ø      ™            <        jparent-clk sel-clk spi-clk        	  •disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '    �                …       Ä               Ø      ™            =        jparent-clk sel-clk spi-clk        	  •disabled          spi@1101d000              mediatek,mt8195-spi-slave           '    Ð                …       Å               Ø      R        jspi                        °      ˜      	  •disabled          spi@1101e000              mediatek,mt8195-spi-slave           '    à                …       Æ               Ø      S        jspi                        °      ˜      	  •disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           '           @         …      Ì                macirq        .  jaxi apb mac_main ptp_ref rmii_internal mac_cg         0  Ø   '       '         R      S      T   '                  R      S      T        °      Â      Ã      Ä        Ï   +           °           Á   9        Ñ   :        ä   ;        ÷                                  •okay          	  rgmii-id            #   <        default sleep           "   =        .   >         8   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916            '           Ø      ^           I  '        Y 8€        k      ]            ø   <         stmmac-axi-config           w           ‡           —                                 ø   9      rx-queues-config            ¡            ·        ø   :   queue0           È        Û          queue1           È        Û          queue2           È        Û          queue3           È        Û             tx-queues-config            ó            	        ø   ;   queue0                      È        '          queue1                      È        '         queue2                      È        '         queue3                      È        '               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           '            -ÿ     >              	  ¦mac ippc            A                     ?                      +           …       €               Ø      /      í      B        jsys_ck ref_ck mcu_ck            5   ?      @            :        H   A      g        •okay            _host            g   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          '                       ¦mac         …       �                      ,      -        °      –      –      $  Ø      /      í               B      $  jsys_ck ref_ck mcu_ck dma_ck xhci_ck         •okay             mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          '    #             õ                 …       ƒ               Ø                          jsource hclk source_cg           •okay            default state_uhs           "   C        .   D        u           TëÂ          L         Ž                   ±         À         Ï         ×         Ý        ë   E        ÷   F      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          '    $             Ç                 …       ‡               Ø                  $        jsource hclk source_cg                          °      ¿        •okay            default state_uhs           "   G   H        .   G        	      �           u           TëÂ          	         	         	+         	9        ë   I        ÷   J      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          '    %             æ                 …       ˆ               Ø                   I        jsource hclk source_cg                           °      ¿      	  •disabled          ufshci@11270000           mediatek,mt8195-ufshci          '    '        #         …       ‰               5   K      @  Ø      ?      @      A      6      7      8      Z      ]      X  jufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  	@                                                                         	N      	  •disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            '    '€                …       ª               Ø                            b   5   6      $  nlvts-calib-data-1 lvts-calib-data-2                    ø   °      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           '    )             )>              	  ¦mac ippc            …                     5   L                  .      /        °      –      –      $  Ø   '         ï            '         $  jsys_ck ref_ck mcu_ck dma_ck xhci_ck         H   A      h         :        •okay            g   B        	g         usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           '    *       -ÿ    *>              	  ¦mac ippc            A            *        ?                      +           …                            0        °      –        Ø   '         ñ   '           jsys_ck ref_ck mcu_ck            5   M            :        H   A      i        •okay            g   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          '                       ¦mac         …                            1        °      –        Ø   '           jsys_ck          •okay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           '    +       -ÿ    +>              	  ¦mac ippc            A            +        ?                      +           …                            2        °      –        Ø   '         ó   '   	        jsys_ck ref_ck mcu_ck            5   N            :        H   A      j        •okay            g   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          '                       ¦mac         …                            3        °      –        Ø   '   	        jsys_ck          •okay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +           '    /        @       	  ¦pcie-mac            …                     	|       ÿ      8  A�                           ‚                       à          	†       O              	�          0  Ø      V      #      &      +      K   '         /  jpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                 G        °              5   P      	  	Ÿpcie-phy            Ï   +            S           	©                     `  	¼                  Q                      Q                     Q                     Q           •okay            default         "   R   interrupt-controller             {                     S           ø   Q         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +           '    /€       @       	  ¦pcie-mac            …                     	|       ÿ      8  A�       $       $           ‚       $       $       à          	†       O              	�          (  Ø      W         X         Q   '         /  jpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                 H        °              5   S         	  	Ÿpcie-phy            Ï   +           S           	©                     `  	¼                  T                      T                     T                     T           •okay            default         "   U   interrupt-controller             {                     S           ø   T         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         '    2À                …      9               Ø      o   '      '           jspi sf axi                       +            •okay            default         "   V   flash@0           jedec,spi-nor           '            Pu         	Ê           	Û            efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            '    Á                              +      usb3-tx-imp@184,1           '  „           	ì               ø   e      usb3-rx-imp@184,2           '  „           	ì              ø   d      usb3-intr@185           '  …           	ì              ø   c      usb3-tx-imp@186,1           '  †           	ì               ø   b      usb3-rx-imp@186,2           '  †           	ì              ø   a      usb3-intr@187           '  ‡           	ì              ø   `      usb2-intr-p0@188,1          '  ˆ           	ì             usb2-intr-p1@188,2          '  ˆ           	ì            usb2-intr-p2@189,1          '  ‰           	ì            usb2-intr-p3@189,2          '  ‰           	ì            pciephy-rx-ln1@190,1            '  �           	ì               ø   l      pciephy-tx-ln1-nmos@190,2           '  �           	ì              ø   k      pciephy-tx-ln1-pmos@191,1           '  ‘           	ì               ø   j      pciephy-rx-ln0@191,2            '  ‘           	ì              ø   i      pciephy-tx-ln0-nmos@192,1           '  ’           	ì               ø   h      pciephy-tx-ln0-pmos@192,2           '  ’           	ì              ø   g      pciephy-glb-intr@193            '  “           	ì               ø   f      dp-data@1ac         '  ¬           ø   ¯      lvts1-calib@1bc         '  ¼           ø   5      lvts2-calib@1d0         '  Ð   8        ø   6      svs-calib@580           '  €   d        ø   7      socinfo-data1@7a0           '               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A        Ä             •okay       usb-phy@0           '               Ø      ò        jref         	ñ           ø   M         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A        Å             •okay       usb-phy@0           '               Ø      ô        jref         	ñ           ø   N         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         '    È                 Ø           ômipi_tx0_pll            Ë            	ñ          	  •disabled            ø   Ÿ      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         '    É                 Ø           ômipi_tx1_pll            Ë            	ñ          	  •disabled            ø          i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    Ð             "€       €        …       š               ß           Ø   W          ;      	  jmain dma                         +          	  •disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    Ð            "        €        …       ›               ß           Ø   W         ;      	  jmain dma                         +            •okay            M €        "   X        default    pmic@34           mediatek,mt6360         '   4         {        Ø      e            IRQB            S      regulator             mediatek,mt6360-regulator           	ü   Y        
   Y        
   Y   buck1         	  þemi_vdd2             	'À        % w@        ‚                   Y      buck2         	  þemi_vddq             “à        % Ö         ‚                   Y      ldo1            þmt6360_ldo1          O€        % 6î€        ‚             ldo2            þpanel1_p1v8          w@        % w@        ‚             ldo3            þvmc_pmu          w@        % 2Z         ‚               ø   J      ldo5          	  þvmch_pmu             2Z         % 2Z         ‚               ø   I      ldo6            þmt6360_ldo6          ¡         %           ‚             ldo7            þemi_vmddr_en             w@        % w@        ‚                Y               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    Ð             "€       €        …       œ               ß           Ø   W         ;      	  jmain dma                         +          	  •disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          '    Ð0                Ë           ø   W      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    à             " €       €        …       �               ß           Ø   Z          ;      	  jmain dma                         +            •okay            default         "   [        M †       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    à            "        €        …       “               ß           Ø   Z         ;      	  jmain dma                         +            •okay            default         "   \        M †       i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    à             "€       €        …       –               ß           Ø   Z         ;      	  jmain dma                         +            •okay            default         "   ]        M €      i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    à0            "€       €        …       ˜               ß           Ø   Z         ;      	  jmain dma                         +            •okay            default         "   ^        M †       i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    à@            "        €        …       ™               ß           Ø   Z         ;      	  jmain dma                         +            •okay            M †         "   _        default       clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          '    àP                Ë           ø   Z      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A        ã             Ï   +           •okay       usb-phy@0           '               Ø      ð           jref da_ref          	ñ           ø   L      usb-phy@700         '              Ø            ð        jref da_ref          b   `   a   b        nintr rx_imp tx_imp          	ñ           ø   S         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A        ä             •okay       usb-phy@0           '               Ø      î           jref da_ref          	ñ           ø   ?      usb-phy@700         '              Ø            î        jref da_ref          b   c   d   e        nintr rx_imp tx_imp          	ñ           ø   @         phy@11e80000              mediatek,mt8195-pcie-phy            '    è                 ¦sif         b   f   g   h   i   j   k   l      G  nglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          Ï   +           	ñ            •okay            ø   P      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           '    ú        À         Ø            
  junipro mp           	ñ          	  •disabled            ø   K      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           '             @         Ø   m          0  …      �             Œ             ‹                job mmu gpu         
,   n      (  Ï   +   
   +      +      +      +           
@core0 core1 core2 core3 core4           •okay            
S   o      clock-controller@13fbf000             mediatek,mt8195-mfgcfg          '    ûð                Ë           ø   m      syscon@14000000           mediatek,mt8195-vppsys0 syscon          '                      Ë           
_   p                   ø         dma-controller@14001000           mediatek,mt8195-mdp3-rdma           '                     
_   p                  
w              
‹   q        Ï   +           
˜   r   €        Ø            <  è   p         p         p         p         p              
Ÿ         display@14002000              mediatek,mt8195-mdp3-fg         '                      
_   p                   Ø             display@14003000              mediatek,mt8195-mdp3-stitch         '     0                
_   p      0            Ø            display@14004000              mediatek,mt8195-mdp3-hdr            '     @                
_   p      @            Ø      "      display@14005000              mediatek,mt8195-mdp3-aal            '     P                …      F               
_   p      P            Ø      
        Ï   +         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '     `                
_   p      `            
w    %        Ø            display@14007000              mediatek,mt8195-mdp3-tdshp          '     p                
_   p      p            Ø      #      display@14008000              mediatek,mt8195-mdp3-color          '     €                …      I               
_   p      €            Ø      $        Ï   +         display@14009000              mediatek,mt8195-mdp3-ovl            '     �                …      J               
_   p      �            Ø      %        Ï   +           
˜   r   ‚      display@1400a000              mediatek,mt8195-mdp3-padding            '                      
_   p                   Ø              Ï   +         display@1400b000              mediatek,mt8195-mdp3-tcc            '     °                
_   p      °            Ø            dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '     À                
_   p      À            
w    +        Ø              
˜   r   ƒ        Ï   +           
Ÿ         mutex@1400f000            mediatek,mt8195-vpp-mutex           '     ð                …      P               
_   p      ð            Ø              Ï   +         smi@14010000              mediatek,mt8195-smi-sub-common          '                     Ø                          japb smi gals0           
ª   s        Ï   +           ø   t      smi@14011000              mediatek,mt8195-smi-sub-common          '                    Ø                          japb smi gals0           
ª   s        Ï   +           ø   ‘      smi@14012000              mediatek,mt8195-smi-common-vpp          '                      Ø                                japb smi gals0 gals1         Ï   +           ø   s      larb@14013000             mediatek,mt8195-smi-larb            '    0                
·           
ª   t        Ø                    japb smi         Ï   +           ø   w      iommu@14018000            mediatek,mt8195-iommu-vpp           '    €              8  
È   u   v   w   x   y   z   {   |   }   ~      €   �   ‚        …      R               Ø              jbclk            š           Ï   +           ø   r      clock-controller@14e00000             mediatek,mt8195-wpesys          '    à                 Ë           ø         clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         '    à                 Ë         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         '    à0                Ë         larb@14e04000             mediatek,mt8195-smi-larb            '    à@                
·           
ª   ƒ        Ø                    japb smi         Ï   +           ø   ¤      larb@14e05000             mediatek,mt8195-smi-larb            '    àP                
·           
ª   s        Ø                          japb smi gals            Ï   +           ø   y      syscon@14f00000           mediatek,mt8195-vppsys1 syscon          '    ð                 Ë           
_   p   	               ø         mutex@14f01000            mediatek,mt8195-vpp-mutex           '    ð                …      {               
_   p   	              Ø      '        Ï   +         larb@14f02000             mediatek,mt8195-smi-larb            '    ð                 
·           
ª   ƒ        Ø                          japb smi gals            Ï   +           ø   £      larb@14f03000             mediatek,mt8195-smi-larb            '    ð0                
·           
ª   t        Ø                          japb smi gals            Ï   +           ø   x      display@14f06000              mediatek,mt8195-mdp3-split          '    ð`                
_   p   	  `            Ø            +      ,        Ï   +         display@14f07000              mediatek,mt8195-mdp3-tcc            '    ðp                
_   p   	  p            Ø            dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           '    ð€                
_   p   	  €            
w  „  ¨        Ø              
˜   „            Ï   +           
Ÿ         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           '    ð�                
_   p   	  �            
w  …  ©        Ø      
        
˜   „   ¤        Ï   +           
Ÿ         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           '    ð                 
_   p   	               
w  †  ª        Ø              
˜   r   À        Ï   +           
Ÿ         display@14f0b000              mediatek,mt8195-mdp3-fg         '    ð°                
_   p   	  °            Ø      	      display@14f0c000              mediatek,mt8195-mdp3-fg         '    ðÀ                
_   p   	  À            Ø            display@14f0d000              mediatek,mt8195-mdp3-fg         '    ðÐ                
_   p   	  Ð            Ø            display@14f0e000              mediatek,mt8195-mdp3-hdr            '    ðà                
_   p   	  à            Ø            display@14f0f000              mediatek,mt8195-mdp3-hdr            '    ðð                
_   p   	  ð            Ø            display@14f10000              mediatek,mt8195-mdp3-hdr            '    ñ                 
_   p   
               Ø             display@14f11000              mediatek,mt8195-mdp3-aal            '    ñ                …      i               
_   p   
              Ø              Ï   +         display@14f12000              mediatek,mt8195-mdp3-aal            '    ñ                 …      j               
_   p   
               Ø              Ï   +         display@14f13000              mediatek,mt8195-mdp3-aal            '    ñ0                …      k               
_   p   
  0            Ø      !        Ï   +         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '    ñ@                
_   p   
  @            
w  �  ¯        Ø            display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '    ñP                
_   p   
  P            
w  ‘  °        Ø      $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '    ñ`                
_   p   
  `            
w  ’  ±        Ø      %      display@14f17000              mediatek,mt8195-mdp3-tdshp          '    ñp                
_   p   
  p            Ø            display@14f18000              mediatek,mt8195-mdp3-tdshp          '    ñ€                
_   p   
  €            Ø      (      display@14f19000              mediatek,mt8195-mdp3-tdshp          '    ñ�                
_   p   
  �            Ø      )      display@14f1a000              mediatek,mt8195-mdp3-merge          '    ñ                 
_   p   
               Ø              Ï   +         display@14f1b000              mediatek,mt8195-mdp3-merge          '    ñ°                
_   p   
  °            Ø              Ï   +         display@14f1c000              mediatek,mt8195-mdp3-color          '    ñÀ                …      t               
_   p   
  À            Ø              Ï   +         display@14f1d000              mediatek,mt8195-mdp3-color          '    ñÐ                
_   p   
  Ð            …      u               Ø              Ï   +         display@14f1e000              mediatek,mt8195-mdp3-color          '    ñà                …      v               
_   p   
  à            Ø              Ï   +         display@14f1f000              mediatek,mt8195-mdp3-ovl            '    ñð                …      w               
_   p   
  ð            Ø               Ï   +           
˜   „   ¢      display@14f20000              mediatek,mt8195-mdp3-padding            '    ò                 
_   p                  Ø              Ï   +         display@14f21000              mediatek,mt8195-mdp3-padding            '    ò                
_   p                 Ø              Ï   +         display@14f22000              mediatek,mt8195-mdp3-padding            '    ò                 
_   p                  Ø              Ï   +         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '    ò0                
_   p     0            
w  Ÿ  «        Ø              
˜   „   £        Ï   +           
Ÿ         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '    ò@                
_   p     @            
w     ¬        Ø              
˜   „   ¦        Ï   +           
Ÿ         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '    òP                
_   p     P            
w  ¡  ­        Ø              
˜   r   Â        Ï   +           
Ÿ         clock-controller@15000000             mediatek,mt8195-imgsys          '                      Ë           ø   $      larb@15001000             mediatek,mt8195-smi-larb            '                     
·   	        
ª   …        Ø   $       $       $   
        japb smi gals            Ï   +           ø   ¥      smi@15002000              mediatek,mt8195-smi-sub-common          '                      Ø   $      $                 japb smi gals0           
ª   s        Ï   +           ø   ˆ      smi@15003000              mediatek,mt8195-smi-sub-common          '     0                Ø   $       $       $   
        japb smi gals0           
ª   ƒ        Ï   +           ø   …      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         '                     Ë           ø   †      larb@15120000             mediatek,mt8195-smi-larb            '                     
·   
        
ª   …        Ø   $      †            japb smi         Ï   +           ø   ¦      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          '                     Ë         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         '    "                 Ë           ø   ‡      larb@15230000             mediatek,mt8195-smi-larb            '    #                 
·           
ª   …        Ø   $      ‡            japb smi         Ï   +           ø   §      clock-controller@15330000             mediatek,mt8195-ipesys          '    3                 Ë           ø   %      larb@15340000             mediatek,mt8195-smi-larb            '    4                 
·           
ª   ˆ        Ø   %      %           japb smi         Ï   +           ø   z      clock-controller@16000000             mediatek,mt8195-camsys          '                      Ë           ø   &      larb@16001000             mediatek,mt8195-smi-larb            '                     
·           
ª   ‰        Ø   &       &       &           japb smi gals            Ï   +           ø   ¨      larb@16002000             mediatek,mt8195-smi-larb            '                      
·           
ª   Š        Ø   &      &           japb smi         Ï   +           ø   {      smi@16004000              mediatek,mt8195-smi-sub-common          '     @                Ø   &       &       &           japb smi gals0           
ª   ƒ        Ï   +           ø   ‰      smi@16005000              mediatek,mt8195-smi-sub-common          '     P                Ø   &      &                 japb smi gals0           
ª   s        Ï   +           ø   Š      larb@16012000             mediatek,mt8195-smi-larb            '                     
·           
ª   Š        Ø   ‹       ‹            japb smi         Ï   +            ø   |      larb@16013000             mediatek,mt8195-smi-larb            '    0                
·           
ª   ‰        Ø   Œ       Œ            japb smi         Ï   +            ø   ©      larb@16014000             mediatek,mt8195-smi-larb            '    @                
·           
ª   Š        Ø   �       �            japb smi         Ï   +   !        ø   ‚      larb@16015000             mediatek,mt8195-smi-larb            '    P                
·           
ª   ‰        Ø   Ž       Ž            japb smi         Ï   +   !        ø   ®      clock-controller@1604f000             mediatek,mt8195-camsys_rawa         '    ð                Ë           ø   ‹      clock-controller@1606f000             mediatek,mt8195-camsys_yuva         '    ð                Ë           ø   Œ      clock-controller@1608f000             mediatek,mt8195-camsys_rawb         '    ð                Ë           ø   �      clock-controller@160af000             mediatek,mt8195-camsys_yuvb         '    
ð                Ë           ø   Ž      clock-controller@16140000             mediatek,mt8195-camsys_mraw         '                     Ë           ø   �      larb@16141000             mediatek,mt8195-smi-larb            '                    
·           
ª   ‰        Ø   &       �       &           japb smi gals            Ï   +   "        ø   ­      larb@16142000             mediatek,mt8195-smi-larb            '                     
·           
ª   Š        Ø   �       �            japb smi         Ï   +   "        ø   �      clock-controller@17200000             mediatek,mt8195-ccusys          '                      Ë           ø   �      larb@17201000             mediatek,mt8195-smi-larb            '                     
·           
ª   Š        Ø   �       �            japb smi         Ï   +           ø   }      video-codec@18000000              mediatek,mt8195-vcodec-dec          
‹   q        
˜   „                        +            '                   @                A                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         '                       
˜   r  à   r  á         Ø      A                  �        jsel vdec lat top                   A        °      �        Ï   +         video-codec@10000             mediatek,mtk-vcodec-lat         '                      …      Ä             0  
˜   „      „     „     „     „     „           Ø      A                  �        jsel vdec lat top                   A        °      �        Ï   +         video-codec@25000             mediatek,mtk-vcodec-core            '     P                …      Ã             P  
˜   „      „  ¡   „  ¢   „  £   „  ¤   „  ¥   „  ¦   „  §   „  ¨   „  ©         Ø      A                  �        jsel vdec lat top                   A        °      �        Ï   +            larb@1800d000             mediatek,mt8195-smi-larb            '     Ð                
·           
ª   ƒ        Ø                      japb smi         Ï   +           ø   ¬      larb@1800e000             mediatek,mt8195-smi-larb            '     à                
·           
ª   ‘        Ø                     japb smi         Ï   +           ø   €      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         '     ð                Ë           ø         larb@1802e000             mediatek,mt8195-smi-larb            '    à                
·           
ª   ƒ        Ø                      japb smi         Ï   +           ø   «      clock-controller@1802f000             mediatek,mt8195-vdecsys         '    ð                Ë           ø         larb@1803e000             mediatek,mt8195-smi-larb            '    à                
·           
ª   ‘        Ø                      japb smi         Ï   +           ø         clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           '    ð                Ë           ø          clock-controller@190f3000             mediatek,mt8195-apusys_pll          '    0                Ë         clock-controller@1a000000             mediatek,mt8195-vencsys         '                      Ë           ø   !      larb@1a010000             mediatek,mt8195-smi-larb            '                     
·           
ª   ƒ        Ø   !      !           japb smi         Ï   +           ø   ª      video-codec@1a020000              mediatek,mt8195-vcodec-enc          '                   H  
˜   „  `   „  a   „  b   „  c   „  d   „  v   „  w   „  x   „  y        …      U               
‹   q        Ø   !         	  jvenc_sel                   @        °      �        Ï   +                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec          Ï   +         0  
˜   „  m   „  n   „  r   „  s   „  t   „  u                     +         0  A                                            jpgdec@0,0            mediatek,mt8195-jpgdec-hw           '                     0  
˜   „  m   „  n   „  r   „  s   „  t   „  u        …      W               Ø   !           jjpgdec          Ï   +         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw           '                    0  
˜   „  m   „  n   „  r   „  s   „  t   „  u        …      X               Ø   !           jjpgdec          Ï   +         jpgdec@1,0            mediatek,mt8195-jpgdec-hw           '                    0  
˜   r  �   r  Ž   r  ’   r  “   r  ”   r  •        …      \               Ø   "           jjpgdec          Ï   +            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           '                      Ë           ø   "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            '                     è   ’               Ë           
_   ’                  ø         jpeg-encoder@1a030000             mediatek,mt8195-jpgenc          Ï   +            
˜   r  ‡   r  ˆ   r  ‰   r  Œ                     +         0  A                                            jpgenc@0,0            mediatek,mt8195-jpgenc-hw           '                        
˜   „  g   „  h   „  i   „  l        …      V               Ø   !           jjpgenc          Ï   +         jpgenc@1,0            mediatek,mt8195-jpgenc-hw           '                       
˜   r  ‡   r  ˆ   r  ‰   r  Œ        …      [               Ø   "           jjpgenc          Ï   +            larb@1b010000             mediatek,mt8195-smi-larb            '                     
·           
ª   s        Ø   "      "                  japb smi gals            Ï   +           ø   ~      ovl@1c000000              mediatek,mt8195-disp-ovl            '                      …      |               Ï   +           Ø               
˜   „           
_   ’             ports                        +       port@0          '       endpoint             port@1          '      endpoint            
×   “        ø   ”               rdma@1c002000             mediatek,mt8195-disp-rdma           '                      …      ~               Ï   +           Ø              
˜   „            
_   ’             ports                        +       port@0          '       endpoint            
×   ”        ø   “         port@1          '      endpoint            
×   •        ø   –               color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           '     0                …                     Ï   +           Ø              
_   ’     0       ports                        +       port@0          '       endpoint            
×   –        ø   •         port@1          '      endpoint            
×   —        ø   ˜               ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           '     @                …      €               Ï   +           Ø              
_   ’     @       ports                        +       port@0          '       endpoint            
×   ˜        ø   —         port@1          '      endpoint            
×   ™        ø   š               aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           '     P                …      �               Ï   +           Ø              
_   ’     P       ports                        +       port@0          '       endpoint            
×   š        ø   ™         port@1          '      endpoint            
×   ›        ø   œ               gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           '     `                …      ‚               Ï   +           Ø              
_   ’     `       ports                        +       port@0          '       endpoint            
×   œ        ø   ›         port@1          '      endpoint            
×   �        ø   ž               dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         '     p                …      ƒ               Ï   +           Ø      	        
_   ’     p       ports                        +       port@0          '       endpoint            
×   ž        ø   �         port@1          '      endpoint                   dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         '     €                …      „               Ï   +           Ø            *   Ÿ        jengine digital hs           5   Ÿ        	Ÿdphy          	  •disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            '     �                …      …               Ï   +           Ø              
_   ’     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         '                     …      Ž               Ï   +           Ø            +            jengine digital hs           5            	Ÿdphy          	  •disabled          merge@1c014000            mediatek,mt8195-disp-merge          '    @                …      �               Ï   +           Ø              
_   ’     @          dp-intf@1c015000              mediatek,mt8195-dp-intf         '    P                …      ‘               Ï   +           Ø      ,                    jpixel engine pll          	  •disabled          mutex@1c016000            mediatek,mt8195-disp-mutex          '    `                …      ’               Ï   +           Ø              
_   ’     `            
w  U      larb@1c018000             mediatek,mt8195-smi-larb            '    €                
·            
ª   ƒ        Ø      (      (              japb smi gals            Ï   +           ø   ¡      larb@1c019000             mediatek,mt8195-smi-larb            '    �                
·           
ª   s        Ø      (                     japb smi gals            Ï   +           ø   u      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          '                     è   ’              
_   ’                  Ë           ™           ø   #      smi@1c01b000              mediatek,mt8195-smi-common-vdo          '    °                 Ø      %      &      )      $        japb smi gals0 gals1         Ï   +           ø   ƒ      iommu@1c01f000            mediatek,mt8195-iommu-vdo           '    ð              8  
È   ¡   ¢   £   ¤   ¥   ¦   §   ¨   ©   ª   «   ¬   ­   ®        …      �               š           Ø      '        jbclk            Ï   +           ø   „      mutex@1c101000            mediatek,mt8195-disp-mutex          '                    …      î               Ï   +           Ø   #           
_   ’                 
w  À      larb@1c102000             mediatek,mt8195-smi-larb            '                     
·           
ª   ƒ        Ø   #       #       #           japb smi gals            Ï   +           ø   ¢      larb@1c103000             mediatek,mt8195-smi-larb            '    0                
·           
ª   s        Ø   #      #                  japb smi gals            Ï   +           ø   v      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           '    @                …      ï               Ø   #           Ï   +           
˜   „   @        
_   ’     @            
Ÿ         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           '    P                …      ð               Ø   #           Ï   +           
˜   r   `        
_   ’     P            
Ÿ         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           '    `                …      ñ               Ø   #           Ï   +           
˜   „   A        
_   ’     `            
Ÿ         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           '    p                …      ò               Ø   #           Ï   +           
˜   r   a        
_   ’     p            
Ÿ         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           '    €                …      ó               Ø   #           Ï   +           
˜   „   B        
_   ’     €            
Ÿ         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           '    �                …      ô               Ø   #           Ï   +           
˜   r   b        
_   ’     �            
Ÿ         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           '                     …      õ               Ø   #           Ï   +           
˜   „   C        
_   ’                  
Ÿ         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           '    °                …      ö               Ø   #           Ï   +           
˜   r   c        
_   ’     °            
Ÿ         vpp-merge@1c10c000            mediatek,mt8195-disp-merge          '    À                …      ÷               Ø   #   	   #           jmerge merge_async           Ï   +           
_   ’     À             
ç           #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          '    Ð                …      ø               Ø   #   
   #           jmerge merge_async           Ï   +           
_   ’     Ð             
ç           #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          '    à                …      ù               Ø   #      #           jmerge merge_async           Ï   +           
_   ’     à             
ç           #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          '    ð                …      ú               Ø   #      #           jmerge merge_async           Ï   +           
_   ’     ð             
ç           #         vpp-merge@1c110000            mediatek,mt8195-disp-merge          '                     …      û               Ø   #      #           jmerge merge_async           Ï   +           
_   ’                   
û           #         dp-intf@1c113000              mediatek,mt8195-dp-intf         '    0                …                     Ï   +           Ø   #   /   #                 jpixel engine pll          	  •disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  '    @            P            p            �                         °            À              4  ¦mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  
_   ’     @       ’     P       ’     p       ’     �       ’             ’     °       ’     À          h  Ø   #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *            ƒ  jmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          Ï   +           
˜   r   d   r   e        …                   (     #   3   #   4   #   5   #   6   #   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx          '    P        €         b   ¯        ndp_calibration_data         Ï   +           …      ¤                 ¤      	  •disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx           '    `        €         b   ¯        ndp_calibration_data         Ï   +           …      Ê                 ¤      	  •disabled             thermal-zones      cpu0-thermal            #  è        1   ú        G   °      trips      trip-alert          W L        c  Ð        "passive         ø   ±      trip-crit           W †         c  Ð      	  "critical             cooling-maps       map0            n   ±      0  s   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            #  è        1   ú        G   °      trips      trip-alert          W L        c  Ð        "passive         ø   ²      trip-crit           W †         c  Ð      	  "critical             cooling-maps       map0            n   ²      0  s   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            #  è        1   ú        G   °      trips      trip-alert          W L        c  Ð        "passive         ø   ³      trip-crit           W †         c  Ð      	  "critical             cooling-maps       map0            n   ³      0  s   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            #  è        1   ú        G   °      trips      trip-alert          W L        c  Ð        "passive         ø   ´      trip-crit           W †         c  Ð      	  "critical             cooling-maps       map0            n   ´      0  s   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            #  è        1   ú        G   °       trips      trip-alert          W L        c  Ð        "passive         ø   µ      trip-crit           W †         c  Ð      	  "critical             cooling-maps       map0            n   µ      0  s   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            #  è        1   ú        G   °      trips      trip-alert          W L        c  Ð        "passive         ø   ¶      trip-crit           W †         c  Ð      	  "critical             cooling-maps       map0            n   ¶      0  s   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            #  è        1   ú        G   °      trips      trip-alert          W L        c  Ð        "passive         ø   ·      trip-crit           W †         c  Ð      	  "critical             cooling-maps       map0            n   ·      0  s   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            #  è        1   ú        G   °      trips      trip-alert          W L        c  Ð        "passive         ø   ¸      trip-crit           W †         c  Ð      	  "critical             cooling-maps       map0            n   ¸      0  s   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            #  è        1   ú        G   ¹      trips      trip-alert          W L        c  Ð        "passive       trip-crit           W †         c  Ð      	  "critical                vpu1-thermal            #  è        1   ú        G   ¹   	   trips      trip-alert          W L        c  Ð        "passive       trip-crit           W †         c  Ð      	  "critical                gpu-thermal         #  è        1   ú        G   ¹   
   trips      trip-alert          W L        c  Ð        "passive       trip-crit           W †         c  Ð      	  "critical                gpu1-thermal            #  è        1   ú        G   ¹      trips      trip-alert          W L        c  Ð        "passive       trip-crit           W †         c  Ð      	  "critical                vdec-thermal            #  è        1   ú        G   ¹      trips      trip-alert          W L        c  Ð        "passive       trip-crit           W †         c  Ð      	  "critical                img-thermal         #  è        1   ú        G   ¹      trips      trip-alert          W L        c  Ð        "passive       trip-crit           W †         c  Ð      	  "critical                infra-thermal           #  è        1   ú        G   ¹      trips      trip-alert          W L        c  Ð        "passive       trip-crit           W †         c  Ð      	  "critical                cam0-thermal            #  è        1   ú        G   ¹      trips      trip-alert          W L        c  Ð        "passive       trip-crit           W †         c  Ð      	  "critical                cam1-thermal            #  è        1   ú        G   ¹      trips      trip-alert          W L        c  Ð        "passive       trip-crit           W †         c  Ð      	  "critical                cpu-thermal         #  è        1            G   º   trips      trip-alert          W L        c  Ð        "passive       trip-crit           W s        c  Ð      	  "critical                pcb-top-thermal         #  è        1            G   »   trips      trip-alert          W $ø        c  Ð        "passive       trip-crit           W L        c  Ð      	  "critical                pcb-bottom-thermal          #  è        1            G   ¼   trips      trip-alert          W $ø        c  Ð        "passive       trip-crit           W L        c  Ð      	  "critical                   chosen          ‚serial0:115200n8          firmware       optee             linaro,optee-tz         2smc          gpio-keys         
    gpio-keys           default         "   ½   key-0           q      j         
  Žvolume_up           ”   s         :        Ÿ            leds          
    gpio-leds           default         "   ¾   led-0           q      k            ±keep            ¿power           È            memory@40000000         memory          '    @       €         regulator-vsys            regulator-fixed         þvsys             Y         Î         LK@        % LK@        ø   Y      reserved-memory                      +            A   optee@43200000           à        '    C        À        memory@50000000           shared-dma-pool         '    P       �           à        ø   )      memory@53000000           shared-dma-pool         '    S       @        memory@54600000          à        '    T`                memory@60000000           shared-dma-pool         '    `                  à      memory@62000000           shared-dma-pool         '    b       @           thermal-sensor-0              generic-adc-thermal                     ç   ¿            ósensor-channel          ÿÿžX  Âÿÿ±à  ^ÿÿÅh  ìÿÿØð  nÿÿìx  ì      j  ˆ  î  '  {  :˜    N   »  a¨  o  u0  /  ˆ¸   ú  œ@   Î  ¯È   ª  ÃP   �  ÖØ   u  ê`   a  ýè   Q p   D $ø   9 8€   0 L   ) _�   # s    †     š(    ­°    Á8    ÔÀ    èH    ûÐ   
 X   	 "à    6h    Ið           ø   º      thermal-sensor-1              generic-adc-thermal                     ç   ¿           ósensor-channel          ÿÿžX  Âÿÿ±à  ^ÿÿÅh  ìÿÿØð  nÿÿìx  ì      j  ˆ  î  '  {  :˜    N   »  a¨  o  u0  /  ˆ¸   ú  œ@   Î  ¯È   ª  ÃP   �  ÖØ   u  ê`   a  ýè   Q p   D $ø   9 8€   0 L   ) _�   # s    †     š(    ­°    Á8    ÔÀ    èH    ûÐ   
 X   	 "à    6h    Ið           ø   »      thermal-sensor-2              generic-adc-thermal                     ç   ¿           ósensor-channel          ÿÿžX  Âÿÿ±à  ^ÿÿÅh  ìÿÿØð  nÿÿìx  ì      j  ˆ  î  '  {  :˜    N   »  a¨  o  u0  /  ˆ¸   ú  œ@   Î  ¯È   ª  ÃP   �  ÖØ   u  ê`   a  ýè   Q p   D $ø   9 8€   0 L   ) _�   # s    †     š(    ­°    Á8    ÔÀ    èH    ûÐ   
 X   	 "à    6h    Ið           ø   ¼         	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 mmc0 mmc1 serial0 serial1 serial2 serial3 serial4 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux drive-strength input-enable output-high input-disable bias-disable bias-pull-up drive-strength-microamp bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 uart-has-rtscts mediatek,pad-select spi-max-frequency nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,mac-wol reset-assert-us reset-deassert-us reset-gpios snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup dr_mode vusb33-supply bus-width hs400-ds-delay cap-mmc-highspeed cap-mmc-hw-reset mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable vmmc-supply vqmmc-supply cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc freq-table-hz mediatek,ufs-disable-mcq mediatek,u3p-dis-msk bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-rx-bus-width spi-tx-bus-width bits #phy-cells LDO_VIN1-supply LDO_VIN2-supply LDO_VIN3-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path label linux,code debounce-interval default-state function color regulator-boot-on no-map io-channels io-channel-names temperature-lookup-table 