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swr_rx_data   dmic01-default-stategclk-pins gpio6 dmic1_clk  data-pins gpio7 dmic1_data  dmic23-default-stategUclk-pins gpio8 dmic2_clk  data-pins gpio9 dmic2_data  wsa-swr-active-stategclk-pins gpio10 wsa_swr_clk   data-pins gpio11 wsa_swr_data   wsa2-swr-active-stategclk-pins gpio15 wsa2_swr_clk   data-pins gpio16 wsa2_swr_data   spkr-01-sd-n-active-state gpio12 gpio   gspkr-23-sd-n-active-state gpio13 gpio   gclock-controller@6ea0000,?qcom,x1e80100-lpassccqcom,sc8280xp-lpasscc Zginterconnect@7e40000?qcom,x1e80100-lpass-ag-noc&gVinterconnect@7400000?qcom,x1e80100-lpass-lpiaon-noc@&gWinterconnect@7430000?qcom,x1e80100-lpass-lpicx-nocC&gmmc@8804000&?qcom,x1e80100-sdhciqcom,sdhci-msm-v5@hc_irqpwr_irqo==+ifacecorexo <  d, h;q0o !?@7sdhc-ddrcpu-sdhc [$okay `GY cdefaultsleep % 1 > FgXopp-table?operating-points-v2gopp-192000001$8opp-5000000018/opp-100000000180opp-2020000001 F8mmc@8844000&?qcom,x1e80100-sdhciqcom,sdhci-msm-v5@hc_irqpwr_irqo==+ifacecorexo <` d, h;q0o !?@7sdhc-ddrcpu-sdhc [ $disabledgYopp-table?operating-points-v2gopp-192000001$8opp-5000000018/opp-100000000180opp-2020000001 F8phy@88e00008?qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phyTo" +ref=9$okay gphy@88e10008?qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phyTo"+ref=4$okay gphy@88e20008?qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phy To"+ref=5$okaygphy@88e3000?qcom,x1e80100-qmp-usb3-uni-phy0  o===+auxrefcom_auxpipe=G=L phyphy_phy=Z usb_mp_phy0_pipe_clk$okay'7gphy@88e5000?qcom,x1e80100-qmp-usb3-uni-phyP  o===+auxrefcom_auxpipe=H=M phyphy_phy=Z usb_mp_phy1_pipe_clk$okay'7gusb@a0f8800?qcom,x1e80100-dwc3qcom,dwc3 Ho====== ===R+cfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ 4Fr:9 1pwr_eventdp_hs_phy_irqdm_hs_phy_irqss_phy_irq=8=A0o!?@%7usb-ddrapps-usb  $disabledgZusb@a000000 ?snps,dwc3  a <  :usb2-phyusb3-phy M f ~  [g[ports port@0endpointg\port@1endpoint_gusb@a2f8800?qcom,x1e80100-dwc3qcom,dwc3 / Ho====== ===R+cfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ (F21&pwr_eventdp_hs_phy_irqdm_hs_phy_irq=8==0o!?@"7usb-ddrapps-usb $okayg]usb@a200000 ?snps,dwc3   <  usb2-phy high-speed  [ hostg^portendpointg_usb@a4f8800 ?qcom,x1e80100-dwc3-mpqcom,dwc3 OHo====== ===R+cfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ F9:58436578lpwr_event_1pwr_event_2hs_phy_1hs_phy_2dp_hs_phy_1dm_hs_phy_1dp_hs_phy_2dm_hs_phy_2ss_phy_1ss_phy_2=8=>0o!?@&7usb-ddrapps-usb $okayg`usb@a400000 ?snps,dwc3 @ 3 < usb2-0usb3-0usb2-1usb3-1 host M f ~  [gausb@a6f8800?qcom,x1e80100-dwc3qcom,dwc3 oHo==== == ===R+cfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ 4Fs=1pwr_eventdp_hs_phy_irqdm_hs_phy_irqss_phy_irq=8=? $okaygbusb@a600000 ?snps,dwc3 ` c <   8usb2-phyusb3-phy M f ~  [ hostgcports port@0endpoint_gport@1endpoint_gusb@a8f8800?qcom,x1e80100-dwc3qcom,dwc3 Ho== === = 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qup2_se1  gFqup-i2c18-data-clk-state gpio72gpio73 qup2_se2  gIqup-i2c19-data-clk-state gpio76gpio77 qup2_se3  gMqup-i2c20-data-clk-state gpio80gpio81 qup2_se4  gPqup-i2c21-data-clk-state gpio84gpio85 qup2_se5  gSqup-i2c22-data-clk-state gpio88gpio89 qup2_se6  gWqup-i2c23-data-clk-state gpio86gpio87 qup2_se7  gZqup-spi0-cs-state gpio3 qup0_se0  gqup-spi0-data-clk-state gpio0gpio1gpio2 qup0_se0  gqup-spi1-cs-state gpio7 qup0_se1  gqup-spi1-data-clk-state gpio4gpio5gpio6 qup0_se1  gqup-spi2-cs-state gpio11 qup0_se2  gqup-spi2-data-clk-state gpio8gpio9gpio10 qup0_se2  gqup-spi3-cs-state gpio15 qup0_se3  gqup-spi3-data-clk-state gpio12gpio13gpio14 qup0_se3  gqup-spi4-cs-state gpio19 qup0_se4  gqup-spi4-data-clk-state gpio16gpio17gpio18 qup0_se4  gqup-spi5-cs-state gpio23 qup0_se5  gqup-spi5-data-clk-state gpio20gpio21gpio22 qup0_se5  gqup-spi6-cs-state gpio27 qup0_se6  gqup-spi6-data-clk-state gpio24gpio25gpio26 qup0_se6  gqup-spi7-cs-state gpio13 qup0_se7  gqup-spi7-data-clk-state gpio14gpio15gpio12 qup0_se7  gqup-spi8-cs-state gpio35 qup1_se0  gcqup-spi8-data-clk-state gpio32gpio33gpio34 qup1_se0  gbqup-spi9-cs-state gpio39 qup1_se1  gfqup-spi9-data-clk-state gpio36gpio37gpio38 qup1_se1  gequp-spi10-cs-state gpio43 qup1_se2  giqup-spi10-data-clk-state gpio40gpio41gpio42 qup1_se2  ghqup-spi11-cs-state gpio47 qup1_se3  glqup-spi11-data-clk-state gpio44gpio45gpio46 qup1_se3  gkqup-spi12-cs-state gpio51 qup1_se4  goqup-spi12-data-clk-state gpio48gpio49gpio50 qup1_se4  gnqup-spi13-cs-state gpio55 qup1_se5  grqup-spi13-data-clk-state gpio52gpio53gpio54 qup1_se5  gqqup-spi14-cs-state gpio59 qup1_se6  guqup-spi14-data-clk-state gpio56gpio57gpio58 qup1_se6  gtqup-spi15-cs-state gpio53 qup1_se7  gqup-spi15-data-clk-state gpio54gpio55gpio52 qup1_se7  gqup-spi16-cs-state gpio67 qup2_se0  gEqup-spi16-data-clk-state gpio64gpio65gpio66 qup2_se0  gDqup-spi17-cs-state gpio71 qup2_se1  gHqup-spi17-data-clk-state gpio68gpio69gpio70 qup2_se1  gGqup-spi18-cs-state gpio75 qup2_se2  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U out-portsportendpoint_dg^tpdm@10b20000"?qcom,coresight-tpdmarm,primecello +apb_pclk ?  U  $disabledout-portsportendpoint_egftpda@10b23000"?qcom,coresight-tpdaarm,primecell0o +apb_pclk $disabledin-portsportendpoint_fgeout-portsportendpoint_gghfunnel@10b24000+?arm,coresight-dynamic-funnelarm,primecell@o +apb_pclk $disabledin-portsportendpoint_hggout-portsportendpoint_igRtpdm@10c08000"?qcom,coresight-tpdmarm,primecello +apb_pclk ?  U out-portsportendpoint_jgkfunnel@10c0b000+?arm,coresight-dynamic-funnelarm,primecello +apb_pclkin-ports port@4endpoint_kgjout-portsportendpoint_lg|tpdm@10c28000"?qcom,coresight-tpdmarm,primecell€o +apb_pclk ?  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U  $disabledout-portsportendpoint_gtpda@10cc4000"?qcom,coresight-tpdaarm,primecell@o +apb_pclkin-ports port@2endpoint_gout-portsportendpoint_gfunnel@10cc5000+?arm,coresight-dynamic-funnelarm,primecellPo +apb_pclkin-portsportendpoint_gout-portsportendpoint_g=funnel@10d04000+?arm,coresight-dynamic-funnelarm,primecell@o +apb_pclkin-ports port@6endpoint_gout-portsportendpoint_gxtpdm@10d08000"?qcom,coresight-tpdmarm,primecellЀo +apb_pclk   - out-portsportendpoint_gtpdm@10d09000"?qcom,coresight-tpdmarm,primecellАo +apb_pclk   - out-portsportendpoint_gtpdm@10d0a000"?qcom,coresight-tpdmarm,primecellРo +apb_pclk   - out-portsportendpoint_gtpdm@10d0b000"?qcom,coresight-tpdmarm,primecellаo +apb_pclk   - out-portsportendpoint_gtpdm@10d0c000"?qcom,coresight-tpdmarm,primecello +apb_pclk   - out-portsportendpoint_gtpdm@10d0d000"?qcom,coresight-tpdmarm,primecello +apb_pclk   - out-portsportendpoint_gtpdm@10d0e000"?qcom,coresight-tpdmarm,primecello +apb_pclk   - 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