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%bfg coreaudio M ] iZtx-swr-active-stateZclk-pins ugpio0 zswr_tx_clk   data-pins ugpio1gpio2 zswr_tx_data   rx-swr-active-stateZclk-pins ugpio3 zswr_rx_clk   data-pins ugpio4gpio5 zswr_rx_data   dmic01-default-stateZclk-pins ugpio6 zdmic1_clk  data-pins ugpio7 zdmic1_data  dmic23-default-stateZKclk-pins ugpio8 zdmic2_clk  data-pins ugpio9 zdmic2_data  wsa-swr-active-stateZclk-pins ugpio10 zwsa_swr_clk   data-pins ugpio11 zwsa_swr_data   wsa2-swr-active-stateZclk-pins ugpio15 zwsa2_swr_clk   data-pins ugpio16 zwsa2_swr_data   spkr-01-sd-n-active-state ugpio12 zgpio   Zclock-controller@6ea0000,2qcom,x1e80100-lpassccqcom,sc8280xp-lpasscc MZinterconnect@7e400002qcom,x1e80100-lpass-ag-noc&ZLinterconnect@74000002qcom,x1e80100-lpass-lpiaon-noc@&ZMinterconnect@74300002qcom,x1e80100-lpass-lpicx-nocC&Zmmc@8804000&2qcom,x1e80100-sdhciqcom,sdhci-msm-v5@hc_irqpwr_irqb==ifacecorexo <  d, h;d0b !?@*sdhc-ddrcpu-sdhc ? disabledZNopp-table2operating-points-v2Zopp-19200000$$+opp-50000000$+/opp-100000000$+0opp-202000000$ F+mmc@8844000&2qcom,x1e80100-sdhciqcom,sdhci-msm-v5@hc_irqpwr_irqb==ifacecorexo <` d, h;d0b !?@*sdhc-ddrcpu-sdhc ? disabledZOopp-table2operating-points-v2Zopp-19200000$$+opp-50000000$+/opp-100000000$+0opp-202000000$ F+phy@88e000082qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phyTb" ref=9 disabledZphy@88e100082qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phyTb"ref=4okay Zphy@88e200082qcom,x1e80100-snps-eusb2-phyqcom,sm8550-snps-eusb2-phy Tb"ref=5okay Zphy@88e30002qcom,x1e80100-qmp-usb3-uni-phy0  b===auxrefcom_auxpipe=G=L phyphy_phy=Musb_mp_phy0_pipe_clkokay Zphy@88e50002qcom,x1e80100-qmp-usb3-uni-phyP  b===auxrefcom_auxpipe=H=M phyphy_phy=Musb_mp_phy1_pipe_clkokay Zusb@a0f88002qcom,x1e80100-dwc3qcom,dwc3 Hb====== ===Rcfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ 49r:9 1pwr_eventdp_hs_phy_irqdm_hs_phy_irqss_phy_irq=+=A0b!?@%*usb-ddrapps-usb   disabledZPusb@a000000 2snps,dwc3  a < :usb2-phyusb3-phy  , D Z r?ZQports port@0endpointZRport@1endpointRZusb@a2f88002qcom,x1e80100-dwc3qcom,dwc3 / Hb====== ===Rcfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ (921&pwr_eventdp_hs_phy_irqdm_hs_phy_irq=+==0b!?@"*usb-ddrapps-usb   disabledZSusb@a200000 2snps,dwc3   < usb2-phy high-speed Z r?ZTportendpointZUusb@a4f8800 2qcom,x1e80100-dwc3-mpqcom,dwc3 OHb====== ===Rcfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ 99:58436578lpwr_event_1pwr_event_2hs_phy_1hs_phy_2dp_hs_phy_1dm_hs_phy_1dp_hs_phy_2dm_hs_phy_2ss_phy_1ss_phy_2=+=>0b!?@&*usb-ddrapps-usb  okayZVusb@a400000 2snps,dwc3 @ 3 <usb2-0usb3-0usb2-1usb3-1 host  , D Z r?ZWusb@a6f88002qcom,x1e80100-dwc3qcom,dwc3 oHb==== == ===Rcfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys==$ 49s=1pwr_eventdp_hs_phy_irqdm_hs_phy_irqss_phy_irq=+=?  okayZXusb@a600000 2snps,dwc3 ` c <  8usb2-phyusb3-phy  , D Z r? hostZYports port@0endpointRZport@1endpointRZusb@a8f88002qcom,x1e80100-dwc3qcom,dwc3 Hb== === = ===Rcfg_noccoreifacesleepmock_utminoc_aggrnoc_aggr_northnoc_aggr_southnoc_sys= = $ 49t< /1pwr_eventdp_hs_phy_irqdm_hs_phy_irqss_phy_irq=+=@0b!?@$*usb-ddrapps-usb  okayZZusb@a800000 2snps,dwc3  e <` 9usb2-phyusb3-phy  , D Z r? hostZ[ports port@0endpointRZport@1endpointRZvideo-codec@aa00000$2qcom,x1e80100-irisqcom,sm8550-iris   ; ;venusvcodec0mxcmmcxdb=Yifacecorevcodec0_core0b?@*!*cpu-cfgvideo-mem=Xbus<@<G? disabledZ\opp-table2operating-points-v2Zopp-192000000$ q+opp-240000000$N+0/opp-338000000$%x+00opp-366000000$з+opp-444000000$v+opp-481000000$z@+clock-controller@aaf00002qcom,x1e80100-videocc  b2=X;; +//MZdisplay-subsystem@ae000002qcom,x1e80100-mdss +mdss Sb=&:Hb? !!?@*mdp0-memmdp1-memcpu-cfg < okayZdisplay-controller@ae010002qcom,x1e80100-dpu   +mdpvbif9(b=&=:Fnrt_busifacelutcorevsyncd;Z]ports port@0endpointRZ port@4endpointRZport@5endpointR Zport@6endpointR Zopp-table2operating-points-v2Zopp-200000000$ +/opp-325000000$_@+0opp-375000000$Z +opp-514000000$+opp-575000000$"E+ displayport-controller@ae900002qcom,x1e80100-dpP     9 0b Jcore_ifacecore_auxctrl_linkctrl_link_ifacestream_pixelstream_1_pixel 888d ;8dpokayZ^ports port@0endpointR Zport@1endpoint R `=Av1Zopp-table2operating-points-v2Z opp-160000000$ h+/opp-270000000$߀+0opp-540000000$ /+opp-810000000$0G+displayport-controller@ae980002qcom,x1e80100-dpP    9 0bJcore_ifacecore_auxctrl_linkctrl_link_ifacestream_pixelstream_1_pixel  999d;9dpokayZ_ports port@0endpointRZport@1endpoint R `=Av1Zopp-table2operating-points-v2Zopp-160000000$ h+/opp-270000000$߀+0opp-540000000$ /+opp-810000000$0G+displayport-controller@ae9a0002qcom,x1e80100-dpP    90b"$'(*Jcore_ifacecore_auxctrl_linkctrl_link_ifacestream_pixelstream_1_pixel%)+ :::d;:dp disabledZ`ports port@0endpointRZ port@1endpoint RZopp-table2operating-points-v2Zopp-160000000$ h+/opp-270000000$߀+0opp-540000000$ /+opp-810000000$0G+displayport-controller@aea00002qcom,x1e80100-dpP     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Zvtemp-alarm@a002qcom,spmi-temp-alarm  Zgpio@8800!2qcom,pmc8380-gpioqcom,spmi-gpio M i"  ]Z"rtmr0-1p15-reg-en-state ugpio8 znormal hZpmic@62qcom,pmc8380qcom,spmi-pmic Zwtemp-alarm@a002qcom,spmi-temp-alarm  Zgpio@8800!2qcom,pmc8380-gpioqcom,spmi-gpio M i#  ]Z#pmic@82qcom,pm8550qcom,spmi-pmic Zxtemp-alarm@a002qcom,spmi-temp-alarm  Zgpio@8800"2qcom,pm8550ve-gpioqcom,spmi-gpio M i$ ]Z$pmic@92qcom,pm8550qcom,spmi-pmic  Zytemp-alarm@a002qcom,spmi-temp-alarm  Zgpio@8800"2qcom,pm8550ve-gpioqcom,spmi-gpio M i% ]Z%rtmr0-1p8-reg-en-state ugpio8 znormal hZpmic@c2qcom,pm8010qcom,spmi-pmic   disabledZztemp-alarm@24002qcom,spmi-temp-alarm$ $Zspmi@c432000 C @ M +cnfgintr periph_irq 9 Z{pmic@72qcom,smb2360qcom,spmi-pmic okayZ|phy@fd002qcom,smb2360-eusb2-repeater & 'Zpmic@a2qcom,smb2360qcom,spmi-pmic  okayZ}phy@fd002qcom,smb2360-eusb2-repeater & (Zpmic@b2qcom,smb2360qcom,spmi-pmic  okayZ~phy@fd002qcom,smb2360-eusb2-repeater & )Zpmic@c2qcom,smb2360qcom,spmi-pmic   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ugpio24gpio25gpio26 zqup0_se6  Zqup-spi7-cs-state ugpio13 zqup0_se7  Zqup-spi7-data-clk-state ugpio14gpio15gpio12 zqup0_se7  Zqup-spi8-cs-state ugpio35 zqup1_se0  Zaqup-spi8-data-clk-state ugpio32gpio33gpio34 zqup1_se0  Z`qup-spi9-cs-state ugpio39 zqup1_se1  Zdqup-spi9-data-clk-state ugpio36gpio37gpio38 zqup1_se1  Zcqup-spi10-cs-state ugpio43 zqup1_se2  Zgqup-spi10-data-clk-state ugpio40gpio41gpio42 zqup1_se2  Zfqup-spi11-cs-state ugpio47 zqup1_se3  Zjqup-spi11-data-clk-state ugpio44gpio45gpio46 zqup1_se3  Ziqup-spi12-cs-state ugpio51 zqup1_se4  Zmqup-spi12-data-clk-state ugpio48gpio49gpio50 zqup1_se4  Zlqup-spi13-cs-state ugpio55 zqup1_se5  Zpqup-spi13-data-clk-state ugpio52gpio53gpio54 zqup1_se5  Zoqup-spi14-cs-state ugpio59 zqup1_se6  Zsqup-spi14-data-clk-state ugpio56gpio57gpio58 zqup1_se6  Zrqup-spi15-cs-state ugpio53 zqup1_se7  Z~qup-spi15-data-clk-state ugpio54gpio55gpio52 zqup1_se7  Z}qup-spi16-cs-state ugpio67 zqup2_se0  ZEqup-spi16-data-clk-state ugpio64gpio65gpio66 zqup2_se0  ZDqup-spi17-cs-state ugpio71 zqup2_se1  ZHqup-spi17-data-clk-state ugpio68gpio69gpio70 zqup2_se1  ZGqup-spi18-cs-state ugpio75 zqup2_se2  ZLqup-spi18-data-clk-state ugpio72gpio73gpio74 zqup2_se2  ZKqup-spi19-cs-state ugpio79 zqup2_se3  ZOqup-spi19-data-clk-state ugpio76gpio77gpio78 zqup2_se3  ZNqup-spi20-cs-state ugpio83 zqup2_se4  ZRqup-spi20-data-clk-state ugpio80gpio81gpio82 zqup2_se4  ZQqup-spi21-cs-state ugpio87 zqup2_se5  ZUqup-spi21-data-clk-state ugpio84gpio85gpio86 zqup2_se5  ZTqup-spi22-cs-state ugpio91 zqup2_se6  ZYqup-spi22-data-clk-state ugpio88gpio89gpio90 zqup2_se6  ZXqup-spi23-cs-state ugpio85 zqup2_se7  Z\qup-spi23-data-clk-state ugpio86gpio87gpio84 zqup2_se7  Z[qup-uart2-default-stateZcts-pins ugpio8 zqup0_se2  rts-pins ugpio9 zqup0_se2  tx-pins ugpio10 zqup0_se2  rx-pins ugpio11 zqup0_se2  qup-uart14-default-stateZtcts-pins ugpio56 zqup1_se6 rts-pins ugpio57 zqup1_se6  tx-pins ugpio58 zqup1_se6  rx-pins ugpio59 zqup1_se6 qup-uart21-default-stateZVtx-pins ugpio86 zqup2_se5  rx-pins ugpio87 zqup2_se5  sdc2-default-stateZclk-pins usdc2_clk  cmd-pins usdc2_cmd  data-pins usdc2_data  sdc2-sleep-stateZclk-pins usdc2_clk  cmd-pins usdc2_cmd  data-pins usdc2_data  hall-int-n-state ugpio2 zgpio Znvme-reg-en-state ugpio18 zgpio  Zedp-reg-en-state ugpio70 zgpio  Zssam-state-state ugpio91 zgpio Zwcn-wlan-bt-en-state ugpio116gpio117 zgpio  Zpcie3-default-stateZperst-n-pins ugpio143 zgpio  clkreq-n-pins ugpio144 zpcie3_clk  wake-n-pins ugpio145 zgpio  pcie6a-default-stateZperst-n-pins ugpio152 zgpio  clkreq-n-pins ugpio153 zpcie6a_clk  wake-n-pins ugpio154 zgpio  rtmr1-1p8-reg-en-state ugpio175 zgpio  Zrtmr1-3p3-reg-en-state ugpio186 zgpio  Zrtmr1-1p15-reg-en-state ugpio188 zgpio  Zwcd-reset-n-active-state ugpio191 zgpio   Zwcn-sw-en-state ugpio214 zgpio  Zcam-indicator-en-state ugpio225 zgpio  Zstm@10002000 2arm,coresight-stmarm,primecell  (+stm-basestm-stimulus-baseb apb_pclkout-portsportendpointR*Z1tpdm@10003000"2qcom,coresight-tpdmarm,primecell0b apb_pclk   disabledout-portsportendpointR+Z,tpda@10004000"2qcom,coresight-tpdaarm,primecell@b apb_pclkin-ports port@0endpointR,Z+port@1endpointR-Z/out-portsportendpointR.Z0tpdm@1000f000"2qcom,coresight-tpdmarm,primecellb apb_pclk  out-portsportendpointR/Z-funnel@10041000+2arm,coresight-dynamic-funnelarm,primecellb apb_pclkin-ports port@6endpointR0Z.port@7endpointR1Z*out-portsportendpointR2Z7funnel@10042000+2arm,coresight-dynamic-funnelarm,primecell b apb_pclkin-ports port@2endpointR3Z}port@5endpointR4ZGport@6endpointR5Zoout-portsportendpointR6Z8funnel@10045000+2arm,coresight-dynamic-funnelarm,primecellPb apb_pclkin-ports port@0endpointR7Z2port@1endpointR8Z6out-portsportendpointR9ZJtpdm@10800000"2qcom,coresight-tpdmarm,primecellb apb_pclk @ out-portsportendpointR:Zstpdm@1082c000"2qcom,coresight-tpdmarm,primecellb apb_pclk    out-portsportendpointR;Zhtpdm@10841000"2qcom,coresight-tpdmarm,primecellb apb_pclk  out-portsportendpointR<Zftpdm@10844000"2qcom,coresight-tpdmarm,primecell@b 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apb_pclkZin-portsportendpointRLZKout-portsportendpointRMZNreplicator@10b06000/2arm,coresight-dynamic-replicatorarm,primecell`b apb_pclkin-portsportendpointRNZMout-portsportendpointROZtpda@10b08000"2qcom,coresight-tpdaarm,primecellb apb_pclkin-ports port@0endpointRPZVport@1endpointRQZWport@2endpointRRZXport@3endpointRSZYport@4endpointRTZZout-portsportendpointRUZItpdm@10b09000"2qcom,coresight-tpdmarm,primecellb apb_pclk @ out-portsportendpointRVZPtpdm@10b0a000"2qcom,coresight-tpdmarm,primecellb apb_pclk @ out-portsportendpointRWZQtpdm@10b0b000"2qcom,coresight-tpdmarm,primecellb apb_pclk @ out-portsportendpointRXZRtpdm@10b0c000"2qcom,coresight-tpdmarm,primecellb apb_pclk @ out-portsportendpointRYZStpdm@10b0d000"2qcom,coresight-tpdmarm,primecellb apb_pclk    out-portsportendpointRZZTtpdm@10b20000"2qcom,coresight-tpdmarm,primecellb apb_pclk     disabledout-portsportendpointR[Z\tpda@10b23000"2qcom,coresight-tpdaarm,primecell0b apb_pclk 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/backlight.1^/pmic-glink/connector@0/ports/port@0/endpoint.1s/pmic-glink/connector@0/ports/port@1/endpoint.1/pmic-glink/connector@0/ports/port@2/endpoint.1/pmic-glink/connector@1/ports/port@0/endpoint.1/pmic-glink/connector@1/ports/port@1/endpoint.1/pmic-glink/connector@1/ports/port@2/endpoint1/regulator-edp-3p31/regulator-rtmr0-1p152/regulator-rtmr0-1p82/regulator-rtmr0-3p32!/regulator-rtmr1-1p1521/regulator-rtmr1-1p82@/regulator-rtmr1-3p32O/regulator-nvme2Y/regulator-vph-pwr2a/regulator-wcn-0p952o/regulator-wcn-1p92|/regulator-wcn-3p32/wcn7850-pmu/regulators/ldo02/wcn7850-pmu/regulators/ldo12/wcn7850-pmu/regulators/ldo22/wcn7850-pmu/regulators/ldo32/wcn7850-pmu/regulators/ldo42/wcn7850-pmu/regulators/ldo52/wcn7850-pmu/regulators/ldo63/wcn7850-pmu/regulators/ldo73/wcn7850-pmu/regulators/ldo83*/wcn7850-pmu/regulators/ldo9 interrupt-parent#address-cells#size-cellsmodelcompatibleclock-frequency#clock-cellsphandleclocksclock-multclock-divdevice_typeregenable-methodnext-level-cachepower-domainspower-domain-namescache-levelcache-unifiedcpuentry-methodidle-state-namearm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usremote-endpointinterconnectsqcom,dload-modemboxesmbox-namesshmem#power-domain-cells#interconnect-cellsqcom,bcm-votersinterruptsdomain-idle-statesrangesno-maphwlockssizereusablelinux,cma-defaultopp-hzrequired-oppsinterrupts-extendedqcom,smemqcom,local-pidqcom,remote-pidqcom,entry-name#qcom,smem-state-cellsinterrupt-controller#interrupt-cellsdma-ranges#reset-cells#mbox-cellsdma-channelsdma-channel-mask#dma-cellsiommusstatusclock-namesinterconnect-namesdmasdma-namespinctrl-0pinctrl-namesoperating-points-v2max-speedvddaon-supplyvddwlcx-supplyvddwlmx-supplyvddrfacmn-supplyvddrfa0p8-supplyvddrfa1p2-supplyvddrfa1p8-supplycurrent-speedreset-gpiosvdd-supplyvdd33-supplyvdd33-cap-supplyvddar-supplyvddat-supplyvddio-supplyretimer-switchorientation-switchvdd3v3-supplyvdd1v8-supply#phy-cellsinterrupt-names#qcom,sensors#thermal-sensor-cellsresetsvdda12-supplyphysreset-namesmode-switchvdda-phy-supplyvdda-pll-supplyreg-namesbus-rangedma-coherentlinux,pci-domainnum-lanesinterrupt-map-maskinterrupt-mapassigned-clocksassigned-clock-ratesphy-nameseq-presets-8gtseq-presets-16gtsperst-gpioswake-gpiosmax-link-speedopp-peak-kBpsopp-levelclock-output-namesmsi-mapvddpe-3v3-supplyqcom,4ln-config-selvddpcie0p9-supplyvddpcie1p8-supply#hwlock-cellsqcom,gmu#cooling-cellsnvmem-cellsnvmem-cell-namesmemory-regionfirmware-nameqcom,opp-acd-levelopp-supported-hwqcom,qmp#iommu-cells#global-interruptsqcom,smem-statesqcom,smem-state-nameslabelqcom,glink-channelsqcom,non-secure-domainqcom,domainqcom,intents#sound-dai-cellsqcom,protection-domainsound-name-prefixqcom,din-portsqcom,dout-portsqcom,ports-sintervalqcom,ports-offset1qcom,ports-offset2qcom,ports-hstartqcom,ports-hstopqcom,ports-word-lengthqcom,ports-block-pack-modeqcom,ports-block-group-countqcom,ports-lane-controlqcom,rx-port-mappingvdd-1p8-supplyvdd-io-supplyqcom,port-mappingqcom,ports-sinterval-lowqcom,tx-port-mappingqcom,dmic-sample-ratevdd-micb-supplygpio-controller#gpio-cellsgpio-rangespinsfunctiondrive-strengthslew-ratebias-disablebias-bus-holdoutput-highinput-enableoutput-lowqcom,dll-configqcom,ddr-configbus-widthwakeup-sourcesnps,dis_u2_susphy_quirksnps,dis_enblslpm_quirksnps,usb3_lpm_capablesnps,dis-u1-entry-quirksnps,dis-u2-entry-quirkqcom,select-utmi-as-pipe-clkmaximum-speeddr_modeassigned-clock-parentsdata-laneslink-frequenciesbacklightpower-supplyqcom,pdc-rangesqcom,eeqcom,channellinux,codeqcom,no-alarmqcom,uefi-rtc-infobits#pwm-cellspower-sourceinput-disableoutput-enablevdd18-supplyvdd3-supplywakeup-parentgpio-reserved-rangesbias-pull-upqcom,cmb-element-bitsqcom,cmb-msrs-numqcom,dsb-element-bitsqcom,dsb-msrs-num#redistributor-regionsredistributor-stridemsi-controller#msi-cellsqcom,tcs-offsetqcom,drv-idqcom,tcs-configqcom,pmic-idvdd-bob1-supplyvdd-bob2-supplyvdd-l1-l4-l10-supplyvdd-l2-l13-l14-supplyvdd-l5-l16-supplyvdd-l6-l7-supplyvdd-l8-l9-supplyvdd-l12-supplyvdd-l15-supplyvdd-l17-supplyregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-initial-moderegulator-always-onvdd-l1-supplyvdd-l2-supplyvdd-l3-supplyvdd-s4-supplyvdd-s1-supplyvdd-s2-supplyvdd-s5-supplyframe-numberthermal-sensorstemperaturehysteresispolling-delay-passivetripcooling-deviceserial0i2c0i2c3i2c4i2c5i2c7qcom,micbias1-microvoltqcom,micbias2-microvoltqcom,micbias3-microvoltqcom,micbias4-microvoltqcom,mbhc-buttons-vthreshold-microvoltqcom,mbhc-headset-vthreshold-microvoltqcom,mbhc-headphone-vthreshold-microvoltqcom,rx-deviceqcom,tx-devicevdd-buck-supplyvdd-rxtx-supplyvdd-mic-bias-supplypwmsenable-gpioslinux,input-typewakeup-event-actioncolorlinux,default-triggerdefault-statepanic-indicatororientation-gpiospower-roledata-rolegpioenable-active-highregulator-boot-onvin-supplyaudio-routinglink-namesound-daivdddig-supplywlan-enable-gpiosbt-enable-gpiosxo_boardsleep_clkbi_tcxo_div2bi_tcxo_ao_div2cpu0l2_0cpu1cpu2cpu3cpu4l2_1cpu5cpu6cpu7cpu8l2_2cpu9cpu10cpu11cpu_map_cluster2cluster_c4cluster_cl4cluster_cl5eud_inscmscmi_dvfsclk_virtmc_virtcpu_pd0cpu_pd1cpu_pd2cpu_pd3cpu_pd4cpu_pd5cpu_pd6cpu_pd7cpu_pd8cpu_pd9cpu_pd10cpu_pd11cluster_pd0cluster_pd1cluster_pd2system_pdgunyah_hyp_memhyp_elf_package_memncc_memcpucp_log_memcpucp_memtags_memxbl_dtlog_memxbl_ramdump_memaop_image_memaop_cmd_db_memaop_config_memtme_crash_dump_memtme_log_memuefi_log_memsecdata_apss_mempdp_ns_shared_memgpu_prr_memtpm_control_memusb_ucsi_shared_mempld_pep_mempld_gmu_mempld_pdp_memtz_stat_memxbl_tmp_buffer_memadsp_rpc_remote_heap_memspu_secure_shared_memory_memadsp_boot_dtb_memspss_region_memadsp_boot_memvideo_memadspslpi_memq6_adsp_dtb_memcdsp_memq6_cdsp_dtb_memgpu_microcode_memcvp_memcamera_memav1_encoder_memwpss_memq6_wpss_dtb_memxbl_sc_memqtee_memta_memtags_mem1llcc_lpi_memsmem_memqup_opp_table_100mhzqup_opp_table_120mhzsmp2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