8<( f9tsd,px30-cobra-ltk050h3148wtsd,px30-cobrarockchip,px30 +27Theobroma Systems Cobra with ltk050h3148w Displayaliases=/i2c@ff180000B/i2c@ff190000G/i2c@ff1a0000L/i2c@ff1b0000Q/serial@ff030000Y/serial@ff158000a/serial@ff160000i/serial@ff168000q/serial@ff170000y/serial@ff178000/spi@ff1d0000/spi@ff1d8000/ethernet@ff360000/mmc@ff390000cpus+cpu@0cpuarm,cortex-a35psciZ cpu@1cpuarm,cortex-a35psciZ cpu@2cpuarm,cortex-a35psciZ  cpu@3cpuarm,cortex-a35psciZ  idle-statespscicpu-sleeparm,idle-state,=Txeucluster-sleeparm,idle-state,=Teuopp-table-0operating-points-v2opp-600000000#F ~~p@opp-8160000000, p@opp-1008000000< p@opp-1200000000G   p@opp-1296000000M?d ppp@arm-pmuarm,cortex-a35-pmu0defg display-subsystemrockchip,display-subsystem okayexternal-gmac-clock fixed-clock gmac_clkinpsci arm,psci-1.0smctimerarm,armv8-timer0   thermal-zonessoc-thermal4BT tripstrip-point-0dpppassivetrip-point-1dLppassivesoc-critd8p criticalcooling-mapsmap0{ gpu-thermald4T tripsgpu-thresholddpppassivegpu-targetdLppassivegpu-critd8p criticalcooling-mapsmap0{ xin24m fixed-clockn6xin24mmpower-management@ff000000$rockchip,px30-pmusysconsimple-mfdpower-controllerrockchip,px30-power-controller+opower-domain@5<power-domain@7;power-domain@9  C@?power-domain@10 @978:power-domain@11 Kpower-domain@12 XD56power-domain@13 (3 !"#power-domain@14I$syscon@ff010000'rockchip,px30-pmugrfsysconsimple-mfdio-domains$rockchip,px30-pmu-io-voltage-domainokay%%reboot-modesyscon-reboot-modeRBRB RBRBRBserial@ff030000$rockchip,px30-uartsnps,dw-apb-uart &&baudclkapb_pclk*''/txrx9CPdefault ^()* disabledi2s@ff060000rockchip,px30-i2s-tdm  mclk_txmclk_rxhclk*''/txrxh+u |tx-mrx-mPdefault0^,-./01234567 disabledi2s@ff070000&rockchip,px30-i2srockchip,rk3066-i2s  i2s_clki2s_hclk*''/txrxPdefault^89:; disabledi2s@ff080000&rockchip,px30-i2srockchip,rk3066-i2s i2s_clki2s_hclk*''/txrxPdefault^<=>? disabledinterrupt-controller@ff131000 arm,gic-400@ @ `   syscon@ff140000$rockchip,px30-grfsysconsimple-mfd+io-domains rockchip,px30-io-voltage-domainokay@A%%BClvdsrockchip,px30-lvdsDdphyh+"lvds disabledports+port@0+endpoint@02Eendpoint@12Fport@1serial@ff158000$rockchip,px30-uartsnps,dw-apb-uart Ibaudclkapb_pclk9CPdefault^Gokayserial@ff160000$rockchip,px30-uartsnps,dw-apb-uart Jbaudclkapb_pclk*''/txrx9CPdefault^H disabledserial@ff168000$rockchip,px30-uartsnps,dw-apb-uart Kbaudclkapb_pclk*''/txrx9CPdefault ^IJK disabledserial@ff170000$rockchip,px30-uartsnps,dw-apb-uart Lbaudclkapb_pclk*'' /txrx9CPdefault ^LMN disabledserial@ff178000$rockchip,px30-uartsnps,dw-apb-uart Mbaudclkapb_pclk*' ' /txrx9CPdefault^Ookayi2c@ff180000&rockchip,px30-i2crockchip,rk3399-i2cN i2cpclk Pdefault^P+okaypmic@20rockchip,rk809 xin32k QPdefault^RBZhStSSS%%%SregulatorsDCDC_REG1vdd_log~p-qregulator-state-memBZ~DCDC_REG2vdd_arm~p-qregulator-state-memvZ~DCDC_REG3vcc_ddrregulator-state-memBDCDC_REG4 vcc_3v0_1v8--Cregulator-state-memBZ-DCDC_REG5vcc_3v32Z2Z%regulator-state-memBZ2ZLDO_REG2vcc_1v8w@w@Bregulator-state-memBZw@LDO_REG3vcc_1v0B@B@regulator-state-memBZB@LDO_REG4vcc_2v8**Vregulator-state-memvZ*LDO_REG5 vccio_sd--Aregulator-state-memBZ-LDO_REG6 vcc_sdio--@regulator-state-memBZ2ZLDO_REG7vcc_lcdB@B@regulator-state-memvZB@LDO_REG8 vcc_1v8_lcdw@w@regulator-state-memBZw@LDO_REG9 vcca_1v8w@w@regulator-state-memvZw@i2c@ff190000&rockchip,px30-i2crockchip,rk3399-i2cO i2cpclk Pdefault^T+okayi2c@ff1a0000&rockchip,px30-i2crockchip,rk3399-i2cP i2cpclk  Pdefault^U+okay2,touchscreen@14 goodix,gt911V Q QPdefault^WX Q %i2c@ff1b0000&rockchip,px30-i2crockchip,rk3399-i2c Q i2cpclk  Pdefault^Y+ disabledspi@ff1d0000&rockchip,px30-spirockchip,rk3066-spi $Uspiclkapb_pclk*' ' /txrxPdefault^Z[\]+ disabledspi@ff1d8000&rockchip,px30-spirockchip,rk3066-spi %Vspiclkapb_pclk*''/txrxPdefault^^_`ab+ disabledwatchdog@ff1e0000rockchip,px30-wdtsnps,dw-wdt[ %okaypwm@ff200000&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkPdefault^c okaypwm@ff200010&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkPdefault^d okaypwm@ff200020&rockchip,px30-pwmrockchip,rk3328-pwm "S pwmpclkPdefault^e  disabledpwm@ff200030&rockchip,px30-pwmrockchip,rk3328-pwm 0"S pwmpclkPdefault^f  disabledpwm@ff208000&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkPdefault^g  disabledpwm@ff208010&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkPdefault^h okaypwm@ff208020&rockchip,px30-pwmrockchip,rk3328-pwm #T pwmpclkPdefault^i okaypwm@ff208030&rockchip,px30-pwmrockchip,rk3328-pwm 0#T pwmpclkPdefault^j okaytimer@ff210000*rockchip,px30-timerrockchip,rk3288-timer! Y& pclktimerdma-controller@ff240000arm,pl330arm,primecell$@ apb_pclk/'tsadc@ff280000rockchip,px30-tsadc( $:,JP,Xtsadcapb_pclku |tsadc-apbh+_Pinitdefaultsleep^kvlkokay saradc@ff288000,rockchip,px30-saradcrockchip,rk3399-saradc( T-Wsaradcapb_pclku |saradc-apbokayBnvmem@ff290000rockchip,px30-otp)@/Zaotpapb_pclkphyu|phy+id@7cpu-leakage@17performance@1eclock-controller@ff2b0000rockchip,px30-cru+ m& xin24mgpllh+8:@IJFq рр clock-controller@ff2bc000rockchip,px30-pmucru+mxin24mh+:&&& JG&syscon@ff2c0000,rockchip,px30-usb2phy-grfsysconsimple-mfd,+usb2phy@100rockchip,px30-usb2phy & phyclk:n usb480m_phyokaynhost-port D linestateokayqotg-port$BA@otg-bvalidotg-idlinestateokaypphy@ff2e0000rockchip,px30-dsi-dphy.& E refpclku>|apbo okayDphy@ff2f0000rockchip,px30-csi-dphy/@Fpclko u/|apbh+ disabledusb@ff3000000rockchip,px30-usbrockchip,rk3066-usbsnps,dwc20 >otgotg*9@ p usb2-phyookayusb@ff340000 generic-ehci4 <qusbookayusb@ff350000 generic-ohci5 =qusbookayethernet@ff360000rockchip,px30-gmac6 +macirq@>??@ACL[stmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_macclk_mac_speedh+HrmiiPdefault^rso u^ |stmmacethokayQoutput^ti%mdiosnps,dwmac-mdio+ethernet-phy@0ethernet-phy-ieee802.3-c22Pdefault^utPP vtmmc@ff370000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc7@ 6 ;CDbiuciuciu-driveciu-sampleрPdefault^wxyzo disabledmmc@ff380000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc8@ 7 8EFbiuciuciu-driveciu-sampleрPdefault ^{|}o  disabledmmc@ff390000.rockchip,px30-dw-mshcrockchip,rk3288-dw-mshc9@ 5 9GHbiuciuciu-driveciu-sampleрPdefault ^~o okay%Cspi@ff3a0000 rockchip,sfc:@ 8:clk_sfchclk_sfc ^Pdefaulto  disablednand-controller@ff3b0000rockchip,px30-nfc;@ 97ahbnfc:7JрPdefault ^o  disabledopp-table-1operating-points-v2opp-200000000 ~opp-300000000opp-400000000ׄopp-4800000008*gpu@ff400000$rockchip,px30-maliarm,mali-bifrost@@$/.- jobmmugpuIookayvideo-codec@ff442000rockchip,px30-vpuD PO vepuvdpu aclkhclk o iommu@ff442800rockchip,iommuD( Q aclkifaceo dsi@ff450000(rockchip,px30-mipi-dsisnps,dw-mipi-dsiE KDpclkDdphyo u=|apbh+okay+ports+port@0+endpoint@02endpoint@12port@1endpoint2panel@0leadtek,ltk050h3148w'BPdefault^ Q 4Vportendpoint2vop@ff460000rockchip,px30-vop-bigF Maclk_vopdclk_vophclk_vopu345 |axiahbdclk o okayport+ endpoint@02endpoint@12Eiommu@ff460f00rockchip,iommuF M aclkifaceo okayvop@ff470000rockchip,px30-vop-litG Naclk_vopdclk_vophclk_vopu789 |axiahbdclk o  disabledport+ endpoint@02endpoint@12Fiommu@ff470f00rockchip,iommuG N aclkifaceo  disabledvideo-capture@ff490000rockchip,px30-vipI E`aclkhclkpclko u,-.|axiahbpclkin disabledisp@ff4a0000rockchip,px30-cif-ispJ$FIJ ispmimipi 3_ispaclkhclkpclk dphyo  disabledports+port@0iommu@ff4a8000rockchip,iommuJ F aclkifaceo ?qos@ff518000rockchip,px30-qossysconQ qos@ff520000rockchip,px30-qossysconR $qos@ff52c000rockchip,px30-qossysconR qos@ff538000rockchip,px30-qossysconS qos@ff538080rockchip,px30-qossysconS qos@ff538100rockchip,px30-qossysconS qos@ff538180rockchip,px30-qossysconS qos@ff540000rockchip,px30-qossysconT qos@ff540080rockchip,px30-qossysconT qos@ff548000rockchip,px30-qossysconT qos@ff548080rockchip,px30-qossysconT  qos@ff548100rockchip,px30-qossysconT !qos@ff548180rockchip,px30-qossysconT "qos@ff548200rockchip,px30-qossysconT #qos@ff550000rockchip,px30-qossysconU qos@ff550080rockchip,px30-qossysconU qos@ff550100rockchip,px30-qossysconU qos@ff550180rockchip,px30-qossysconU qos@ff558000rockchip,px30-qossysconU qos@ff558080rockchip,px30-qossysconU pinctrlrockchip,px30-pinctrlh+Z+gPdefault^gpio@ff040000rockchip,gpio-bank &n~Qgpio@ff250000rockchip,gpio-bank% \n~gpio@ff260000rockchip,gpio-bank& ]n~vgpio@ff270000rockchip,gpio-bank' ^n~pcfg-pull-uppcfg-pull-downpcfg-pull-nonepcfg-pull-none-2mapcfg-pull-up-2mapcfg-pull-up-4mapcfg-pull-none-4mapcfg-pull-down-4mapcfg-pull-none-8mapcfg-pull-up-8mapcfg-pull-none-12ma pcfg-pull-up-12ma pcfg-pull-none-smtpcfg-output-highpcfg-output-lowpcfg-input-highpcfg-inputi2c0i2c0-xfer  Pi2c1i2c1-xfer Ti2c2i2c2-xfer Ui2c3i2c3-xfer   Ytsadctsadc-otp-pinktsadc-otp-outluart0uart0-xfer   (uart0-cts )uart0-rts *uart1uart1-xfer Guart1-ctsuart1-rtsuart2-m0uart2m0-xfer Huart2-m1uart2m1-xfer  uart3-m0uart3m0-xfer uart3m0-ctsuart3m0-rtsuart3-m1uart3m1-xfer Iuart3m1-cts Juart3m1-rts Kuart4uart4-xfer Luart4-ctsMuart4-rtsNuart5uart5-xfer Ouart5-ctsuart5-rtsspi0spi0-clkZspi0-csn[spi0-miso \spi0-mosi ]spi0-clk-hsspi0-miso-hs spi0-mosi-hs spi1spi1-clk^spi1-csn0 _spi1-csn1 `spi1-misoaspi1-mosi bspi1-clk-hsspi1-miso-hsspi1-mosi-hs pdmpdm-clk0m0pdm-clk0m1pdm-clk1pdm-sdi0m0pdm-sdi0m1pdm-sdi1pdm-sdi2pdm-sdi3pdm-clk0m0-sleeppdm-clk0m1-sleeppdm-clk1-sleeppdm-sdi0m0-sleeppdm-sdi0m1-sleeppdm-sdi1-sleeppdm-sdi2-sleeppdm-sdi3-sleepi2s0i2s0-8ch-mclki2s0-8ch-sclktx,i2s0-8ch-sclkrx -i2s0-8ch-lrcktx.i2s0-8ch-lrckrx /i2s0-8ch-sdo00i2s0-8ch-sdo12i2s0-8ch-sdo24i2s0-8ch-sdo36i2s0-8ch-sdi01i2s0-8ch-sdi1 3i2s0-8ch-sdi2 5i2s0-8ch-sdi37i2s1i2s1-2ch-mclki2s1-2ch-sclk8i2s1-2ch-lrck9i2s1-2ch-sdi:i2s1-2ch-sdo;i2s2i2s2-2ch-mclki2s2-2ch-sclk<i2s2-2ch-lrck=i2s2-2ch-sdi>i2s2-2ch-sdo?sdmmcsdmmc-clkwsdmmc-cmdxsdmmc-detysdmmc-bus1sdmmc-bus4@zsdiosdio-clk}sdio-cmd|sdio-bus4@{emmcemmc-clk ~emmc-cmd emmc-rstnout emmc-bus1emmc-bus4@emmc-bus8emmc-reset flashflash-cs0flash-rdy flash-dqs flash-ale flash-cle flash-wrn flash-cslflash-rdnflash-bus8sfcsfc-bus4@sfc-bus2 sfc-cs0sfc-clk lcdclcdc-rgb-dclk-pinlcdc-rgb-m0-hsync-pinlcdc-rgb-m0-vsync-pinlcdc-rgb-m0-den-pinlcdc-rgb888-m0-data-pins     lcdc-rgb666-m0-data-pins      lcdc-rgb565-m0-data-pins     lcdc-rgb888-m1-data-pins   lcdc-rgb666-m1-data-pins   lcdc-rgb565-m1-data-pins   pwm0pwm0-pincpwm1pwm1-pindpwm2pwm2-pin epwm3pwm3-pinfpwm4pwm4-pingpwm5pwm5-pinhpwm6pwm6-pinipwm7pwm7-pinjgmacrmii-pins rmac-refclk-12ma smac-refclk cif-m0cif-clkout-m0 dvp-d2d9-m0   dvp-d0d1-m0  d10-d11-m0 cif-m1cif-clkout-m1dvp-d2d9-m1  dvp-d0d1-m1 d10-d11-m1 ispisp-prelighthogcobra-pin-hogP ethernetphy-rstuledsheartbeat-led-pinpaneldsp-rst tch-intWtch-rst Xpmicpmic-intRchosen serial5:115200n8backlightpwm-backlight S "abeeper pwm-beeper "emmc-pwrseqmmc-pwrseq-emmc^Pdefault  gpio-leds gpio-ledsPdefault^led-0 ' Q -heartbeat 3heartbeatpwm-leds pwm-ledsled-0 ' Ioff -ring_red "B@ Wled-1 ' Ioff -ring_green "B@ Wled-2 ' Ioff -ring_blue "B@ Wregulator-vccsysregulator-fixed vcc5v0_sysLK@LK@S compatibleinterrupt-parent#address-cells#size-cellsmodeli2c0i2c1i2c2i2c3serial0serial1serial2serial3serial4serial5spi0spi1ethernet0mmc0device_typeregenable-methodclocks#cooling-cellscpu-idle-statesdynamic-power-coefficientoperating-points-v2cpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-usopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendinterruptsinterrupt-affinityportsstatusclock-frequencyclock-output-names#clock-cellspolling-delay-passivepolling-delaysustainable-powerthermal-sensorstemperaturehysteresistripcooling-devicecontribution#power-domain-cellspm_qospmuio1-supplypmuio2-supplyoffsetmode-bootloadermode-fastbootmode-loadermode-normalmode-recoveryclock-namesdmasdma-namesreg-shiftreg-io-widthpinctrl-namespinctrl-0rockchip,grfresetsreset-names#sound-dai-cells#interrupt-cellsinterrupt-controllervccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyphysphy-namesrockchip,outputremote-endpointsystem-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc9-supplyregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayregulator-on-in-suspendregulator-suspend-microvoltregulator-off-in-suspendi2c-scl-falling-time-nsi2c-scl-rising-time-nsAVDD28-supplyirq-gpiosreset-gpiostouchscreen-inverted-xVDDIO-supplynum-cs#pwm-cellsarm,pl330-periph-burst#dma-cellsassigned-clocksassigned-clock-ratesrockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cells#io-channel-cellsvref-supplybits#reset-cellsassigned-clock-parents#phy-cellsinterrupt-namespower-domainsdr_modeg-np-tx-fifo-sizeg-rx-fifo-sizeg-tx-fifo-sizephy-modeclock_in_outphy-handlephy-supplyreset-assert-usreset-deassert-usbus-widthfifo-depthmax-frequencycap-mmc-highspeedmmc-pwrseqnon-removablevmmc-supplyvqmmc-supplymali-supplyiommus#iommu-cellsbacklightiovcc-supplyvci-supplyrockchip,disable-mmu-resetrockchip,pmurangesgpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enableoutput-highoutput-lowinput-enablerockchip,pinsstdout-pathpower-supplypwmscolorlabellinux,default-triggerdefault-statemax-brightness