Ðþí  +Ð   8  (T   (            |  (                             "    amd,seattle-overdrive amd,seattle                                    +         3   7AMD Seattle (Rev.B0) Development Board (Overdrive)     clock-100000000           fixed-clock          =             Jõá          Zadl3clk_100mhz           m         clock-375000000           fixed-clock          =             JZÀ         Zccpclk_375mhz         clock-333000000           fixed-clock          =             JÙ-@         Zsataclk_333mhz           m         clock-500000000           fixed-clock          =             JÍe          Zpcieclk_500mhz        clock-250000000           fixed-clock          =             Jæ²€         Zmiscclk_250mhz           m         interrupt-controller@e1101000             arm,gic-400 arm,cortex-a15-gic            u         Š                        +         @   ›    á             áð             á              á                   Ÿ      	           ª            á                  m      v2m@e0080000              arm,gic-v2m-frame             ±         ›                       m            timer             arm,armv8-timer       0   Ÿ        ÿ        ÿ        ÿ      
  ÿ      bus           simple-bus                       +             ª         À                          sata@e0300000             snps,dwc-ahci            ›    à0                  Ÿ      c            Ë            Ò                    Ù      sata@e0d00000         	   ædisabled              snps,dwc-ahci            ›    àÐ                  Ÿ      b            Ë            Ò                            Ù      iommu@e0200000            arm,mmu-401          ›    à                   í            Ÿ      L         L                         Ù         m         iommu@e0c00000            arm,mmu-401          ›    àÀ                  í            Ÿ      K         K                         Ù         m         i2c@e1000000             æokay              snps,designware-i2c          ›    á                   Ÿ      e            Ë         i2c@e0050000             æokay              snps,designware-i2c          ›    à                  Ÿ      T            Ë         serial@e1010000           arm,pl011 arm,primecell          ›    á                  Ÿ      H            Ë              uartclk apb_pclk          spi@e1020000             æokay              arm,pl022 arm,primecell          ›    á                  Ÿ      J            Ë              sspclk apb_pclk       spi@e1030000             æokay              arm,pl022 arm,primecell          ›    á                  Ÿ      I            Ë              sspclk apb_pclk                                 +       mmc@0             mmc-spi-slot             ›             1-         2  €  H        A            Q            `            t             gpio@e1040000         	   ædisabled              arm,pl061 arm,primecell         ˆ            ›    á                  ”         Ÿ      g             u         Š            Ë         	  apb_pclk          gpio@e1050000            æokay              arm,pl061 arm,primecell         ˆ            ›    á                  ”          u         Š            Ÿ      f            Ë         	  apb_pclk          gpio@e0020000         	   ædisabled              arm,pl061 arm,primecell         ˆ            ›    à                  ”          u         Š            Ÿ      n            Ë         	  apb_pclk          gpio@e0030000         	   ædisabled              arm,pl061 arm,primecell         ˆ            ›    à                  ”          u         Š            Ÿ      m            Ë         	  apb_pclk          gpio@e0080000            æokay              arm,pl061 arm,primecell         ˆ            ›    à                  ”          u         Š            Ÿ      i            Ë         	  apb_pclk          ccp@e0100000             æokay              amd,ccp-seattle-v1a          ›    à                  Ÿ                    Ù          Ò                   @      B      pcie@f0000000             pci-host-ecam-generic                        +            Š           ¤pci         °               º            ›    ð                  Å  ÿ                 à  Ø                                                                  !                                  "                                  #                                  $                                  %                                  &                                  '                                  (                                  )                                  *                                  +             Ù         ÀC                                T   ª               ïÿ                @       @       €                                   æ                       æokay          iommu@e0a00000            arm,mmu-401          ›    à                   í            Ÿ      M         M                         Ù         m         ccn@e8000000              arm,ccn-504          ›    è                   Ÿ      |         kcs@e0010000          	   ædisabled          	    ipmi-kcs            ¤ipmi             ›    à                  Ÿ      …           ð           ù         ethernet@e0700000             amd,xgbe-seattle-v1a          P   ›    àp             àx             á$            á%         `    á% ø             H   Ÿ      E         Z         [         \         ]         C                                -                  =                 Q   
   
           d                    v                 �                   ª¡¢£¤¥           Ë              dma_clk ptp_clk         ¶xgmii            Ò   	                 Ù      ethernet@e0900000             amd,xgbe-seattle-v1a          P   ›    à�             à˜             á$            á% €       `    á% ü             H   Ÿ      D         U         V         W         X         B                                -                  =                 Q   
   
           d                    v                 �                   ª±²³´µ           Ë              dma_clk ptp_clk         ¶xgmii            Ò   
                 Ù      iommu@e0600000            arm,mmu-401          ›    à`                  í            Ÿ      P         P                         Ù         m   	      iommu@e0800000            arm,mmu-401          ›    à€                  í            Ÿ      O         O                         Ù         m   
         cpus                         +       cpu-map    cluster0       core0           ¿         core1           ¿            cluster1       core0           ¿         core1           ¿            cluster2       core0           ¿         core1           ¿            cluster3       core0           ¿         core1           ¿               cpu@0           ¤cpu           arm,cortex-a57           ›            Ãpsci            Ñ  À         Þ   @        ð           ý  €         
   @                   )            m         cpu@1           ¤cpu           arm,cortex-a57           ›           Ãpsci            Ñ  À         Þ   @        ð           ý  €         
   @                   )            m         cpu@100         ¤cpu           arm,cortex-a57           ›           Ãpsci            Ñ  À         Þ   @        ð           ý  €         
   @                   )            m         cpu@101         ¤cpu           arm,cortex-a57           ›          Ãpsci            Ñ  À         Þ   @        ð           ý  €         
   @                   )            m         cpu@200         ¤cpu           arm,cortex-a57           ›           Ãpsci            Ñ  À         Þ   @        ð           ý  €         
   @                   )            m         cpu@201         ¤cpu           arm,cortex-a57           ›          Ãpsci            Ñ  À         Þ   @        ð           ý  €         
   @                   )            m         cpu@300         ¤cpu           arm,cortex-a57           ›           Ãpsci            Ñ  À         Þ   @        ð           ý  €         
   @                   )            m         cpu@301         ¤cpu           arm,cortex-a57           ›          Ãpsci            Ñ  À         Þ   @        ð           ý  €         
   @                   )            m            l2-cache0           Ó           à   @        ò            2        @            m         l2-cache1           Ó           à   @        ò            2        @            m         l2-cache2           Ó           à   @        ò            2        @            m         l2-cache3           Ó           à   @        ò            2        @            m         l3-cache            Q           Ó €          à   @        ò             2         m         pmu           arm,cortex-a57-pmu        `   Ÿ                           	          
                                                    ]                              chosen          p/bus/serial@e1010000          psci              arm,psci-0.2            Êsmc          	compatible interrupt-parent #address-cells #size-cells model #clock-cells clock-frequency clock-output-names phandle interrupt-controller #interrupt-cells reg interrupts ranges msi-controller dma-ranges clocks iommus dma-coherent status #global-interrupts #iommu-cells clock-names num-cs spi-max-frequency voltage-ranges pl022,interface pl022,com-mode pl022,rx-level-trig pl022,tx-level-trig #gpio-cells gpio-controller device_type bus-range msi-parent interrupt-map-mask interrupt-map iommu-map reg-size reg-spacing amd,per-channel-interrupt amd,speed-set amd,serdes-blwc amd,serdes-cdr-rate amd,serdes-pq-skew amd,serdes-tx-amp amd,serdes-dfe-tap-config amd,serdes-dfe-tap-enable mac-address phy-mode cpu enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets l2-cache cache-unified next-level-cache cache-level interrupt-affinity stdout-path 