Ðþí  †ï   8  ƒh   (            ‡  ƒ0                                 hisilicon,hip07-d05                                  +         &   7Hisilicon Hip07 D05 Development Board      psci              arm,psci-0.2             =smc       cpus                         +       cpu-map    cluster0       core0            D         core1            D         core2            D         core3            D            cluster1       core0            D         core1            D         core2            D         core3            D   	         cluster2       core0            D   
      core1            D         core2            D         core3            D            cluster3       core0            D         core1            D         core2            D         core3            D            cluster4       core0            D         core1            D         core2            D         core3            D            cluster5       core0            D         core1            D         core2            D         core3            D            cluster6       core0            D         core1            D         core2            D         core3            D            cluster7       core0            D         core1            D         core2            D          core3            D   !         cluster8       core0            D   "      core1            D   #      core2            D   $      core3            D   %         cluster9       core0            D   &      core1            D   '      core2            D   (      core3            D   )         cluster10      core0            D   *      core1            D   +      core2            D   ,      core3            D   -         cluster11      core0            D   .      core1            D   /      core2            D   0      core3            D   1         cluster12      core0            D   2      core1            D   3      core2            D   4      core3            D   5         cluster13      core0            D   6      core1            D   7      core2            D   8      core3            D   9         cluster14      core0            D   :      core1            D   ;      core2            D   <      core3            D   =         cluster15      core0            D   >      core1            D   ?      core2            D   @      core3            D   A            cpu@10000            Hcpu           arm,cortex-a72           T            Xpsci             f   B         w             „         cpu@10001            Hcpu           arm,cortex-a72           T           Xpsci             f   B         w             „         cpu@10002            Hcpu           arm,cortex-a72           T           Xpsci             f   B         w             „         cpu@10003            Hcpu           arm,cortex-a72           T           Xpsci             f   B         w             „         cpu@10100            Hcpu           arm,cortex-a72           T           Xpsci             f   C         w             „         cpu@10101            Hcpu           arm,cortex-a72           T          Xpsci             f   C         w             „         cpu@10102            Hcpu           arm,cortex-a72           T          Xpsci             f   C         w             „         cpu@10103            Hcpu           arm,cortex-a72           T          Xpsci             f   C         w             „   	      cpu@10200            Hcpu           arm,cortex-a72           T           Xpsci             f   D         w             „   
      cpu@10201            Hcpu           arm,cortex-a72           T          Xpsci             f   D         w             „         cpu@10202            Hcpu           arm,cortex-a72           T          Xpsci             f   D         w             „         cpu@10203            Hcpu           arm,cortex-a72           T          Xpsci             f   D         w             „         cpu@10300            Hcpu           arm,cortex-a72           T           Xpsci             f   E         w             „         cpu@10301            Hcpu           arm,cortex-a72           T          Xpsci             f   E         w             „         cpu@10302            Hcpu           arm,cortex-a72           T          Xpsci             f   E         w             „         cpu@10303            Hcpu           arm,cortex-a72           T          Xpsci             f   E         w             „         cpu@30000            Hcpu           arm,cortex-a72           T            Xpsci             f   F         w            „         cpu@30001            Hcpu           arm,cortex-a72           T           Xpsci             f   F         w            „         cpu@30002            Hcpu           arm,cortex-a72           T           Xpsci             f   F         w            „         cpu@30003            Hcpu           arm,cortex-a72           T           Xpsci             f   F         w            „         cpu@30100            Hcpu           arm,cortex-a72           T           Xpsci             f   G         w            „         cpu@30101            Hcpu           arm,cortex-a72           T          Xpsci             f   G         w            „         cpu@30102            Hcpu           arm,cortex-a72           T          Xpsci             f   G         w            „         cpu@30103            Hcpu           arm,cortex-a72           T          Xpsci             f   G         w            „         cpu@30200            Hcpu           arm,cortex-a72           T           Xpsci             f   H         w            „         cpu@30201            Hcpu           arm,cortex-a72           T          Xpsci             f   H         w            „         cpu@30202            Hcpu           arm,cortex-a72           T          Xpsci             f   H         w            „         cpu@30203            Hcpu           arm,cortex-a72           T          Xpsci             f   H         w            „         cpu@30300            Hcpu           arm,cortex-a72           T           Xpsci             f   I         w            „         cpu@30301            Hcpu           arm,cortex-a72           T          Xpsci             f   I         w            „         cpu@30302            Hcpu           arm,cortex-a72           T          Xpsci             f   I         w            „          cpu@30303            Hcpu           arm,cortex-a72           T          Xpsci             f   I         w            „   !      cpu@50000            Hcpu           arm,cortex-a72           T            Xpsci             f   J         w            „   "      cpu@50001            Hcpu           arm,cortex-a72           T           Xpsci             f   J         w            „   #      cpu@50002            Hcpu           arm,cortex-a72           T           Xpsci             f   J         w            „   $      cpu@50003            Hcpu           arm,cortex-a72           T           Xpsci             f   J         w            „   %      cpu@50100            Hcpu           arm,cortex-a72           T           Xpsci             f   K         w            „   &      cpu@50101            Hcpu           arm,cortex-a72           T          Xpsci             f   K         w            „   '      cpu@50102            Hcpu           arm,cortex-a72           T          Xpsci             f   K         w            „   (      cpu@50103            Hcpu           arm,cortex-a72           T          Xpsci             f   K         w            „   )      cpu@50200            Hcpu           arm,cortex-a72           T           Xpsci             f   L         w            „   *      cpu@50201            Hcpu           arm,cortex-a72           T          Xpsci             f   L         w            „   +      cpu@50202            Hcpu           arm,cortex-a72           T          Xpsci             f   L         w            „   ,      cpu@50203            Hcpu           arm,cortex-a72           T          Xpsci             f   L         w            „   -      cpu@50300            Hcpu           arm,cortex-a72           T           Xpsci             f   M         w            „   .      cpu@50301            Hcpu           arm,cortex-a72           T          Xpsci             f   M         w            „   /      cpu@50302            Hcpu           arm,cortex-a72           T          Xpsci             f   M         w            „   0      cpu@50303            Hcpu           arm,cortex-a72           T          Xpsci             f   M         w            „   1      cpu@70000            Hcpu           arm,cortex-a72           T            Xpsci             f   N         w            „   2      cpu@70001            Hcpu           arm,cortex-a72           T           Xpsci             f   N         w            „   3      cpu@70002            Hcpu           arm,cortex-a72           T           Xpsci             f   N         w            „   4      cpu@70003            Hcpu           arm,cortex-a72           T           Xpsci             f   N         w            „   5      cpu@70100            Hcpu           arm,cortex-a72           T           Xpsci             f   O         w            „   6      cpu@70101            Hcpu           arm,cortex-a72           T          Xpsci             f   O         w            „   7      cpu@70102            Hcpu           arm,cortex-a72           T          Xpsci             f   O         w            „   8      cpu@70103            Hcpu           arm,cortex-a72           T          Xpsci             f   O         w            „   9      cpu@70200            Hcpu           arm,cortex-a72           T           Xpsci             f   P         w            „   :      cpu@70201            Hcpu           arm,cortex-a72           T          Xpsci             f   P         w            „   ;      cpu@70202            Hcpu           arm,cortex-a72           T          Xpsci             f   P         w            „   <      cpu@70203            Hcpu           arm,cortex-a72           T          Xpsci             f   P         w            „   =      cpu@70300            Hcpu           arm,cortex-a72           T           Xpsci             f   Q         w            „   >      cpu@70301            Hcpu           arm,cortex-a72           T          Xpsci             f   Q         w            „   ?      cpu@70302            Hcpu           arm,cortex-a72           T          Xpsci             f   Q         w            „   @      cpu@70303            Hcpu           arm,cortex-a72           T          Xpsci             f   Q         w            „   A      l2-cache0             cache            Œ             ˜         „   B      l2-cache1             cache            Œ             ˜         „   C      l2-cache2             cache            Œ             ˜         „   D      l2-cache3             cache            Œ             ˜         „   E      l2-cache4             cache            Œ             ˜         „   F      l2-cache5             cache            Œ             ˜         „   G      l2-cache6             cache            Œ             ˜         „   H      l2-cache7             cache            Œ             ˜         „   I      l2-cache8             cache            Œ             ˜         „   J      l2-cache9             cache            Œ             ˜         „   K      l2-cache10            cache            Œ             ˜         „   L      l2-cache11            cache            Œ             ˜         „   M      l2-cache12            cache            Œ             ˜         „   N      l2-cache13            cache            Œ             ˜         „   O      l2-cache14            cache            Œ             ˜         „   P      l2-cache15            cache            Œ             ˜         „   Q         interrupt-controller@4d000000             arm,gic-v3           ¦                        +             ·          ¾         Ó            ê             €   T    M              M       @      m       @     M       @     m       @      þ              þ             þ                  ÿ      	            „      msi-controller@4c000000           arm,gic-v3-its           
                    T    L                msi-controller@6c000000           arm,gic-v3-its           
                    T    l                   „   S      msi-controller@c6000000           arm,gic-v3-its           
                    T    Æ                   „   T      msi-controller@8c6000000              arm,gic-v3-its           
                    T   Æ                   „   U      msi-controller@4004c000000            arm,gic-v3-its           
                    T   L                msi-controller@4006c000000            arm,gic-v3-its           
                    T   l                msi-controller@400c6000000            arm,gic-v3-its           
                    T   Æ                   „   V      msi-controller@408c6000000            arm,gic-v3-its           
                    T  Æ                   „   W         ethernet-0            hisilicon,hns-nic-v2            $   R        .           =                Ookay             V         „   g      ethernet-1            hisilicon,hns-nic-v2            $   R        .           =                Ookay             V         „   h      ethernet-2            hisilicon,hns-nic-v2            $   R        .            =                Ookay             V         „   e      ethernet-3            hisilicon,hns-nic-v2            $   R        .           =                Ookay             V         „   f      timer             arm,armv8-timer       0   ÿ                                 
         pmu           arm,cortex-a72-pmu           ÿ               interrupt-controller@60080000             hisilicon,mbigen-v2          T    `            uart_intc           c   S  Ç          ¾         ¦           n            „   \         interrupt-controller@a0080000             hisilicon,mbigen-v2          T                 intc_pcie2_a            c   T  ‡          ¾         ¦           n   
         „   n      intc_sas1           c   T             ¾         ¦           n   €         „   l      intc_sas2           c   T  @          ¾         ¦           n   €         „   m      intc_smmu_pcie          c   T           ¾         ¦           n         intc_usb            c   T  €          ¾         ¦           n            „   ]         interrupt-controller@d0080000             hisilicon,mbigen-v2          T    Ð            intc_sec            c   T            ¾         ¦           n   !         „   o      intc_smmu_alg           c   T           ¾         ¦           n            „   X         interrupt-controller@8,d0080000           hisilicon,mbigen-v2          T   Ð            intc_sec            c   U $           ¾         ¦           n   !         „   q      intc_smmu_alg           c   U +          ¾         ¦           n            „   Y         interrupt-controller@400,d0080000             hisilicon,mbigen-v2          T   Ð            intc_sec            c   V D           ¾         ¦           n   !         „   s      intc_smmu_alg           c   V K          ¾         ¦           n            „   Z         interrupt-controller@408,d0080000             hisilicon,mbigen-v2          T  Ð            intc_sec            c   W d           ¾         ¦           n   !         „   u      intc_smmu_alg           c   W k          ¾         ¦           n            „   [         interrupt-controller@c0080000             hisilicon,mbigen-v2          T    À            intc_dsaf0          c   T            ¾         ¦           n  ™         „   _      intc-roce           c   T           ¾         ¦           n   "         „   i      intc-sas0           c   T 	           ¾         ¦           n   €         „   j      intc_smmu_dsa           c   T            ¾         ¦           n            iommu@a0040000            arm,smmu-v3          T                      w            V         „      	  Odisabled          iommu@d0040000            arm,smmu-v3          T    Ð                     X         ÿ  Ý     Þ     ß           ¢eventq gerror priq          w            V         „         „   p      iommu@8d0040000           arm,smmu-v3          T   Ð                     Y         ÿ  Ý     Þ     ß           ¢eventq gerror priq          w            V         „         „   r      iommu@400d0040000             arm,smmu-v3          T   Ð                     Z         ÿ  Ý     Þ     ß           ¢eventq gerror priq          w            V         „         „   t      iommu@408d0040000             arm,smmu-v3          T  Ð                     [         ÿ  Ý     Þ     ß           ¢eventq gerror priq          w            V         „         „   v      soc           simple-bus                       +             ·   isa@a01b0000              hisilicon,hip07-lpc          +                        T                 bt@e4             ipmi-bt          Hipmi             T      ä           Ookay             serial@602b0000           arm,sbsa-uart            T    `+                     \         ÿ  '           ² Â         À           Ookay          usb@a7030000              generic-ohci             T    §                     ]         ÿ  €            V        Ookay          usb@a7020000              generic-ehci             T    §                     ]         ÿ  �            V        Ookay          sub_ctrl_c@60000000           hisilicon,peri-subctrl syscon            T    `                   „   ^      dsa_subctrl@c0000000              hisilicon,dsa-subctrl syscon             T    À                   „   `      dsa_cpld@78000010             syscon           T    x                 À            „   b      pcie_subctl@a0000000          "    hisilicon,pcie-sas-subctrl syscon            T                        „   k      sds_ctrl@c2200000             syscon           T    Â                   „   a      mdio@603c0000             hisilicon,hns-mdio           T    `<                 Í   ^  8  
8  S  Z                     +       ethernet-phy@0            ethernet-phy-ieee802.3-c22           T             „   c      ethernet-phy@1            ethernet-phy-ieee802.3-c22           T            „   d         dsa@c5000000                         +              hisilicon,hns-dsaf-v2           Û6port-16rss           T    Å        ‰      Ç        `          àppe-base dsaf-base              _        ê   `        ù         È   ÿ  @     A     B     C     D     E     F     G     H     I     J     K     L     M     N     O     P     Q     R     S     T     U     V     W     X     À     Á     Â     Ã     Ä     Å     Æ     Ç     È     É     Ê     Ë     Ì     Í     Î     Ï     Ð     Ñ     Ò     Ó     Ô     Õ     Ö     ×     Ø     Ù     Ú     Û     Ü     Ý     Þ     ß     à     á     â     ã     ä     å     æ     ç     è     é     ê     ë     ì     í     î     ï     ð     ñ     ò     ó     ô     õ     ö     ÷     ø     ù     ú     û     ü     ý     þ     ÿ                                                   	     
                                                                                                                    !     "     #     $     %     &     '     (     )     *     +     ,     -     .     /     0     1     2     3     4     5     6     7     8     9     :     ;     <     =     >     ?     @     A     B     C     D     E     F     G     H     I     J     K     L     M     N     O     P     Q     R     S     T     U     V     W     X     Y     Z     [     \     ]     ^     _     `     a     b     c     d     e     f     g     h     i     j     k     l     m     n     o     p     q     r     s     t     u     v     w     x     y     z     {     |     }     ~          €     �     ‚     ƒ     „     …     †     ‡     ˆ     ‰     Š     ‹     Œ     �     Ž     �     �     ‘     ’     “     ”     •     –     —     ˜     ™     š     ›     œ     �     ž     Ÿ           ¡     ¢     £     ¤     ¥     ¦     §     ¨     ©     ª     «     ¬     ­     ®     ¯     °     ±     ²     ³     ´     µ     ¶     ·     ¸     ¹     º     »     ¼     ½     ¾     ¿     À     Á     Â     Ã     Ä     Å     Æ     Ç     È     É     Ê     Ë     Ì     Í     Î     Ï     Ð     Ñ     Ò     Ó     Ô     Õ     Ö     ×     Ø     Ù     Ú     Û     Ü     Ý     Þ     ß     à     á     â     ã     ä     å     æ     ç     è     é     ê     ë     ì     í     î     ï     ð     ñ     ò     ó     ô     õ     ö     ÷     ø     ù     ú     û     ü     ý     þ     ÿ                                                   	     
                                                                                                                    !     "     #     $     %     &     '     (     )     *     +     ,     -     .     /     0     1     2     3     4     5     6     7     8     9     :     ;     <     =     >     ?                                  V         „   R   port@0           T               a        ,   b            8            H            Yÿð              efiber         port@1           T              a        ,   b           8           H           Yÿð              efiber         port@4           T           p   c           a        8           H           Yÿð              ecopper        port@5           T           p   d           a        8           H           Yÿð              ecopper           infiniband@c4000000           hisilicon,hns-roce-v1            T    Ä                   V        {   e   f           g   h        †   R        ’ šÍ                       +               i        ÿ  Ò     Ó     Ô     Õ     Ö     ×     Ø     Ù     Ú     Û     Ü     Ý     Þ     ß     à     á     â     ã     ä     å     æ     ç     è     é     ê     ë     ì     í     î     ï     ð     ñ          ò        5  ¢hns-roce-comp-0 hns-roce-comp-1 hns-roce-comp-2 hns-roce-comp-3 hns-roce-comp-4 hns-roce-comp-5 hns-roce-comp-6 hns-roce-comp-7 hns-roce-comp-8 hns-roce-comp-9 hns-roce-comp-10 hns-roce-comp-11 hns-roce-comp-12 hns-roce-comp-13 hns-roce-comp-14 hns-roce-comp-15 hns-roce-comp-16 hns-roce-comp-17 hns-roce-comp-18 hns-roce-comp-19 hns-roce-comp-20 hns-roce-comp-21 hns-roce-comp-22 hns-roce-comp-23 hns-roce-comp-24 hns-roce-comp-25 hns-roce-comp-26 hns-roce-comp-27 hns-roce-comp-28 hns-roce-comp-29 hns-roce-comp-30 hns-roce-comp-31 hns-roce-async hns-roce-common          sas@c3000000              hisilicon,hip07-sas-v2           T    Ã                  œPˆ            ¥   `        º  
`        É  Z0        Ü  8        ï           û            V            j         ÿ   @      A      B      C      D      E      F      G      H      I      J      K      L      M      N      O      P      Q      R      S      T      U      V      W      X      Y      Z      [      \      ]      ^      _      `      a      b      c      d      e      f      g      h      i      j      k      l      m      n      o      p      q      r      s      t      u      v      w      x      y      z      {      |      }      ~            €      �      ‚      ƒ      „      …      †      ‡      ˆ      ‰      Š      ‹      Œ      �      Ž      �      �      ‘      ’      “      ”      •      –      —      ˜      ™      š      ›      œ      �      ž      Ÿ     Y     Z     [     \     ]     ^     _     `     a     b     c     d     e     f     g     h     i     j     k     l     m     n     o     p     q     r     s     t     u     v     w     x         	  Odisabled          sas@a2000000              hisilicon,hip07-sas-v2           T    ¢                  œPˆ            ¥   k                 º  
        É  Z        Ü          ï           û            V            l         ÿ   @      A      B      C      D      E      F      G      H      I      J      K      L      M      N      O      P      Q      R      S      T      U      V      W      X      Y      Z      [      \      ]      ^      _      `      a      b      c      d      e      f      g      h      i      j      k      l      m      n      o      p      q      r      s      t      u      v      w      x      y      z      {      |      }      ~            €      �      ‚      ƒ      „      …      †      ‡      ˆ      ‰      Š      ‹      Œ      �      Ž      �      �      ‘      ’      “      ”      •      –      —      ˜      ™      š      ›      œ      �      ž      Ÿ     @     A     B     C     D     E     F     G     H     I     J     K     L     M     N     O     P     Q     R     S     T     U     V     W     X     Y     Z     [     \     ]     ^     _           Ookay          sas@a3000000              hisilicon,hip07-sas-v2           T    £                  œPˆ            ¥   k        º  
à        É  Zp        Ü  ¨        ï           û   	         V            m         ÿ   À      Á      Â      Ã      Ä      Å      Æ      Ç      È      É      Ê      Ë      Ì      Í      Î      Ï      Ð      Ñ      Ò      Ó      Ô      Õ      Ö      ×      Ø      Ù      Ú      Û      Ü      Ý      Þ      ß      à      á      â      ã      ä      å      æ      ç      è      é      ê      ë      ì      í      î      ï      ð      ñ      ò      ó      ô      õ      ö      ÷      ø      ù      ú      û      ü      ý      þ      ÿ                                                   	     
                                                                                                              `     a     b     c     d     e     f     g     h     i     j     k     l     m     n     o     p     q     r     s     t     u     v     w     x     y     z     {     |     }     ~              	  Odisabled          pcie@af800000             hisilicon,hip07-pcie-ecam             T    ¯€       €       
                    ø   ÿ        &  ø    T  ø            .  ÿÿ                     +            Hpci          V      8   ·       ¨       ¨                        ¯                  ¦           ;  ø                  p  N                  n  Ÿ                     n  Ÿ                     n  Ÿ                     n  Ÿ           Ookay          crypto@d0000000           hisilicon,hip07-sec          T    Ð              Ò              Ò             Ò             Ò             Ò             Ò             Ò             Ò             Ò             Ò	             Ò
             Ò             Ò             Ò             Ò             Ò             Ò                     o        \   p            V        ÿ  @     A     B     C     D     E     F     G     H     I     J     K     L     M     N     O     P     Q     R     S     T     U     V     W     X     Y     Z     [     \     ]     ^     _     `         crypto@8d0000000              hisilicon,hip07-sec          T   Ð             Ò             Ò            Ò            Ò            Ò            Ò            Ò            Ò            Ò            Ò	            Ò
            Ò            Ò            Ò            Ò            Ò            Ò                     q        \   r            V        ÿ  @     A     B     C     D     E     F     G     H     I     J     K     L     M     N     O     P     Q     R     S     T     U     V     W     X     Y     Z     [     \     ]     ^     _     `         crypto@400d0000000            hisilicon,hip07-sec          T   Ð             Ò             Ò            Ò            Ò            Ò            Ò            Ò            Ò            Ò            Ò	            Ò
            Ò            Ò            Ò            Ò            Ò            Ò                     s        \   t            V        ÿ  @     A     B     C     D     E     F     G     H     I     J     K     L     M     N     O     P     Q     R     S     T     U     V     W     X     Y     Z     [     \     ]     ^     _     `         crypto@408d0000000            hisilicon,hip07-sec          T  Ð            Ò            Ò           Ò           Ò           Ò           Ò           Ò           Ò           Ò           Ò	           Ò
           Ò           Ò           Ò           Ò           Ò           Ò                     u        \   v            V        ÿ  @     A     B     C     D     E     F     G     H     I     J     K     L     M     N     O     P     Q     R     S     T     U     V     W     X     Y     Z     [     \     ]     ^     _     `            memory@0             Hmemory           T            @            w          distance-map              numa-distance-map-v1          À  c           
                                                 
                                              
                                              
      aliases         s/soc/serial@602b0000          chosen          {serial0:115200n8             	compatible interrupt-parent #address-cells #size-cells model method cpu device_type reg enable-method next-level-cache numa-node-id phandle cache-level cache-unified #interrupt-cells ranges interrupt-controller #redistributor-regions redistributor-stride interrupts msi-controller #msi-cells ae-handle port-idx-in-ae local-mac-address status dma-coherent msi-parent num-pins #iommu-cells hisilicon,broken-prefetch-cmd interrupt-names current-speed reg-io-width subctrl-vbase mode reg-names subctrl-syscon reset-field-offset desc-num buf-size serdes-syscon cpld-syscon port-rst-offset port-mode-offset mc-mac-mask media-type phy-handle eth-handle dsaf-handle node-guid sas-addr hisilicon,sas-syscon ctrl-reset-reg ctrl-reset-sts-reg ctrl-clock-ena-reg queue-count phy-count hip06-sas-v2-quirk-amt bus-range msi-map msi-map-mask interrupt-map-mask interrupt-map iommus distance-matrix serial0 stdout-path 