Ðþí  M   8  ID   (            Ó  I                             $    mediatek,mt6795-evb mediatek,mt6795                                  +         !   7MediaTek MT6795 Evaluation Board          	   =embedded       aliases          J/soc/ovl@1400c000            O/soc/ovl@1400d000            T/soc/rdma@1400e000           Z/soc/rdma@1400f000           `/soc/rdma@14010000           f/soc/wdma@14011000           l/soc/wdma@14012000           r/soc/color@14013000          y/soc/color@14014000          €/soc/split@14018000          ‡/soc/split@14019000          Ž/soc/dpi@1401d000            “/soc/dsi@1401b000            ˜/soc/dsi@1401c000            �/soc/serial@11002000             ¥/soc/serial@11003000             ­/soc/serial@11004000             µ/soc/serial@11005000          psci              arm,psci-0.2             ½smc       cpus                         +       cpu@0            Äcpu           arm,cortex-a53           Ðpsci             Þ             â            ó                    cpu@1            Äcpu           arm,cortex-a53           Ðpsci             Þ            â             €            @        +           8  €         E   @        W   €         ó                    cpu@2            Äcpu           arm,cortex-a53           Ðpsci             Þ            â             €            @        +           8  €         E   @        W   €         ó                    cpu@3            Äcpu           arm,cortex-a53           Ðpsci             Þ            â             €            @        +           8  €         E   @        W   €         ó              	      cpu@100          Äcpu           arm,cortex-a53           Ðpsci             Þ            â             €            @        +           8  €         E   @        W   €         ó              
      cpu@101          Äcpu           arm,cortex-a53           Ðpsci             Þ           â             €            @        +           8  €         E   @        W   €         ó                    cpu@102          Äcpu           arm,cortex-a53           Ðpsci             Þ           â             €            @        +           8  €         E   @        W   €         ó                    cpu@103          Äcpu           arm,cortex-a53           Ðpsci             Þ           â             €            @        +           8  €         E   @        W   €         ó                    cpu-map    cluster0       core0           d         core1           d         core2           d         core3           d   	         cluster1       core0           d   
      core1           d         core2           d         core3           d               l2-cache0             cache           h                         @        -            t                 l2-cache1             cache           h                         @        -            t                    oscillator-26m            fixed-clock         ‚            �Œº€        Ÿclk26m                   oscillator-32k            fixed-clock         ‚            �  }         Ÿclk32k                   dummy13m              fixed-clock         � Æ]@        ‚                     pmu           arm,cortex-a53-pmu        0  ²                 	          
                     ½            	      timer             arm,armv8-timer                   0  ²        ÿ        ÿ        ÿ      
  ÿ      soc                      +             simple-bus           Ð   syscon@10000000            mediatek,mt6795-topckgen syscon          Þ                      ‚                    syscon@10001000            mediatek,mt6795-infracfg syscon          Þ                     ‚           ×                    syscon@10003000           mediatek,mt6795-pericfg syscon           Þ     0                ‚           ×                    syscon@10006000       )    mediatek,mt6795-scpsys syscon simple-mfd             Þ     `           power-controller          !    mediatek,mt6795-power-controller                         +            ä                 power-domain@1           Þ           ø      R        ÿmm          ä          power-domain@2           Þ           ø      R      U        ÿmm venc         ä          power-domain@3           Þ           ø      R        ÿmm          ä          power-domain@0           Þ            ø      R        ÿmm          ä                     power-domain@4           Þ           ø      R      e        ÿmm mjc          ä          power-domain@5           Þ           ä          power-domain@6           Þ           ø           ÿmfg                      +            ä      power-domain@7           Þ                        +            ä      power-domain@8           Þ           ä                                 pinctrl@10005000              mediatek,mt6795-pinctrl           Þ     P             °              
  base eint           ²       ™          š            '        7           C              Å         O        d                    watchdog@10007000             mediatek,mt6795-wdt          Þ     p                ²       €           ×           u         timer@10008000        ,    mediatek,mt6795-timer mediatek,mt6577-timer          Þ     €                ²       ˜           ø            pwrap@1000d000            mediatek,mt6795-pwrap            Þ     Ð                pwrap           ²       ¡           �              ˆpwrap           ø      c         	  ÿspi wrap          interrupt-controller@10200620         .    mediatek,mt6795-sysirq mediatek,mt6577-sysirq            O        d                        Þ                               timer@10200670            mediatek,mt6795-systimer             Þ     p               ²       @           ø           ÿclk13m        iommu@10205000            mediatek,mt6795-m4u          Þ     P                ø              ÿbclk            ²       ’                      ”                    £               ±                    syscon@10209000       "    mediatek,mt6795-apmixedsys syscon            Þ     �                ‚              !      clock-controller@10209f00             mediatek,mt6795-fhctl            Þ     Ÿ              	  ¾disabled          mailbox@10212000          (    mediatek,mt6795-gce mediatek,mt8173-gce          Þ    !                 ²       �           ø              ÿgce         Å                    dsi-phy@10215000              mediatek,mt8173-mipi-tx          Þ    !P                ø           Ÿmipi_tx0_pll            ‚            Ñ          	  ¾disabled                     dsi-phy@10216000              mediatek,mt8173-mipi-tx          Þ    !`                ø           Ÿmipi_tx1_pll            ‚            Ñ          	  ¾disabled                      interrupt-controller@10221000             arm,gic-400         d                        O      @   Þ    "            "              "@             "`                 ²      	                   cci@10390000              arm,cci-400                      +            Þ    9                 Ð        9        slave-if@1000             arm,cci-400-ctrl-if       	  Üace-lite             Þ            slave-if@4000             arm,cci-400-ctrl-if         Üace          Þ  @                     slave-if@5000             arm,cci-400-ctrl-if         Üace          Þ  P                     pmu@9000              arm,cci-400-pmu,r1           Þ  �   P       <  ²       :          ;          <          =          >            serial@11002000       *    mediatek,mt6795-uart mediatek,mt6577-uart            Þ                      ²       [           ø                  	  ÿbaud bus            ë                     ðtx rx           ¾okay          serial@11003000       *    mediatek,mt6795-uart mediatek,mt6577-uart            Þ     0                ²       \           ø                  	  ÿbaud bus            ë                    ðtx rx         	  ¾disabled          dma-controller@11000380       2    mediatek,mt6795-uart-dma mediatek,mt6577-uart-dma         €   Þ     €       `             `     €       `             `     €       `             `     €       `             `      `  ²       g          h          i          j          k          l          m          n           ú           ø              ÿapdma                                        serial@11004000       *    mediatek,mt6795-uart mediatek,mt6577-uart            Þ     @                ²       ]           ø                   	  ÿbaud bus            ë                    ðtx rx         	  ¾disabled          serial@11005000       *    mediatek,mt6795-uart mediatek,mt6577-uart            Þ     P                ²       ^           ø      !            	  ÿbaud bus            ë                    ðtx rx         	  ¾disabled          pwm@11006000              mediatek,mt6795-pwm          Þ     `                &           ²       M         H  ø      S      	                                                ,  ÿtop main pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7       	  ¾disabled          i2c@11007000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c           Þ     p        p             €        ²       T           1           ø                  	  ÿmain dma                         +          	  ¾disabled          i2c@11008000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c           Þ     €        p     €       €        ²       U           1           ø                  	  ÿmain dma                         +          	  ¾disabled          i2c@11009000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c           Þ     �        p             €        ²       V           1           ø                  	  ÿmain dma                         +          	  ¾disabled          i2c@11010000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c           Þ             p     €       €        ²       W           1           ø                  	  ÿmain dma                         +          	  ¾disabled          i2c@11011000          (    mediatek,mt6795-i2c mediatek,mt8173-i2c           Þ            p             €        ²       X           1           ø                  	  ÿmain dma                         +          	  ¾disabled          mmc@11230000              mediatek,mt6795-mmc          Þ    #                 ²       O           ø            \      ]        ÿsource hclk source_cg         	  ¾disabled          mmc@11240000              mediatek,mt6795-mmc          Þ    $                 ²       P           ø            O        ÿsource hclk       	  ¾disabled          mmc@11250000              mediatek,mt6795-mmc          Þ    %                 ²       Q           ø            O        ÿsource hclk       	  ¾disabled          mmc@11260000              mediatek,mt6795-mmc          Þ    &                 ²       R           ø            O        ÿsource hclk       	  ¾disabled          syscon@14000000           mediatek,mt6795-mmsys syscon             Þ                      £               ;      R        K×„         ‚           ×           `                           g                              ovl@1400c000          2    mediatek,mt6795-disp-ovl mediatek,mt8173-disp-ovl            Þ     À                ²       ¼           £               ø                             g        À          ovl@1400d000          2    mediatek,mt6795-disp-ovl mediatek,mt8173-disp-ovl            Þ     Ð                ²       ½           £               ø                            g        Ð          rdma@1400e000         4    mediatek,mt6795-disp-rdma mediatek,mt8173-disp-rdma          Þ     à                ²       ¾           £               ø                            g        à          rdma@1400f000         4    mediatek,mt6795-disp-rdma mediatek,mt8173-disp-rdma          Þ     ð                ²       ¿           £               ø                            g        ð          rdma@14010000         4    mediatek,mt6795-disp-rdma mediatek,mt8173-disp-rdma          Þ                     ²       À           £               ø                            g                   wdma@14011000         4    mediatek,mt6795-disp-wdma mediatek,mt8173-disp-wdma          Þ                    ²       Á           £               ø                            g                  wdma@14012000         4    mediatek,mt6795-disp-wdma mediatek,mt8173-disp-wdma          Þ                     ²       Â           £               ø                            g                   color@14013000        6    mediatek,mt6795-disp-color mediatek,mt8173-disp-color            Þ    0                ²       Ã           £               ø              g        0          color@14014000        6    mediatek,mt6795-disp-color mediatek,mt8173-disp-color            Þ    @                ²       Ä           £               ø              g        @          aal@14015000          2    mediatek,mt6795-disp-aal mediatek,mt8173-disp-aal            Þ    P                ²       Å           £               ø              g        P          gamma@14016000        6    mediatek,mt6795-disp-gamma mediatek,mt8173-disp-gamma            Þ    `                ²       Æ           £               ø              g        `          merge@14017000        6    mediatek,mt6795-disp-merge mediatek,mt8173-disp-merge            Þ    p                £               ø            split@14018000        6    mediatek,mt6795-disp-split mediatek,mt8173-disp-split            Þ    €                £               ø            split@14019000        6    mediatek,mt6795-disp-split mediatek,mt8173-disp-split            Þ    �                £               ø            ufoe@1401a000         4    mediatek,mt6795-disp-ufoe mediatek,mt8173-disp-ufoe          Þ                     ²       Ç           £               ø              g                   dsi@1401b000          (    mediatek,mt6795-dsi mediatek,mt8173-dsi          Þ    °                ²       È           £               ø      $      %           ÿengine digital hs           †           ‹dphy          	  ¾disabled          dsi@1401c000          (    mediatek,mt6795-dsi mediatek,mt8173-dsi          Þ    À                ²       É           £               ø      &      '            ÿengine digital hs           †            ‹dphy          	  ¾disabled          dpi@1401d000          (    mediatek,mt6795-dpi mediatek,mt8183-dpi          Þ    Ð                ²       Ê           £               ø      (      )   !           ÿpixel engine pll          	  ¾disabled          pwm@1401e000          2    mediatek,mt6795-disp-pwm mediatek,mt8173-disp-pwm            Þ    à                &           ø      !               ÿmain mm       	  ¾disabled          pwm@1401f000          2    mediatek,mt6795-disp-pwm mediatek,mt8173-disp-pwm            Þ    ð                &           ø      #      "        ÿmain mm       	  ¾disabled          mutex@14020000            mediatek,mt8173-disp-mutex           Þ                     ²       ±           £               ø              •   4   5        g                   larb@14021000             mediatek,mt6795-smi-larb             Þ                    ø                     ÿapb smi         ©   "        ¶            £                        smi@14022000              mediatek,mt6795-smi-common           Þ                     £               ø                     ÿapb smi            "      od@14023000       0    mediatek,mt6795-disp-od mediatek,mt8173-disp-od          Þ    0                ø              g        0          larb@15001000             mediatek,mt6795-smi-larb             Þ                     ø                     ÿapb smi         ©   "        ¶           £                       clock-controller@16000000             mediatek,mt6795-vdecsys          Þ                      ‚              #      larb@16010000             mediatek,mt6795-smi-larb             Þ                     ©   "        ¶           ø   #       #           ÿapb smi         £                       clock-controller@18000000             mediatek,mt6795-vencsys          Þ                      ‚              $      larb@18001000             mediatek,mt6795-smi-larb             Þ                     ø   $      $            ÿapb smi         ©   "        ¶           £                          memory@40000000          Ämemory           Þ    @       €        chosen          Çserial0:921600n8             	compatible interrupt-parent #address-cells #size-cells model chassis-type ovl0 ovl1 rdma0 rdma1 rdma2 wdma0 wdma1 color0 color1 split0 split1 dpi0 dsi0 dsi1 serial0 serial1 serial2 serial3 method device_type enable-method reg cci-control-port next-level-cache phandle i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets cpu cache-level cache-unified #clock-cells clock-frequency clock-output-names interrupts interrupt-affinity ranges #reset-cells #power-domain-cells clocks clock-names mediatek,infracfg reg-names gpio-controller #gpio-cells gpio-ranges interrupt-controller #interrupt-cells timeout-sec resets reset-names mediatek,larbs power-domains #iommu-cells status #mbox-cells #phy-cells interface-type dmas dma-names dma-requests mediatek,dma-33bits #dma-cells #pwm-cells clock-div assigned-clocks assigned-clock-rates mboxes mediatek,gce-client-reg iommus phys phy-names mediatek,gce-events mediatek,smi mediatek,larb-id stdout-path 