Ðþí .t   8 %¨   (            Ì %p                             $    mediatek,mt8195-evb mediatek,mt8195                                  +         !   7MediaTek MT8195 evaluation board       aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/dpi@1c112000            T/soc/mailbox@10320000            Y/soc/mailbox@10330000            ^/soc/hdmi-tx@1c300000            d/soc/hdr-engine@1c114000             k/soc/mutex@1c016000          r/soc/mutex@1c101000          y/soc/vpp-merge@1c10c000          €/soc/vpp-merge@1c10d000          ‡/soc/vpp-merge@1c10e000          Ž/soc/vpp-merge@1c10f000          •/soc/vpp-merge@1c110000          œ/soc/dma-controller@1c104000             §/soc/dma-controller@1c105000             ²/soc/dma-controller@1c106000             ½/soc/dma-controller@1c107000             È/soc/dma-controller@1c108000             Ó/soc/dma-controller@1c109000             Þ/soc/dma-controller@1c10a000             é/soc/dma-controller@1c10b000             ô/soc/serial@11001100          cpus                         +       cpu@0            ücpu           arm,cortex-a55                      psci                           .ec3@        >  4        Q              a  €         n   @        €   €        �  €         š   @        ¬   €        ¹           Ê           Ù   	      cpu@100          ücpu           arm,cortex-a55                     psci                           .ec3@        >  4        Q              a  €         n   @        €   €        �  €         š   @        ¬   €        ¹           Ê           Ù   
      cpu@200          ücpu           arm,cortex-a55                     psci                           .ec3@        >  4        Q              a  €         n   @        €   €        �  €         š   @        ¬   €        ¹           Ê           Ù         cpu@300          ücpu           arm,cortex-a55                     psci                           .ec3@        >  4        Q              a  €         n   @        €   €        �  €         š   @        ¬   €        ¹           Ê           Ù         cpu@400          ücpu           arm,cortex-a78                     psci                          .�fÔÀ        >           Q              a           n   @        €           �           š   @        ¬           ¹           Ê           Ù         cpu@500          ücpu           arm,cortex-a78                     psci                          .�fÔÀ        >           Q              a           n   @        €           �           š   @        ¬           ¹           Ê           Ù         cpu@600          ücpu           arm,cortex-a78                     psci                          .�fÔÀ        >           Q              a           n   @        €           �           š   @        ¬           ¹           Ê           Ù         cpu@700          ücpu           arm,cortex-a78                     psci                          .�fÔÀ        >           Q              a           n   @        €           �           š   @        ¬           ¹           Ê           Ù         cpu-map    cluster0       core0           á   	      core1           á   
      core2           á         core3           á         core4           á         core5           á         core6           á         core7           á               idle-states         åpsci       cpu-retention-l           arm,idle-state          ò           	           2        +   _        ;  D        Ù         cpu-retention-b           arm,idle-state          ò           	           -        +   Œ        ;  ä        Ù         cpu-off-l             arm,idle-state          ò          	           7        +   ›        ;  H        Ù         cpu-off-b             arm,idle-state          ò          	           2        +   È        ;  è        Ù            l2-cache0             cache           L           c           p   @        ‚           ¹            X        Ù         l2-cache1             cache           L           c           p   @        ‚           ¹            X        Ù         l3-cache              cache           L           c            p   @        ‚            X        Ù            dsu-pmu           arm,dsu-pmu         f                       q   	   
                          vfail          dmic-codec            dmic-codec          }           Š   2      mt8195-sound            š         	  vdisabled          fixed-factor-clock-13m            fixed-factor-clock          ¬            ¹           À           Ê           Õclk13m          Ù   (      oscillator-26m            fixed-clock         ¬            .Œº€        Õclk26m          Ù         oscillator-32k            fixed-clock         ¬            .  €         Õclk32k        performance-controller@11bc10             mediatek,cpufreq-hw               ¼            ½0               è           Ù         opp-table-gpu             operating-points-v2                  Ù   V   opp-390000000               >í€         	‰h      opp-410000000               p€         	¡Ò      opp-431000000               °‰À         	¡Ò      opp-473000000               1h@         	º<      opp-515000000               ²FÀ         	º<      opp-556000000               !#ã          	Ò¦      opp-598000000               #¤Á€         	ë      opp-640000000               &%           	ë      opp-670000000               'ïc€         
ä      opp-700000000               )¹'          
L¸      opp-730000000               +‚ê€         
}Œ      opp-760000000               -L®          
®`      opp-790000000               /q€         
ß4      opp-820000000               0à5                opp-850000000               2©ø€         @Ü      opp-880000000               4s¼          q°         pmu-a55           arm,cortex-a55-pmu                      f                  pmu-a78           arm,cortex-a78-pmu                      f                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  f                                             
             soc                      +             simple-bus           "        )                          interrupt-controller@c000000              arm,gic-v3          4           E                        \                                             f      	               Ù      ppi-partitions     interrupt-partition-0           q   	   
              Ù         interrupt-partition-1           q                    Ù               syscon@10000000            mediatek,mt8195-topckgen syscon                               ¬           Ù         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                               ¬           z           Ù         syscon@10003000           mediatek,mt8195-pericfg syscon               0                ¬           Ù   7      pinctrl@10005000              mediatek,mt8195-pinctrl       €       P            Ñ             Ó             Ô             â             ë             ô              °              B  ‡iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            ‘        ¡           ­              �         \        f       ë               4           Ù      i2c0-pins           Ù   E   pins            ¹    	        À   e        Í            i2c1-pins           Ù   F   pins            ¹  
          À   e        Í            i2c4-pins           Ù   G   pins            ¹            À   e        Ü  è         i2c6-pins           Ù   C   pins            ¹            À   e         i2c7-pins      pins            ¹            À   e         nor-pins            Ù   A   pins0           ¹  Ž  �  �         ô      pins1           ¹  Œ  ‚  ƒ         À         uart0-pins          Ù   .   pins            ¹  b  c            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8195-power-controller                         +                       Ù   *   power-domain@8                                  +                  power-domain@9             	        ¹                    mfg alt         #                        +                  power-domain@10            
                  power-domain@11                              power-domain@12                              power-domain@13                              power-domain@14                                    power-domain@15                  Ø  ¹                        	      @      A      K      à                                                                                                                          vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           #                        +                  power-domain@16                  8  ¹      â      $      %      &      '      (      )      D  vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         #                        +                  power-domain@17                    ¹      á                    vppsys1 vppsys1-0 vppsys1-1         #                     power-domain@22                     ¹                              $  wepsys-0 wepsys-1 wepsys-2 wepsys-3         #                     power-domain@23                    ¹               vdec0-0         #                        +                   power-domain@24                    ¹               vdec1-0         #                     power-domain@25                    ¹                vdec2-0         #                        power-domain@26                    ¹   !            venc0-larb          #                        +                   power-domain@27                    ¹   "            venc1-larb          #                        power-domain@18                     ¹      ã   #       #      #         &  vdosys1 vdosys1-0 vdosys1-1 vdosys1-2           #                        +                  power-domain@19                    #                     power-domain@20                    #                     power-domain@21                    ¹      Q        hdmi_tx                      power-domain@28                    ¹   $       $   
        img-0 img-1         #                        +                  power-domain@29                              power-domain@30                    ¹         $      %           ipe ipe-0 ipe-1         #                        power-domain@31                  (  ¹   &       &      &      &      &           cam-0 cam-1 cam-2 cam-3 cam-4           #                        +                  power-domain@32                               power-domain@33            !                  power-domain@34            "                           power-domain@0                      #                     power-domain@1                     #                     power-domain@2                               power-domain@3                               power-domain@4                     ¹      5      7        csi_rx_top csi_rx_top1                    power-domain@5                     ¹   '           ether                     power-domain@6                     ¹      X      n        adsp adsp1                       +            #                 power-domain@7                      ¹      g      "      n      2        audio audio1 audio2 audio3          #                              watchdog@10007000             mediatek,mt8195-wdt          5             p                z           Ù   -      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                À                ¬           Ù         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer             p                f      	               ¹   (      pwrap@10024000            mediatek,mt8195-pwrap syscon                @                ‡pwrap           f       ó               ¹                   	  spi wrap            M      $        ]      Ë      spmi@10027000             mediatek,mt8195-spmi                 p            �                ‡pmif spmimst            ¹                   E      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         M      $        ]      Ë      infra-iommu@10315000              mediatek,mt8195-iommu-infra             1P       P       P  f                                                                         t           Ù   =      mailbox@10320000              mediatek,mt8195-gce             2        @         f       â               �           ¹              Ù   y      mailbox@10330000              mediatek,mt8195-gce             3        @         f       ä               �           ¹              Ù   W      scp@10500000              mediatek,mt8195-scp       0      P             r             p        €         ‡sram cfg l1tcm          f      Î             	  vdisabled            Ù   X      clock-controller@10720000             mediatek,mt8195-scp_adsp                r                 ¬           Ù   )      dsp@10803000              mediatek,mt8195-dsp              €0            „               	  ‡cfg sram          ,  ¹      X         n      Š   )          #      K  adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          �   *           ›rx tx           ¦   +   ,      	  vdisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           �                �`                f      ¾               Ù   +      mailbox@10817000              mediatek,mt8195-adsp-mbox           �                �p                f      ¿               Ù   ,      mt8195-afe-pcm@10890000           mediatek,mt8195-audio               ‰                 ­           �   *           f      6               ¿   -         	  Æaudiosys          ”  ¹                     Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d      2   )          ó  clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  vdisabled            Ù         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f       �               ¹               	  baud bus            vokay            Òdefault         à   .      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f       Ž               ¹               	  baud bus          	  vdisabled          serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f       �               ¹               	  baud bus          	  vdisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f      Ó               ¹               	  baud bus          	  vdisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f      Ô               ¹               	  baud bus          	  vdisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                f      Õ               ¹               	  baud bus          	  vdisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                 ¹              main            ê           vokay          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                0                ¬           Ù   '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                  f       ¿               ¹      ™                    parent-clk sel-clk spi-clk        	  vdisabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap              °                f       ©               ¹              ¿               ü   /   0      $  lvts-calib-data-1 lvts-calib-data-2                    Ù   ¡      svs@1100bc00              mediatek,mt8195-svs              ¼                f       Ç               ¹              main            ü   1   /      (  svs-calibration-data t-calibration-data         ¿              Æsvs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                à                f       Ë               �   *           /           ¹      *      0        main mm       	  vdisabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                ð                f                     /           ¹      +      N        main mm       	  vdisabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 f       À               ¹      ™            3        parent-clk sel-clk spi-clk        	  vdisabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 f       Á               ¹      ™            4        parent-clk sel-clk spi-clk        	  vdisabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                0                f       Â               ¹      ™            5        parent-clk sel-clk spi-clk        	  vdisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                €                f       Ã               ¹      ™            <        parent-clk sel-clk spi-clk        	  vdisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                �                f       Ä               ¹      ™            =        parent-clk sel-clk spi-clk        	  vdisabled          spi@1101d000              mediatek,mt8195-spi-slave               Ð                f       Å               ¹      R        spi         M              ]      ˜      	  vdisabled          spi@1101e000              mediatek,mt8195-spi-slave               à                f       Æ               ¹      S        spi         M              ]      ˜      	  vdisabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                      @         f      Ì               :macirq        .  axi apb mac_main ptp_ref rmii_internal mac_cg         0  ¹   '       '         R      S      T   '           M      R      S      T        ]      Â      Ã      Ä        �   *           J           [   2        k   3        ~   4        ‘           œ           §          	  vdisabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           ´           Ä           Ô                                 Ù   2      rx-queues-config            Þ            ô        Ù   3   queue0                             queue1                             queue2                             queue3                                tx-queues-config            0            F        Ù   4   queue0          X                    d          queue1          X                    d         queue2          X                    d         queue3          X                    d               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                       -ÿ     >              	  ‡mac ippc            "                     ?                      +           f       €               ¹      /      í      B        sys_ck ref_ck mcu_ck            r   5      6            w        …   7      g        vokay       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 ‡mac         f       �               M      ,      -        ]      –      –      $  ¹      /      í               B      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         vokay             mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              #             õ                 f       ƒ               ¹                          source hclk source_cg         	  vdisabled          mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              $             Ç                 f       ‡               ¹                  $        source hclk source_cg           M              ]      ¿      	  vdisabled          mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              %             æ                 f       ˆ               ¹                   I        source hclk source_cg           M               ]      ¿      	  vdisabled          ufshci@11270000           mediatek,mt8195-ufshci              '        #         f       ‰               r   8      @  ¹      ?      @      A      6      7      8      Z      ]      X  ufs ufs_aes ufs_tick unipro_sysclk unipro_tick unipro_mp_bclk ufs_tx_symbol ufs_mem_sub       @  œ                                                                         ª      	  vdisabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                '€                f       ª               ¹              ¿              ü   /   0      $  lvts-calib-data-1 lvts-calib-data-2                    Ù   ˜      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci               )             )>              	  ‡mac ippc            f                     r   9      :           M      .      /        ]      –      –      $  ¹   '         ï            '         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         …   7      h         w        vokay          usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               *       -ÿ    *>              	  ‡mac ippc            "            *        ?                      +           f                     M      0        ]      –        ¹   '         ñ   '           sys_ck ref_ck mcu_ck            r   ;            w        …   7      i        vokay       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 ‡mac         f                     M      1        ]      –        ¹   '           sys_ck          vokay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               +       -ÿ    +>              	  ‡mac ippc            "            +        ?                      +           f                     M      2        ]      –        ¹   '         ó   '   	        sys_ck ref_ck mcu_ck            r   <            w        …   7      j        vokay       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 ‡mac         f                     M      3        ]      –        ¹   '   	        sys_ck          vokay             Ã         pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            üpci                      +               /        @       	  ‡pcie-mac            f                     Ô       ÿ      8  "�                           ‚                       à          Þ       =              è          0  ¹      V      #      &      +      K   '         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          M      G        ]              r   >      	  ÷pcie-phy            �   *            4                                `                    ?                      ?                     ?                     ?         	  vdisabled       interrupt-controller             \                     4           Ù   ?         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            üpci                      +               /€       @       	  ‡pcie-mac            f                     Ô       ÿ      8  "�       $       $           ‚       $       $       à          Þ       =              è          (  ¹      W         X         Q   '         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          M      H        ]              r   :         	  ÷pcie-phy            �   *           4                                `                    @                      @                     @                     @         	  vdisabled       interrupt-controller             \                     4           Ù   @         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor             2À                f      9               ¹      o   '      '           spi sf axi                       +            vokay            Òdefault         à   A   flash@0           jedec,spi-nor                       "úð€         efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                Á                              +      usb3-tx-imp@184,1             „           4               Ù   M      usb3-rx-imp@184,2             „           4              Ù   L      usb3-intr@185             …           4              Ù   K      usb3-tx-imp@186,1             †           4               Ù   J      usb3-rx-imp@186,2             †           4              Ù   I      usb3-intr@187             ‡           4              Ù   H      usb2-intr-p0@188,1            ˆ           4             usb2-intr-p1@188,2            ˆ           4            usb2-intr-p2@189,1            ‰           4            usb2-intr-p3@189,2            ‰           4            pciephy-rx-ln1@190,1              �           4               Ù   T      pciephy-tx-ln1-nmos@190,2             �           4              Ù   S      pciephy-tx-ln1-pmos@191,1             ‘           4               Ù   R      pciephy-rx-ln0@191,2              ‘           4              Ù   Q      pciephy-tx-ln0-nmos@192,1             ’           4               Ù   P      pciephy-tx-ln0-pmos@192,2             ’           4              Ù   O      pciephy-glb-intr@193              “           4               Ù   N      dp-data@1ac           ¬           Ù   —      lvts1-calib@1bc           ¼           Ù   /      lvts2-calib@1d0           Ð   8        Ù   0      svs-calib@580             €   d        Ù   1      socinfo-data1@7a0                          t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "        Ä             vokay       usb-phy@0                          ¹      ò        ref         9           Ù   ;         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "        Å             vokay       usb-phy@0                          ¹      ô        ref         9           Ù   <         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             È                 ¹           Õmipi_tx0_pll            ¬            9          	  vdisabled            Ù   †      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx             É                 ¹           Õmipi_tx1_pll            ¬            9          	  vdisabled            Ù   ‡      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        f       š               À           ¹   B          ;      	  main dma                         +          	  vdisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð            "        €        f       ›               À           ¹   B         ;      	  main dma                         +            vokay            Òdefault         à   C        . €      i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              Ð             "€       €        f       œ               À           ¹   B         ;      	  main dma                         +          	  vdisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s              Ð0                ¬           Ù   B      hdmi-phy@11d5f000             mediatek,mt8195-hdmi-phy                Õð                 ¹      P                          pll_ref 26m pll1 pll2           Õhdmi_txpll          ¬            9            D   
        S         	  vdisabled            Ù   –      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             " €       €        f       �               À           ¹   D          ;      	  main dma                         +            vokay            Òdefault         à   E        . †       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à            "        €        f       “               À           ¹   D         ;      	  main dma                         +            vokay            Òdefault         à   F        . €      i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à             "€       €        f       –               À           ¹   D         ;      	  main dma                         +          	  vdisabled          i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à0            "€       €        f       ˜               À           ¹   D         ;      	  main dma                         +          	  vdisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              à@            "        €        f       ™               À           ¹   D         ;      	  main dma                         +            vokay            Òdefault         à   G        . €      clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w              àP                ¬           Ù   D      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "        ã             �   *           vokay       usb-phy@0                          ¹      ð           ref da_ref          9           Ù   9      usb-phy@700                       ¹            ð        ref da_ref          ü   H   I   J        intr rx_imp tx_imp          9           Ù   :         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           "        ä             vokay       usb-phy@0                          ¹      î           ref da_ref          9           Ù   5      usb-phy@700                       ¹            î        ref da_ref          ü   K   L   M        intr rx_imp tx_imp          9           Ù   6         phy@11e80000              mediatek,mt8195-pcie-phy                è                 ‡sif         ü   N   O   P   Q   R   S   T      G  glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          �   *           9          	  vdisabled            Ù   >      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy               ú        À         ¹            
  unipro mp           9          	  vdisabled            Ù   8      gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                        @         ¹   U          0  f      �             Œ             ‹               :job mmu gpu         e   V      (  �   *   
   *      *      *      *           ycore0 core1 core2 core3 core4         	  vdisabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg              ûð                ¬           Ù   U      syscon@14000000           mediatek,mt8195-vppsys0 syscon                                ¬           Œ   W                   Ù         dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                Œ   W                  ¤              ¸   X        �   *           Å   Y   €        ¹            <  ¦   W         W         W         W         W              Ì         display@14002000              mediatek,mt8195-mdp3-fg                               Œ   W                   ¹             display@14003000              mediatek,mt8195-mdp3-stitch              0                Œ   W      0            ¹            display@14004000              mediatek,mt8195-mdp3-hdr                 @                Œ   W      @            ¹      "      display@14005000              mediatek,mt8195-mdp3-aal                 P                f      F               Œ   W      P            ¹      
        �   *         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                Œ   W      `            ¤    %        ¹            display@14007000              mediatek,mt8195-mdp3-tdshp               p                Œ   W      p            ¹      #      display@14008000              mediatek,mt8195-mdp3-color               €                f      I               Œ   W      €            ¹      $        �   *         display@14009000              mediatek,mt8195-mdp3-ovl                 �                f      J               Œ   W      �            ¹      %        �   *           Å   Y   ‚      display@1400a000              mediatek,mt8195-mdp3-padding                                  Œ   W                   ¹              �   *         display@1400b000              mediatek,mt8195-mdp3-tcc                 °                Œ   W      °            ¹            dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot              À                Œ   W      À            ¤    +        ¹              Å   Y   ƒ        �   *           Ì         mutex@1400f000            mediatek,mt8195-vpp-mutex                ð                f      P               Œ   W      ð            ¹              �   *         smi@14010000              mediatek,mt8195-smi-sub-common                               ¹                          apb smi gals0           ×   Z        �   *           Ù   [      smi@14011000              mediatek,mt8195-smi-sub-common                              ¹                          apb smi gals0           ×   Z        �   *           Ù   x      smi@14012000              mediatek,mt8195-smi-common-vpp                                ¹                                apb smi gals0 gals1         �   *           Ù   Z      larb@14013000             mediatek,mt8195-smi-larb                0                ä           ×   [        ¹                    apb smi         �   *           Ù   ^      iommu@14018000            mediatek,mt8195-iommu-vpp               €              8  õ   \   ]   ^   _   `   a   b   c   d   e   f   g   h   i        f      R               ¹              bclk            t           �   *           Ù   Y      clock-controller@14e00000             mediatek,mt8195-wpesys              à                 ¬           Ù         clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0             à                 ¬         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1             à0                ¬         larb@14e04000             mediatek,mt8195-smi-larb                à@                ä           ×   j        ¹                    apb smi         �   *           Ù   ‹      larb@14e05000             mediatek,mt8195-smi-larb                àP                ä           ×   Z        ¹                          apb smi gals            �   *           Ù   `      syscon@14f00000           mediatek,mt8195-vppsys1 syscon              ð                 ¬           Œ   W   	               Ù         mutex@14f01000            mediatek,mt8195-vpp-mutex               ð                f      {               Œ   W   	              ¹      '        �   *         larb@14f02000             mediatek,mt8195-smi-larb                ð                 ä           ×   j        ¹                          apb smi gals            �   *           Ù   Š      larb@14f03000             mediatek,mt8195-smi-larb                ð0                ä           ×   [        ¹                          apb smi gals            �   *           Ù   _      display@14f06000              mediatek,mt8195-mdp3-split              ð`                Œ   W   	  `            ¹            +      ,        �   *         display@14f07000              mediatek,mt8195-mdp3-tcc                ðp                Œ   W   	  p            ¹            dma-controller@14f08000           mediatek,mt8195-mdp3-rdma               ð€                Œ   W   	  €            ¤  „  ¨        ¹              Å   k            �   *           Ì         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma               ð�                Œ   W   	  �            ¤  …  ©        ¹      
        Å   k   ¤        �   *           Ì         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma               ð                 Œ   W   	               ¤  †  ª        ¹              Å   Y   À        �   *           Ì         display@14f0b000              mediatek,mt8195-mdp3-fg             ð°                Œ   W   	  °            ¹      	      display@14f0c000              mediatek,mt8195-mdp3-fg             ðÀ                Œ   W   	  À            ¹            display@14f0d000              mediatek,mt8195-mdp3-fg             ðÐ                Œ   W   	  Ð            ¹            display@14f0e000              mediatek,mt8195-mdp3-hdr                ðà                Œ   W   	  à            ¹            display@14f0f000              mediatek,mt8195-mdp3-hdr                ðð                Œ   W   	  ð            ¹            display@14f10000              mediatek,mt8195-mdp3-hdr                ñ                 Œ   W   
               ¹             display@14f11000              mediatek,mt8195-mdp3-aal                ñ                f      i               Œ   W   
              ¹              �   *         display@14f12000              mediatek,mt8195-mdp3-aal                ñ                 f      j               Œ   W   
               ¹              �   *         display@14f13000              mediatek,mt8195-mdp3-aal                ñ0                f      k               Œ   W   
  0            ¹      !        �   *         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ@                Œ   W   
  @            ¤  �  ¯        ¹            display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñP                Œ   W   
  P            ¤  ‘  °        ¹      $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               ñ`                Œ   W   
  `            ¤  ’  ±        ¹      %      display@14f17000              mediatek,mt8195-mdp3-tdshp              ñp                Œ   W   
  p            ¹            display@14f18000              mediatek,mt8195-mdp3-tdshp              ñ€                Œ   W   
  €            ¹      (      display@14f19000              mediatek,mt8195-mdp3-tdshp              ñ�                Œ   W   
  �            ¹      )      display@14f1a000              mediatek,mt8195-mdp3-merge              ñ                 Œ   W   
               ¹              �   *         display@14f1b000              mediatek,mt8195-mdp3-merge              ñ°                Œ   W   
  °            ¹              �   *         display@14f1c000              mediatek,mt8195-mdp3-color              ñÀ                f      t               Œ   W   
  À            ¹              �   *         display@14f1d000              mediatek,mt8195-mdp3-color              ñÐ                Œ   W   
  Ð            f      u               ¹              �   *         display@14f1e000              mediatek,mt8195-mdp3-color              ñà                f      v               Œ   W   
  à            ¹              �   *         display@14f1f000              mediatek,mt8195-mdp3-ovl                ñð                f      w               Œ   W   
  ð            ¹               �   *           Å   k   ¢      display@14f20000              mediatek,mt8195-mdp3-padding                ò                 Œ   W                  ¹              �   *         display@14f21000              mediatek,mt8195-mdp3-padding                ò                Œ   W                 ¹              �   *         display@14f22000              mediatek,mt8195-mdp3-padding                ò                 Œ   W                  ¹              �   *         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò0                Œ   W     0            ¤  Ÿ  «        ¹              Å   k   £        �   *           Ì         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             ò@                Œ   W     @            ¤     ¬        ¹              Å   k   ¦        �   *           Ì         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             òP                Œ   W     P            ¤  ¡  ­        ¹              Å   Y   Â        �   *           Ì         clock-controller@15000000             mediatek,mt8195-imgsys                                ¬           Ù   $      larb@15001000             mediatek,mt8195-smi-larb                                 ä   	        ×   l        ¹   $       $       $   
        apb smi gals            �   *           Ù   Œ      smi@15002000              mediatek,mt8195-smi-sub-common                                ¹   $      $                 apb smi gals0           ×   Z        �   *           Ù   o      smi@15003000              mediatek,mt8195-smi-sub-common               0                ¹   $       $       $   
        apb smi gals0           ×   j        �   *           Ù   l      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                              ¬           Ù   m      larb@15120000             mediatek,mt8195-smi-larb                                 ä   
        ×   l        ¹   $      m            apb smi         �   *           Ù   �      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                               ¬         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe             "                 ¬           Ù   n      larb@15230000             mediatek,mt8195-smi-larb                #                 ä           ×   l        ¹   $      n            apb smi         �   *           Ù   Ž      clock-controller@15330000             mediatek,mt8195-ipesys              3                 ¬           Ù   %      larb@15340000             mediatek,mt8195-smi-larb                4                 ä           ×   o        ¹   %      %           apb smi         �   *           Ù   a      clock-controller@16000000             mediatek,mt8195-camsys                                ¬           Ù   &      larb@16001000             mediatek,mt8195-smi-larb                                 ä           ×   p        ¹   &       &       &           apb smi gals            �   *           Ù   �      larb@16002000             mediatek,mt8195-smi-larb                                  ä           ×   q        ¹   &      &           apb smi         �   *           Ù   b      smi@16004000              mediatek,mt8195-smi-sub-common               @                ¹   &       &       &           apb smi gals0           ×   j        �   *           Ù   p      smi@16005000              mediatek,mt8195-smi-sub-common               P                ¹   &      &                 apb smi gals0           ×   Z        �   *           Ù   q      larb@16012000             mediatek,mt8195-smi-larb                                 ä           ×   q        ¹   r       r            apb smi         �   *            Ù   c      larb@16013000             mediatek,mt8195-smi-larb                0                ä           ×   p        ¹   s       s            apb smi         �   *            Ù   �      larb@16014000             mediatek,mt8195-smi-larb                @                ä           ×   q        ¹   t       t            apb smi         �   *   !        Ù   i      larb@16015000             mediatek,mt8195-smi-larb                P                ä           ×   p        ¹   u       u            apb smi         �   *   !        Ù   •      clock-controller@1604f000             mediatek,mt8195-camsys_rawa             ð                ¬           Ù   r      clock-controller@1606f000             mediatek,mt8195-camsys_yuva             ð                ¬           Ù   s      clock-controller@1608f000             mediatek,mt8195-camsys_rawb             ð                ¬           Ù   t      clock-controller@160af000             mediatek,mt8195-camsys_yuvb             
ð                ¬           Ù   u      clock-controller@16140000             mediatek,mt8195-camsys_mraw                              ¬           Ù   v      larb@16141000             mediatek,mt8195-smi-larb                                ä           ×   p        ¹   &       v       &           apb smi gals            �   *   "        Ù   ”      larb@16142000             mediatek,mt8195-smi-larb                                 ä           ×   q        ¹   v       v            apb smi         �   *   "        Ù   h      clock-controller@17200000             mediatek,mt8195-ccusys                                ¬           Ù   w      larb@17201000             mediatek,mt8195-smi-larb                                 ä           ×   q        ¹   w       w            apb smi         �   *           Ù   d      video-codec@18000000              mediatek,mt8195-vcodec-dec          ¸   X        Å   k                        +                               @                "                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                Å   Y  à   Y  á         ¹      A                  �        sel vdec lat top            M      A        ]      �        �   *         video-codec@10000             mediatek,mtk-vcodec-lat                               f      Ä             0  Å   k      k     k     k     k     k           ¹      A                  �        sel vdec lat top            M      A        ]      �        �   *         video-codec@25000             mediatek,mtk-vcodec-core                 P                f      Ã             P  Å   k      k  ¡   k  ¢   k  £   k  ¤   k  ¥   k  ¦   k  §   k  ¨   k  ©         ¹      A                  �        sel vdec lat top            M      A        ]      �        �   *            larb@1800d000             mediatek,mt8195-smi-larb                 Ð                ä           ×   j        ¹                      apb smi         �   *           Ù   “      larb@1800e000             mediatek,mt8195-smi-larb                 à                ä           ×   x        ¹                     apb smi         �   *           Ù   g      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc              ð                ¬           Ù         larb@1802e000             mediatek,mt8195-smi-larb                à                ä           ×   j        ¹                      apb smi         �   *           Ù   ’      clock-controller@1802f000             mediatek,mt8195-vdecsys             ð                ¬           Ù         larb@1803e000             mediatek,mt8195-smi-larb                à                ä           ×   x        ¹                      apb smi         �   *           Ù   f      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1               ð                ¬           Ù          clock-controller@190f3000             mediatek,mt8195-apusys_pll              0                ¬         clock-controller@1a000000             mediatek,mt8195-vencsys                               ¬           Ù   !      larb@1a010000             mediatek,mt8195-smi-larb                                 ä           ×   j        ¹   !      !           apb smi         �   *           Ù   ‘      video-codec@1a020000              mediatek,mt8195-vcodec-enc                             H  Å   k  `   k  a   k  b   k  c   k  d   k  v   k  w   k  x   k  y        f      U               ¸   X        ¹   !         	  venc_sel            M      @        ]      �        �   *                        +         jpeg-decoder@1a040000             mediatek,mt8195-jpgdec          �   *         0  Å   k  m   k  n   k  r   k  s   k  t   k  u                     +         0  "                                            jpgdec@0,0            mediatek,mt8195-jpgdec-hw                                0  Å   k  m   k  n   k  r   k  s   k  t   k  u        f      W               ¹   !           jpgdec          �   *         jpgdec@0,10000            mediatek,mt8195-jpgdec-hw                               0  Å   k  m   k  n   k  r   k  s   k  t   k  u        f      X               ¹   !           jpgdec          �   *         jpgdec@1,0            mediatek,mt8195-jpgdec-hw                               0  Å   Y  �   Y  Ž   Y  ’   Y  “   Y  ”   Y  •        f      \               ¹   "           jpgdec          �   *            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                 ¬           Ù   "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                 ¦   y               ¬           Œ   y                  Ù         jpeg-encoder@1a030000             mediatek,mt8195-jpgenc          �   *            Å   Y  ‡   Y  ˆ   Y  ‰   Y  Œ                     +         0  "                                            jpgenc@0,0            mediatek,mt8195-jpgenc-hw                                   Å   k  g   k  h   k  i   k  l        f      V               ¹   !           jpgenc          �   *         jpgenc@1,0            mediatek,mt8195-jpgenc-hw                                  Å   Y  ‡   Y  ˆ   Y  ‰   Y  Œ        f      [               ¹   "           jpgenc          �   *            larb@1b010000             mediatek,mt8195-smi-larb                                 ä           ×   Z        ¹   "      "                  apb smi gals            �   *           Ù   e      ovl@1c000000              mediatek,mt8195-disp-ovl                                  f      |               �   *           ¹               Å   k           Œ   y             ports                        +       port@0                 endpoint             port@1                endpoint               z        Ù   {               rdma@1c002000             mediatek,mt8195-disp-rdma                                 f      ~               �   *           ¹              Å   k            Œ   y             ports                        +       port@0                 endpoint               {        Ù   z         port@1                endpoint               |        Ù   }               color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                0                f                     �   *           ¹              Œ   y     0       ports                        +       port@0                 endpoint               }        Ù   |         port@1                endpoint               ~        Ù                  ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                @                f      €               �   *           ¹              Œ   y     @       ports                        +       port@0                 endpoint                       Ù   ~         port@1                endpoint               €        Ù   �               aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                P                f      �               �   *           ¹              Œ   y     P       ports                        +       port@0                 endpoint               �        Ù   €         port@1                endpoint               ‚        Ù   ƒ               gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                `                f      ‚               �   *           ¹              Œ   y     `       ports                        +       port@0                 endpoint               ƒ        Ù   ‚         port@1                endpoint               „        Ù   …               dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither              p                f      ƒ               �   *           ¹      	        Œ   y     p       ports                        +       port@0                 endpoint               …        Ù   „         port@1                endpoint                   dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi              €                f      „               �   *           ¹            *   †        engine digital hs           r   †        ÷dphy          	  vdisabled          dsc@1c009000              mediatek,mt8195-disp-dsc                 �                f      …               �   *           ¹              Œ   y     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              f      Ž               �   *           ¹            +   ‡        engine digital hs           r   ‡        ÷dphy          	  vdisabled          merge@1c014000            mediatek,mt8195-disp-merge              @                f      �               �   *           ¹              Œ   y     @          dp-intf@1c015000              mediatek,mt8195-dp-intf             P                f      ‘               �   *           ¹      ,                    pixel engine pll          	  vdisabled          mutex@1c016000            mediatek,mt8195-disp-mutex              `                f      ’               �   *           ¹              Œ   y     `            ¤  U      larb@1c018000             mediatek,mt8195-smi-larb                €                ä            ×   j        ¹      (      (              apb smi gals            �   *           Ù   ˆ      larb@1c019000             mediatek,mt8195-smi-larb                �                ä           ×   Z        ¹      (                     apb smi gals            �   *           Ù   \      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                               ¦   y              Œ   y                  ¬           z           Ù   #      smi@1c01b000              mediatek,mt8195-smi-common-vdo              °                 ¹      %      &      )      $        apb smi gals0 gals1         �   *           Ù   j      iommu@1c01f000            mediatek,mt8195-iommu-vdo               ð              8  õ   ˆ   ‰   Š   ‹   Œ   �   Ž   �   �   ‘   ’   “   ”   •        f      �               t           ¹      '        bclk            �   *           Ù   k      mutex@1c101000            mediatek,mt8195-disp-mutex                              f      î               �   *           ¹   #           Œ   y                 ¤  À      larb@1c102000             mediatek,mt8195-smi-larb                                 ä           ×   j        ¹   #       #       #           apb smi gals            �   *           Ù   ‰      larb@1c103000             mediatek,mt8195-smi-larb                0                ä           ×   Z        ¹   #      #                  apb smi gals            �   *           Ù   ]      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma               @                f      ï               ¹   #           �   *           Å   k   @        Œ   y     @            Ì         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma               P                f      ð               ¹   #           �   *           Å   Y   `        Œ   y     P            Ì         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma               `                f      ñ               ¹   #           �   *           Å   k   A        Œ   y     `            Ì         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma               p                f      ò               ¹   #           �   *           Å   Y   a        Œ   y     p            Ì         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma               €                f      ó               ¹   #           �   *           Å   k   B        Œ   y     €            Ì         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma               �                f      ô               ¹   #           �   *           Å   Y   b        Œ   y     �            Ì         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma                                f      õ               ¹   #           �   *           Å   k   C        Œ   y                  Ì         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma               °                f      ö               ¹   #           �   *           Å   Y   c        Œ   y     °            Ì         vpp-merge@1c10c000            mediatek,mt8195-disp-merge              À                f      ÷               ¹   #   	   #           merge merge_async           �   *           Œ   y     À                     ¿   #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge              Ð                f      ø               ¹   #   
   #           merge merge_async           �   *           Œ   y     Ð                     ¿   #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge              à                f      ù               ¹   #      #           merge merge_async           �   *           Œ   y     à                     ¿   #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge              ð                f      ú               ¹   #      #           merge merge_async           �   *           Œ   y     ð                     ¿   #         vpp-merge@1c110000            mediatek,mt8195-disp-merge                               f      û               ¹   #      #           merge merge_async           �   *           Œ   y                   (        ¿   #         dpi@1c112000              mediatek,mt8195-dpi                              ¹   #   -   #      #   2        pixel engine pll            f                      �   *           ¿   #         	  vdisabled       ports                        +       port@0                 endpoint             port@1                endpoint                   dp-intf@1c113000              mediatek,mt8195-dp-intf             0                f                     �   *           ¹   #   /   #                 pixel engine pll          	  vdisabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p      @            P            p            �                         °            À              4  ‡mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  Œ   y     @       y     P       y     p       y     �       y             y     °       y     À          h  ¹   #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *            ƒ  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          �   *           Å   Y   d   Y   e        f                   (  ¿   #   3   #   4   #   5   #   6   #   7      E  Ævdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          hdmi-tx@1c300000              mediatek,mt8195-hdmi-tx         ?               0                  ¹      Q      L      M      ,        bus hdcp hdcp24m hdmi-split         M      L        ]      “        f      ¥               �   *           r   –        ÷hdmi          	  vdisabled       i2c           mediatek,mt8195-hdmi-ddc            ¹         ports                        +       port@0                 endpoint             port@1                endpoint                   edp-tx@1c500000           mediatek,mt8195-edp-tx              P        €         ü   —        dp_calibration_data         �   *           f      ¤               P  ¤      	  vdisabled          dp-tx@1c600000            mediatek,mt8195-dp-tx               `        €         ü   —        dp_calibration_data         �   *           f      Ê               P  ¤      	  vdisabled             thermal-zones      cpu0-thermal            a  è        o   ú        …   ˜      trips      trip-alert          • L        ¡  Ð        passive         Ù   ™      trip-crit           • †         ¡  Ð      	  critical             cooling-maps       map0            ¬   ™      0  ±   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            a  è        o   ú        …   ˜      trips      trip-alert          • L        ¡  Ð        passive         Ù   š      trip-crit           • †         ¡  Ð      	  critical             cooling-maps       map0            ¬   š      0  ±   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            a  è        o   ú        …   ˜      trips      trip-alert          • L        ¡  Ð        passive         Ù   ›      trip-crit           • †         ¡  Ð      	  critical             cooling-maps       map0            ¬   ›      0  ±   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            a  è        o   ú        …   ˜      trips      trip-alert          • L        ¡  Ð        passive         Ù   œ      trip-crit           • †         ¡  Ð      	  critical             cooling-maps       map0            ¬   œ      0  ±   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            a  è        o   ú        …   ˜       trips      trip-alert          • L        ¡  Ð        passive         Ù   �      trip-crit           • †         ¡  Ð      	  critical             cooling-maps       map0            ¬   �      0  ±   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            a  è        o   ú        …   ˜      trips      trip-alert          • L        ¡  Ð        passive         Ù   ž      trip-crit           • †         ¡  Ð      	  critical             cooling-maps       map0            ¬   ž      0  ±   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            a  è        o   ú        …   ˜      trips      trip-alert          • L        ¡  Ð        passive         Ù   Ÿ      trip-crit           • †         ¡  Ð      	  critical             cooling-maps       map0            ¬   Ÿ      0  ±   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            a  è        o   ú        …   ˜      trips      trip-alert          • L        ¡  Ð        passive         Ù          trip-crit           • †         ¡  Ð      	  critical             cooling-maps       map0            ¬          0  ±   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            a  è        o   ú        …   ¡      trips      trip-alert          • L        ¡  Ð        passive       trip-crit           • †         ¡  Ð      	  critical                vpu1-thermal            a  è        o   ú        …   ¡   	   trips      trip-alert          • L        ¡  Ð        passive       trip-crit           • †         ¡  Ð      	  critical                gpu-thermal         a  è        o   ú        …   ¡   
   trips      trip-alert          • L        ¡  Ð        passive       trip-crit           • †         ¡  Ð      	  critical                gpu1-thermal            a  è        o   ú        …   ¡      trips      trip-alert          • L        ¡  Ð        passive       trip-crit           • †         ¡  Ð      	  critical                vdec-thermal            a  è        o   ú        …   ¡      trips      trip-alert          • L        ¡  Ð        passive       trip-crit           • †         ¡  Ð      	  critical                img-thermal         a  è        o   ú        …   ¡      trips      trip-alert          • L        ¡  Ð        passive       trip-crit           • †         ¡  Ð      	  critical                infra-thermal           a  è        o   ú        …   ¡      trips      trip-alert          • L        ¡  Ð        passive       trip-crit           • †         ¡  Ð      	  critical                cam0-thermal            a  è        o   ú        …   ¡      trips      trip-alert          • L        ¡  Ð        passive       trip-crit           • †         ¡  Ð      	  critical                cam1-thermal            a  è        o   ú        …   ¡      trips      trip-alert          • L        ¡  Ð        passive       trip-crit           • †         ¡  Ð      	  critical                   chosen          Àserial0:921600n8          memory@40000000          ümemory              @       €            	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 dpi1 gce0 gce1 hdmi0 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-pull-up drive-strength drive-strength-microamp bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 #io-channel-cells nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup freq-table-hz mediatek,ufs-disable-mcq usb2-lpm-disable bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-max-frequency bits #phy-cells mediatek,ibias mediatek,ibias_up operating-points-v2 power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en #sound-dai-cells max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path 