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:disabledportsport@0TendpointxO┬Wport@1TendpointxP┬[vdoa@21e4000!fsl,imx6q-vdoaT@@Aйserial@21e8000!fsl,imx6q-uartfsl,imx21-uartT─@A═║Hipgper ]brxtx:okayldefaultzQserial@21ec000!fsl,imx6q-uartfsl,imx21-uartTю@A═║Hipgper ]brxtx :disabledserial@21f0000!fsl,imx6q-uartfsl,imx21-uartT@A═║Hipgper ] brxtx :disabledserial@21f4000!fsl,imx6q-uartfsl,imx21-uartT@@A═║Hipgper ]!"brxtx:okayldefaultzRi2c@21f8000!fsl,imx6q-i2cfsl,imx21-i2cT─@#At :disabledipu@2400000!fsl,imx6q-ipuT@@A┌┐└Hbusdi0di1д port@0T┬bendpointxS┬)port@1TldefaultzT┬cendpointxUv┬/port@2T┬dendpoint@0Tendpoint@1TxV┬endpoint@2TxW┬Oendpoint@3TxX┬endpoint@4TxY┬port@3T┬eendpoint@0Tendpoint@1TxZ┬ endpoint@2Tx[┬Pendpoint@3Tx\┬endpoint@4Tx]┬sram@900000 !mmio-sramT░░A▌┬cpuscpu@0!arm,cortex-a9"cpuT^)2═пюМь Ю▄0:2═МьюМь ЮМьSНl·(Ah╙)Harmpll2_pfd2_396msteppll1_swpll1_sysa_l#v`єa╟speed_gradecpu@1!arm,cortex-a9"cpuT^)2═пюМь Ю▄0:2═МьюМь ЮМьSНl·(Ah╙)Harmpll2_pfd2_396msteppll1_swpll1_sysa_l#v`capture-subsystem!fsl,imx-capture-subsystem│bcdisplay-subsystem!fsl,imx-display-subsystem│debacklight!pwm-backlight┤fLK@ ▄ @─Ъ·gpio-keys !gpio-keyskey-user-pb└user_pb│gЇkey-user-pb1x └user_pb1xЇР?key-erased└key-erasedЇР?key-eeprom-wp └eeprom_wpЇР?key-tamper└tamperЇР?key-switch-hold└switch_holdЇР?leds !gpio-ledsldefaultzhled-user1└user1│iбon пheartbeatled-user2└user2│iбoffled-user3└user3│iбoffmemory@10000000"memoryT@pps !pps-gpioldefaultzj│:okayregulator-1p0v!regulator-fixed\1P0VkB@┐B@⌡regulator-3p3v!regulator-fixed\3P3Vk2Z═┐2Z═⌡┬=regulator-can1-stby!regulator-fixedldefaultzk \can1_stbyik2Z═┐2Z═┬regulator-usb-h1-vbus!regulator-fixed\usb_h1_vbuskLK@┐LK@⌡┬5regulator-usb-otg-vbus!regulator-fixed \usb_otg_vbuskLK@┐LK@iDФ┬2sound2!fsl,imx6q-ventana-sgtl5000fsl,imx-audio-sgtl5000sgtl5000-audioЫl m8 MIC_INMic JackMic JackMic BiasHeadphone JackHP_OUT " / #address-cells#size-cellsmodelcompatiblebootargsethernet0can0can1gpio0gpio1gpio2gpio3gpio4gpio5gpio6i2c0i2c1i2c2ipu0mmc0mmc1mmc2mmc3serial0serial1serial2serial3serial4spi0spi1spi2spi3usb0usb1usb2usb3usbphy0usbphy1i2c3led0led1led2nandssi0#clock-cellsclock-frequencygprstatusclocksclock-namesregfsl,data-mappingfsl,data-widthremote-endpointphandlenative-modehactivevactivehback-porchhfront-porchvback-porchvfront-porchhsync-lenvsync-leninterrupt-parentinterrupts#phy-cellsrangesbootph-all#dma-cellsdma-channelsreg-namesinterrupt-namesdmasdma-namespinctrl-namespinctrl-0ddc-i2c-buspower-domains#cooling-cells#interrupt-cellsinterrupt-controllercache-unifiedcache-levelarm,tag-latencyarm,data-latencyarm,shared-overridedevice_typebus-rangenum-lanesinterrupt-map-maskinterrupt-mapreset-gpiobootph-pre-ramrts-gpios#sound-dai-cellsfsl,fifo-depthfsl,asrc-ratefsl,asrc-widthresetsiram#pwm-cellsfsl,stop-modexceiver-supplygpio-controller#gpio-cellsgpio-rangesfsl,ext-reset-outputassigned-clocksassigned-clock-parentsregulator-nameregulator-min-microvoltregulator-max-microvoltregulator-always-onanatop-reg-offsetanatop-vol-bit-shiftanatop-vol-bit-widthanatop-min-bit-valanatop-min-voltageanatop-max-voltageanatop-enable-bitanatop-delay-reg-offsetanatop-delay-bit-shiftanatop-delay-bit-widthregulator-enable-ramp-delayfsl,tempmonnvmem-cellsnvmem-cell-names#thermal-sensor-cellsphy-3p0-supplyfsl,anatopregmapvaluelinux,keycodewakeup-source#reset-cells#power-domain-cellspower-supply#mux-control-cellsmux-reg-masksmux-controlsbus-widthfsl,pinsfsl,sdma-ram-script-namefsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dwordvbus-supplydisable-over-currentdr_modephy_type#index-cellsphy-modephy-reset-gpiospinctrl-1pinctrl-2cd-gpiosvmmc-supplyno-1-8-vgw,modelabelpagesizelltc,fb-voltage-dividerregulator-ramp-delayregulator-boot-onVDDA-supplyVDDIO-supplywakeup-gpiospowerdown-gpiosfsl,weim-cs-gprnext-level-cacheoperating-pointsfsl,soc-operating-pointsclock-latencyarm-supplypu-supplysoc-supplyportspwmsbrightness-levelsdefault-brightness-levellinux,codedefault-statelinux,default-triggerenable-active-highssi-controlleraudio-codecaudio-routingmux-int-portmux-ext-port