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@disabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d210000]! 2 @disabledmailbox@5d280000]( 2!clock-controller@5d4000002fsl,imx8qxp-lpcg]@4Ghpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clk2yclock-controller@5d4100002fsl,imx8qxp-lpcg]A4Ghpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clk2zclock-controller@5d4200002fsl,imx8qxp-lpcg]B4Ghpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clk2{clock-controller@5d4300002fsl,imx8qxp-lpcg]C4Ghpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clk2|clock-controller@5d4400002fsl,imx8qxp-lpcg]D4Ghpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clk2clock-controller@5d4500002fsl,imx8qxp-lpcg]E4Ghpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clk2clock-controller@5d4600002fsl,imx8qxp-lpcg]F4Ghpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clk2clock-controller@5d4700002fsl,imx8qxp-lpcg]G4Ghpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clk2clock-conn-enet0-root 2fixed-clock沀conn_enet0_root_clktclock-dummy 2fixed-clock clk_dummychosen/bus@5a000000/serial@5a060000memory@80000000memory@regulator-m2uart1sel2regulator-fixed%2Z=2Z &m2_uart1_sel 5i:Mregulator-02regulator-fixed%2Z=2Z&mux3_en 5Mregulator-12regulator-fixed &fec1_supply%2Z=2Z 5i M @disabledregulator-22regulator-fixed&fec1_io_supply%w@=w@ 5:M @disabledregulator-42regulator-fixed &mii-select%2Z=2Z 5:MVregulator-52regulator-fixed &can1-stby%2Z=2Z 5:Xregulator-32regulator-fixed &SD1_SPWR%-=- 5:a bregulator-adc-vref2regulator-fixed &vref_1v8%w@=w@R interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0ethernet1gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7mu1i2c2mmc0mmc1serial0serial1serial6device_typeregenable-methodnext-level-cacheclocks#cooling-cellsoperating-points-v2phandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterruptsrangesno-mapreusablesizealloc-rangeslinux,cma-defaultmbox-namesmboxes#power-domain-cells#clock-cellsgpio-controller#gpio-cellspinctrl-namespinctrl-0fsl,pinslinux,keycodeswakeup-sourcetimeout-sec#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceclock-frequencyclock-output-namesclock-namesassigned-clocksassigned-clock-ratespower-domainsstatusclock-indicesdmasdma-namesfsl,asrc-ratefsl,asrc-widthfsl,asrc-clk-map#dma-cellsdma-channelsdma-channel-maskmemory-regiondaisfsl,spi-only-use-cs1-selspi-max-frequency#pwm-cells#io-channel-cellsvref-supplyfsl,clk-sourcefsl,scu-indexxceiver-supplyfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dwordsrp-disablehnp-disableadp-disablepower-active-highdisable-over-current#index-cellsfsl,tx-d-calbus-widthno-sdno-sdionon-removablefsl,tuning-start-tapfsl,tuning-stepvmmc-supplycd-gpioswp-gpiosfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetrx-internal-delay-psnvmem-cellsnvmem-cell-namesreset-gpiosreset-assert-usqca,disable-smarteeevddio-supplyregulator-min-microvoltregulator-max-microvoltinterrupt-nameseee-broken-1000tqca,disable-hibernation-modereset-deassert-usreg-namesphysphy-namescdns,on-chip-buff-size#phy-cellsgpio-rangesspi-tx-bus-widthspi-rx-bus-width#mbox-cellsstdout-pathregulator-namegpioenable-active-highregulator-always-onoff-on-delay-us