  @   8  8   (                                                                                     ,Freescale i.MX8QM MEK            2fsl,imx8qm-mek fsl,imx8qm      aliases          =/bus@5b000000/mmc@5b010000           B/bus@5b000000/mmc@5b020000           G/bus@5b000000/mmc@5b030000           L/bus@5a000000/serial@5a060000            T/bus@5a000000/serial@5a070000            \/bus@5a000000/serial@5a080000            d/bus@5a000000/serial@5a090000             l/vpu@2c000000/vpu-core@2d080000           v/vpu@2c000000/vpu-core@2d090000           /vpu@2c000000/vpu-core@2d0a0000       cpus                                 cpu@0            cpu          2arm,cortex-a53                                               psci                            @                                    @                                          ,           ;         cpu@1            cpu          2arm,cortex-a53                                              psci                            @                                    @                                          ,           ;   	      cpu@2            cpu          2arm,cortex-a53                                              psci                            @                                    @                                          ,           ;   
      cpu@3            cpu          2arm,cortex-a53                                              psci                            @                                    @                                          ,           ;         l2-cache0            2cache           C            O                        @                    ;         l2-cache1            2cache           C            O                        @                     opp-table-0          2operating-points-v2          ]        ;      opp-600000000           h    #F         o         } I      opp-896000000           h    5g         o B@        } I      opp-1104000000          h    Aʹ         o         } I      opp-1200000000          h    G         o         } I                  opp-table-1          2operating-points-v2          ]   opp-600000000           h    #F         o B@        } I      opp-1056000000          h    >H         o B@        } I      opp-1296000000          h    M?d         o         } I      opp-1596000000          h    _!         o         } I                  interrupt-controller@51a00000            2arm,gic-v3        P       Q             Q             R               R             R                                           	                        ;         pmu          2arm,armv8-pmuv3                        psci             2arm,psci-1.0             smc       timer            2arm,armv8-timer       0                                   
         iommu@51400000           2arm,mmu-500                           Q@                                                                                                                                                                                                                                                                                                                                                                                                                         ;   7      system-controller            2fsl,imx-scu         tx0 rx0 gip3          $                                   power-controller             2fsl,imx8qm-scu-pd fsl,scu-pd                       ;         clock-controller             2fsl,imx8qm-clk fsl,scu-clk                     ;         pinctrl          2fsl,imx8qm-iomuxc           ;   K   i2c1grp                 L        L        ;   &      i2c1gpio-grp                    L        L        ;   '      adc0grp                  `        ;   ,      fec1grp                                                                                                                                                             ;   ?      lpspi2grp         $     z      @   {      @   |      @        ;         lpspi2csgrp            }      !        ;         flexspi0grp                  !         !         !         !         !         !         !         !         !         !         !         !         !         !         !         !        ;   L      lpuart0grp                                      ;         lpuart2grp                                    ;         lpuart3grp                                    ;   !      usdhc1grp                    A          !          !          !          !          !          !          !          !          !          A        ;   8      usdhc2grp         T           A          !          !          !          !          !          !        ;   :         rtc          2fsl,imx8qxp-sc-rtc        thermal-sensor        *   2fsl,imx8qxp-sc-thermal fsl,imx-sc-thermal           '           ;            thermal-zones      cpu0-thermal            =           S          a          trips      trip0           q         }           passive         ;         trip1           q         }        	   critical             cooling-maps       map0                     0        	   
               gpu0-thermal            =           S          a         trips      trip0           q         }           passive       trip1           q         }        	   critical                gpu1-thermal            =           S          a         trips      trip0           q         }           passive       trip1           q         }        	   critical                drc0-thermal            =           S          a         trips      trip0           q         }           passive       trip1           q         }        	   critical                   vpu@2c000000                                     ,       ,                   ,                             	  disabled       mailbox@2d000000             2fsl,imx6sx-mu            -                                                     	  disabled            ;         mailbox@2d020000             2fsl,imx6sx-mu            -                                                    	  disabled            ;         mailbox@2d040000             2fsl,imx6sx-mu            -                                                    	  disabled            ;         vpu-core@2d080000            -              2nxp,imx8q-vpu-decoder                        tx0 tx1 rx        $                                       	  disabled          vpu-core@2d090000            -	              2nxp,imx8q-vpu-encoder                        tx0 tx1 rx        $                                       	  disabled          vpu-core@2d0a0000            -
              2nxp,imx8q-vpu-encoder                        tx0 tx1 rx        $                                       	  disabled             clock-img-ipg            2fixed-clock                              img_ipg_clk         ;         bus@58000000             2simple-bus                                   X       X         jpegdec@58400000             X@                   5                                                                                            %   2nxp,imx8qm-jpgdec nxp,imx8qxp-jpgdec          jpegenc@58450000             XE                   1                                                                                            %   2nxp,imx8qm-jpgenc nxp,imx8qxp-jpgenc          clock-controller@585d0000            2fsl,imx8qxp-lpcg             X]                                                    0  img_jpeg_dec_lpcg_clk img_jpeg_dec_lpcg_ipg_clk                      ;         clock-controller@585f0000            2fsl,imx8qxp-lpcg             X_                                                    0  img_jpeg_enc_lpcg_clk img_jpeg_enc_lpcg_ipg_clk                      ;            clock-dma-ipg            2fixed-clock                     '         dma_ipg_clk         ;   #      bus@5a000000             2simple-bus                                   Z       Z         spi@5a000000             2fsl,imx7ulp-spi          Z                                              P                                              per ipg               5                          5      	  disabled          spi@5a010000             2fsl,imx7ulp-spi          Z                                             Q                                              per ipg               6                          6      	  disabled          spi@5a020000             2fsl,imx7ulp-spi          Z                                             R                                              per ipg               7                          7        okay            +default         9              C      
      spi@0                         2rohm,dh2228fv           LÀ         spi@5a030000             2fsl,imx7ulp-spi          Z                                             S                                              per ipg               8                          8      	  disabled          serial@5a060000          Z                   Y                               	  ipg baud                  9           Ĵ               9        ^rx tx            h                                   okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            +default         9         serial@5a070000          Z                   Z                               	  ipg baud                  :           Ĵ               :        ^rx tx            h                                 	  disabled          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart          serial@5a080000          Z                   [                               	  ipg baud                  ;           Ĵ               ;        ^rx tx            h                                   okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            +default         9         serial@5a090000          Z	                   \                                 	  ipg baud                  <           Ĵ               <        ^rx tx            h                                   okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            +default         9   !      pwm@5a190000             2fsl,imx8qxp-pwm fsl,imx27-pwm            Z                                   "      "            ipg per                          n6         m                       dma-controller@5a1f0000          2fsl,imx8qm-edma          Z             x                                                                                                                                                                                                                                                 @      A      B      C      D      E      F      G      H      I      J      K      L      M      N      O      P      Q      R      S      T      U                   okay            ;         clock-controller@5a400000            2fsl,imx8qxp-lpcg             Z@                               5      #                        spi0_lpcg_clk spi0_lpcg_ipg_clk               5        ;         clock-controller@5a410000            2fsl,imx8qxp-lpcg             ZA                               6      #                        spi1_lpcg_clk spi1_lpcg_ipg_clk               6        ;         clock-controller@5a420000            2fsl,imx8qxp-lpcg             ZB                               7      #                        spi2_lpcg_clk spi2_lpcg_ipg_clk               7        ;         clock-controller@5a430000            2fsl,imx8qxp-lpcg             ZC                               8      #                        spi3_lpcg_clk spi3_lpcg_ipg_clk               8        ;         clock-controller@5a460000            2fsl,imx8qxp-lpcg             ZF                               9      #                     '  uart0_lpcg_baud_clk uart0_lpcg_ipg_clk                9        ;         clock-controller@5a470000            2fsl,imx8qxp-lpcg             ZG                               :      #                     '  uart1_lpcg_baud_clk uart1_lpcg_ipg_clk                :        ;         clock-controller@5a480000            2fsl,imx8qxp-lpcg             ZH                               ;      #                     '  uart2_lpcg_baud_clk uart2_lpcg_ipg_clk                ;        ;         clock-controller@5a490000            2fsl,imx8qxp-lpcg             ZI                               <      #                     '  uart3_lpcg_baud_clk uart3_lpcg_ipg_clk                <        ;          clock-controller@5a590000            2fsl,imx8qxp-lpcg             ZY                                     #                     (  adma_pwm_lpcg_clk adma_pwm_lpcg_ipg_clk                       ;   "      i2c@5a800000             Z    @                               $       $           per ipg               `           n6               `      	  disabled          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c        i2c@5a810000             Z    @                               %       %           per ipg               a           n6               a        okay          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c                                             +default gpio            9   &           '           (                  (             i2c@5a820000             Z    @                               )       )           per ipg               b           n6               b      	  disabled          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c        i2c@5a830000             Z    @                               *       *           per ipg               c           n6               c      	  disabled          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c        adc@5a880000             2nxp,imx8qxp-adc                     Z                                                +       +           per ipg               e           n6               e        okay            +default         9   ,           -      adc@5a890000             2nxp,imx8qxp-adc                     Z                                                .       .           per ipg               f           n6               f      	  disabled          can@5a8d0000             2fsl,imx8qm-flexcan           Z                                                /      /            ipg per               i           bZ               i                             	  disabled          can@5a8e0000             2fsl,imx8qm-flexcan           Z                                                0      0            ipg per               j           bZ               j                            	  disabled          can@5a8f0000             2fsl,imx8qm-flexcan           Z                                                1      1            ipg per               k           bZ               k                            	  disabled          dma-controller@5a9f0000          2fsl,imx8qm-edma          Z   !          x              
      x                                                                                                  P        l      m      n      o      p      q      r      s      t      u      clock-controller@5ac00000            2fsl,imx8qxp-lpcg             Z                               `      #                        i2c0_lpcg_clk i2c0_lpcg_ipg_clk               `        ;   $      clock-controller@5ac10000            2fsl,imx8qxp-lpcg             Z                               a      #                        i2c1_lpcg_clk i2c1_lpcg_ipg_clk               a        ;   %      clock-controller@5ac20000            2fsl,imx8qxp-lpcg             Z                               b      #                        i2c2_lpcg_clk i2c2_lpcg_ipg_clk               b        ;   )      clock-controller@5ac30000            2fsl,imx8qxp-lpcg             Z                               c      #                        i2c3_lpcg_clk i2c3_lpcg_ipg_clk               c        ;   *      clock-controller@5ac80000            2fsl,imx8qxp-lpcg             Z                               e      #                        adc0_lpcg_clk adc0_lpcg_ipg_clk               e        ;   +      clock-controller@5ac90000            2fsl,imx8qxp-lpcg             Z                               f      #                        adc1_lpcg_clk adc1_lpcg_ipg_clk               f        ;   .      clock-controller@5acd0000            2fsl,imx8qxp-lpcg             Z                               i      #   #                        5  can0_lpcg_pe_clk can0_lpcg_ipg_clk can0_lpcg_chi_clk                  i        ;   /      clock-controller@5a4a0000            2fsl,imx8qxp-lpcg             ZJ                               =      #                     '  uart4_lpcg_baud_clk uart4_lpcg_ipg_clk                =      i2c@5a840000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           Z    @               X                            2       2           per ipg               d           n6               d      	  disabled          clock-controller@5ac40000            2fsl,imx8qxp-lpcg             Z                               d      #                        i2c4_lpcg_clk i2c4_lpcg_ipg_clk               d        ;   2      clock-controller@5ace0000            2fsl,imx8qxp-lpcg             Z                               j      #   #                        5  can1_lpcg_pe_clk can1_lpcg_ipg_clk can1_lpcg_chi_clk                  j        ;   0      clock-controller@5acf0000            2fsl,imx8qxp-lpcg             Z                               k      #   #                        5  can2_lpcg_pe_clk can2_lpcg_ipg_clk can2_lpcg_chi_clk                  k        ;   1         clock-conn-axi           2fixed-clock                     CU        conn_axi_clk            ;   E      clock-conn-ahb           2fixed-clock                     	!        conn_ahb_clk            ;   F      clock-conn-ipg           2fixed-clock                             conn_ipg_clk            ;   D      bus@5b000000             2simple-bus                                   [       [         usb@5b0d0000          -   2fsl,imx7ulp-usb fsl,imx6ul-usb fsl,imx27-usb             [                                              3           4                5                       "           6                      	  disabled          usbmisc@5b0d0200            J         8   2fsl,imx7ulp-usbmisc fsl,imx7d-usbmisc fsl,imx6q-usbmisc          [            ;   4      usbphy@5b100000          2fsl,imx7ulp-usbphy           [                 5                      	  disabled            ;   3      mmc@5b010000                               [                 6      6      6            ipg ahb per                       okay          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc          W   7             +default         9   8        ^            h         n         v      mmc@5b020000                               [                 9      9      9            ipg ahb per                                             okay          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc          W   7             +default         9   :        ^              ;           <                 <             mmc@5b030000                               [                 =      =      =            ipg ahb per                     	  disabled          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc          W   7           ethernet@5b040000            [           0                                                    >      >      >      >            ipg ahb enet_clk_ref ptp                                      沀sY@                                            okay             2fsl,imx8qm-fec fsl,imx6sx-fec           W   7             +default         9   ?      	  rgmii-id               @            mdio                                 ethernet-phy@0           2ethernet-phy-ieee802.3-c22                       ;   @      ethernet-phy@1           2ethernet-phy-ieee802.3-c22                          ethernet@5b050000            [           0                                                   A      A      A      A            ipg ahb enet_clk_ref ptp                                      沀sY@                                          	  disabled             2fsl,imx8qm-fec fsl,imx6sx-fec           W   7           usb@5b110000             2fsl,imx8qm-usb3          [                                             (      B      B       B      B      B           lpm bus aclk ipg core                           沀                   	  disabled       usb@5b120000          
   2cdns,usb3            [     [     [             otg xhci dev                       0                                              host peripheral otg wakeup          *   C        /cdns3,usb3-phy          9         	  disabled             usb-phy@5b160000             2nxp,salvo-phy            [                 B           salvo_phy_clk                        P          	  disabled            ;   C      clock-controller@5b200000            2fsl,imx8qxp-lpcg             [                                      D   E                        9  sdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk                          ;   6      clock-controller@5b210000            2fsl,imx8qxp-lpcg             [!                                     D   E                        9  sdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk                          ;   9      clock-controller@5b220000            2fsl,imx8qxp-lpcg             ["                                     D   E                        9  sdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk                          ;   =      clock-controller@5b230000            2fsl,imx8qxp-lpcg             [#                      0                        E            D   D                                   enet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk                          ;   >      clock-controller@5b240000            2fsl,imx8qxp-lpcg             [$                      0                        E            D   D                                   enet1_lpcg_timer_clk enet1_lpcg_txc_sampling_clk enet1_lpcg_ahb_clk enet1_lpcg_rgmii_txc_clk enet1_lpcg_ipg_clk enet1_lpcg_ipg_s_clk                          ;   A      clock-controller@5b270000            2fsl,imx8qxp-lpcg             ['                            F   D                    "  usboh3_ahb_clk usboh3_phy_ipg_clk                        ;   5      clock-controller@5b280000            2fsl,imx8qxp-lpcg             [(                                                 0                      D   D   D              M  usb3_app_clk usb3_lpm_clk usb3_ipg_clk usb3_core_pclk usb3_phy_clk usb3_aclk                         ;   B         clock-lsio-bus           2fixed-clock                              lsio_bus_clk            ;   M      bus@5d000000             2simple-bus                                    ]       ]                      pwm@5d000000             2fsl,imx27-pwm            ]              ipg per             G      G                            n6         m                  ^         	  disabled          pwm@5d010000             2fsl,imx27-pwm            ]             ipg per             H      H                            n6         m                  _         	  disabled          pwm@5d020000             2fsl,imx27-pwm            ]             ipg per             I      I                            n6         m                  `         	  disabled          pwm@5d030000             2fsl,imx27-pwm            ]             ipg per             J      J                            n6         m                  a         	  disabled          gpio@5d080000            ]                                [        k                                              2fsl,imx8qm-gpio fsl,imx35-gpio        0  w   K              K            K      $           ;   (      gpio@5d090000            ]	                                [        k                                              2fsl,imx8qm-gpio fsl,imx35-gpio        @  w   K       (      K      2      K      ?      K      H         gpio@5d0a0000            ]
                                [        k                                              2fsl,imx8qm-gpio fsl,imx35-gpio        0  w   K       P      K      U      K      h   
      gpio@5d0b0000            ]                                [        k                                              2fsl,imx8qm-gpio fsl,imx35-gpio          w   K       r      K      u      K            K            K            K            K            K            K            K            K            K                 ;         gpio@5d0c0000            ]                                [        k                                              2fsl,imx8qm-gpio fsl,imx35-gpio        `  w   K             K            K            K            K            K                 ;   N      gpio@5d0d0000            ]                                [        k                                              2fsl,imx8qm-gpio fsl,imx35-gpio          w   K             K            K            K            K            K            K            K                 ;   <      gpio@5d0e0000            ]                                [        k                                              2fsl,imx8qm-gpio fsl,imx35-gpio           w   K          
   K   
            gpio@5d0f0000            ]                                [        k                                              2fsl,imx8qm-gpio fsl,imx35-gpio        spi@5d120000                                       2nxp,imx8qxp-fspi             ]                   fspi_base fspi_mmap                \                                      fspi_en fspi                          okay            +default         9   L   flash@0                                                2jedec,spi-nor           Lk@                               mailbox@5d1b0000             ]                                        	  disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d1c0000             ]                                        ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu         ;         mailbox@5d1d0000             ]                                        	  disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d1e0000             ]                                        	  disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d1f0000             ]                                        	  disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d200000             ]                                                       	  disabled             2fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d210000             ]!                                                      	  disabled             2fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d280000             ](                                                         2fsl,imx8qm-mu fsl,imx6sx-mu       clock-controller@5d400000            2fsl,imx8qxp-lpcg             ]@                      4                                 M                                       h  pwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk                       ;   G      clock-controller@5d410000            2fsl,imx8qxp-lpcg             ]A                      4                                 M                                       h  pwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk                       ;   H      clock-controller@5d420000            2fsl,imx8qxp-lpcg             ]B                      4                                 M                                       h  pwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk                       ;   I      clock-controller@5d430000            2fsl,imx8qxp-lpcg             ]C                      4                                 M                                       h  pwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk                       ;   J      clock-controller@5d440000            2fsl,imx8qxp-lpcg             ]D                      4                                 M                                       h  pwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk                     clock-controller@5d450000            2fsl,imx8qxp-lpcg             ]E                      4                                 M                                       h  pwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk                     clock-controller@5d460000            2fsl,imx8qxp-lpcg             ]F                      4                                 M                                       h  pwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk                     clock-controller@5d470000            2fsl,imx8qxp-lpcg             ]G                      4                                 M                                       h  pwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk                        chosen          /bus@5a000000/serial@5a060000         memory@80000000          memory                      @         usdhc2-vmmc          2regulator-fixed       	  SD1_SPWR             -         -           N                        ;   ;      regulator-adc-vref           2regulator-fixed       	  vref_1v8             w@         w@        ;   -         	interrupt-parent #address-cells #size-cells model compatible mmc0 mmc1 mmc2 serial0 serial1 serial2 serial3 vpu-core0 vpu-core1 vpu-core2 device_type reg clocks enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache operating-points-v2 #cooling-cells phandle cache-level cache-unified opp-shared opp-hz opp-microvolt clock-latency-ns opp-suspend #interrupt-cells interrupt-controller interrupts #global-interrupts #iommu-cells mbox-names mboxes #power-domain-cells #clock-cells fsl,pins #thermal-sensor-cells polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device ranges power-domains status #mbox-cells clock-frequency clock-output-names assigned-clocks assigned-clock-rates slot clock-indices clock-names pinctrl-names pinctrl-0 cs-gpios spi-max-frequency dma-names dmas #pwm-cells #dma-cells dma-channels dma-channel-mask pinctrl-1 scl-gpios sda-gpios #io-channel-cells vref-supply fsl,clk-source fsl,scu-index fsl,usbphy fsl,usbmisc ahb-burst-config tx-burst-size-dword rx-burst-size-dword #index-cells iommus bus-width no-sd no-sdio non-removable fsl,tuning-start-tap fsl,tuning-step vmmc-supply cd-gpios wp-gpios fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle fsl,magic-packet reg-names interrupt-names phys phy-names cdns,on-chip-buff-size #phy-cells gpio-controller #gpio-cells gpio-ranges spi-tx-bus-width spi-rx-bus-width stdout-path regulator-name regulator-min-microvolt regulator-max-microvolt gpio enable-active-high 