     8     (                                                 xiaomi,ax3000t mediatek,mt7981b                                  +            7Xiaomi AX3000T     cpus                         +       cpu@0             arm,cortex-a53           =             Acpu          Mpsci          cpu@1             arm,cortex-a53           =            Acpu          Mpsci             oscillator-40m            fixed-clock          [bZ          kclkxtal          ~          psci              arm,psci-1.0             Tsmc       soc           simple-bus                                 +      interrupt-controller@c000000              arm,gic-v3            =                                                       	                                           clock-controller@10001000              mediatek,mt7981-infracfg syscon          =                      ~                     clock-controller@1001b000              mediatek,mt7981-topckgen syscon          =                     ~         clock-controller@1001e000             mediatek,mt7981-apmixedsys           =                     ~         pwm@10048000              mediatek,mt7981-pwm          =                  (                                          top main pwm1 pwm2 pwm3                   clock-controller@15000000             mediatek,mt7981-ethsys syscon            =                       ~                        timer             arm,armv8-timer                   0                                    
         memory@40000000          =    @                   Amemory           	compatible interrupt-parent #address-cells #size-cells model reg device_type enable-method clock-frequency clock-output-names #clock-cells ranges interrupts interrupt-controller #interrupt-cells phandle clocks clock-names #pwm-cells #reset-cells 