  f   8  `   (              `                             $    mediatek,mt8188-evb mediatek,mt8188                                  +         !   7MediaTek MT8188 evaluation board       cpus                         +       cpu@0            =cpu           arm,cortex-a55           I             Mpsci             [w5          k           ~                              @                                    @                                                     cpu@100          =cpu           arm,cortex-a55           I            Mpsci             [w5          k           ~                              @                                    @                                               	      cpu@200          =cpu           arm,cortex-a55           I            Mpsci             [w5          k           ~                              @                                    @                                               
      cpu@300          =cpu           arm,cortex-a55           I            Mpsci             [w5          k           ~                              @                                    @                                                     cpu@400          =cpu           arm,cortex-a55           I            Mpsci             [w5          k           ~                              @                                    @                                                     cpu@500          =cpu           arm,cortex-a55           I            Mpsci             [w5          k           ~                              @                                    @                                                     cpu@600          =cpu           arm,cortex-a78           I            Mpsci             [          k            ~                              @                                    @                                                     cpu@700          =cpu           arm,cortex-a78           I            Mpsci             [          k            ~                              @                                    @                                                     cpu-map    cluster0       core0                    core1              	      core2              
      core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-off-l             arm,idle-state                      6        G   2        X   _        h  D                 cpu-off-b             arm,idle-state                      6        G   -        X           h                   cluster-off-l             arm,idle-state                    6        G   7        X           h  H                 cluster-off-b             arm,idle-state                    6        G   2        X           h                      l2-cache0             cache           y                           @                                                  l2-cache1             cache           y                           @                                                  l3-cache              cache           y                            @                                         oscillator-13m            fixed-clock                      [ ]@        clk13m                   oscillator-26m            fixed-clock                      [        clk26m                   oscillator-32k            fixed-clock                      [           clk32k        pmu-a55           arm,cortex-a55-pmu                                        pmu-a78           arm,cortex-a78-pmu                                        psci              arm,psci-1.0             Tsmc       timer             arm,armv8-timer                   @                                               
                [ ]@      soc                      +             simple-bus              interrupt-controller@c000000              arm,gic-v3                                                       I                                          	                     ppi-partitions     interrupt-partition-0                 	   
                          interrupt-partition-1                                        syscon@10000000            mediatek,mt8188-topckgen syscon          I                                          syscon@10001000       #    mediatek,mt8188-infracfg-ao syscon           I                                         syscon@10003000           mediatek,mt8188-pericfg syscon           I     0                                     pinctrl@10005000              mediatek,mt8188-pinctrl       `   I     P                                                                               0  iocfg0 iocfg_rm iocfg_lt iocfg_lm iocfg_rt eint                  %           1                                                                      adsp-uart-pins     pins-tx-rx          =  #  $         i2c0-pins              &   pins-bus            =  8  7        D            i2c1-pins              -   pins-bus            =  :  9        D            i2c2-pins              '   pins-bus            =  <  ;        D            i2c3-pins              (   pins-bus            =  >  =        D            i2c4-pins              .   pins-bus            =  @  ?        D            i2c5-pins              1   pins-bus            =  B  A        D            i2c6-pins              2   pins-bus            =  D  C        D            mmc0-default-pins              #   pins-cmd-dat          $  =                           Q        ^           D   e      pins-clk            =          ^           m   f      pins-rst            =          ^           D   e         mmc0-uhs-pins              $   pins-cmd-dat          $  =                           Q        ^           D   e      pins-clk-ds         =            ^           m   f      pins-rst            =          ^           D   e         nor-pins               +   pins-io-ck          =    }           m      pins-io-cs          =  ~             D         spi0-pins                 pins-spi            =  E  F  G  H         |         spi1-pins                 pins-spi            =  K  L  M  N         |         spi2-pins                 pins-spi            =  O  P  Q  R         |         uart0-pins                pins-rx-tx          =              D            watchdog@10007000             mediatek,mt8188-wdt          I     p                                  syscon@1000c000       "    mediatek,mt8188-apmixedsys syscon            I                                   /      timer@10017000        ,    mediatek,mt8188-timer mediatek,mt6765-timer          I    p                      	                        pwrap@10024000        3    mediatek,mt8188-pwrap mediatek,mt8195-pwrap syscon           I    @                pwrap                                                    	  spi wrap       pmic              mediatek,mt6359                                         mt6359codec       regulators     buck_vs1            vs1          5          !                     0      buck_vgpu11         vgpu11                    7        D                     Y                   0      buck_vmodem         vmodem                            D  *                 buck_vpu            vpu                   7        D                     Y                   0      buck_vcore          vcore                              D                     Y                   0      buck_vs2            vs2          5          j                      0      buck_vpa            vpa                    7          ,      buck_vproc2         vproc2                    7        D  L                   Y                buck_vproc1         vproc1                    7        D  L                   Y                buck_vcore_sshub            vcore_sshub                   7      buck_vgpu11_sshub           vgpu11_sshub                      7      ldo_vaud18          vaud18           w@         w@                 ldo_vsim1           vsim1                     /M`      ldo_vibr            vibr             O         2Z      ldo_vrf12           vrf12                               0      ldo_vusb            vusb             -         -                   0      ldo_vsram_proc2         vsram_proc2                            D  L                    0      ldo_vio18           vio18                                        0      ldo_vcamio          vcamio                          ldo_vcn18           vcn18            w@         w@                 ldo_vfe28           vfe28            *         *           x      ldo_vcn13           vcn13                            ldo_vcn33_1_bt          vcn33_1_bt           *         5g      ldo_vcn33_1_wifi            vcn33_1_wifi             *         5g      ldo_vaux18          vaux18           w@         w@                    0      ldo_vsram_others            vsram_others                               D                   ldo_vefuse          vefuse                          ldo_vxo22           vxo22            w@         !         0      ldo_vrfck           vrfck            `               ldo_vrfck_1         vrfck                     j       ldo_vbif28          vbif28           *         *                 ldo_vio28           vio28            *         2Z         0      ldo_vemc            vemc             ,@          2Z      ldo_vemc_1          vemc             &%         2Z           !      ldo_vcn33_2_bt          vcn33_2_bt           *         5g      ldo_vcn33_2_wifi            vcn33_2_wifi             *         5g      ldo_va12            va12             O                   0      ldo_va09            va09             5          O      ldo_vrf18           vrf18                     P      ldo_vsram_md          	  vsram_md                               D  *                 ldo_vufs            vufs                                 "      ldo_vm18            vm18                               0      ldo_vbbck           vbbck                     O      ldo_vsram_proc1         vsram_proc1                            D  L                    0      ldo_vsim2           vsim2                     /M`      ldo_vsram_others_sshub          vsram_others_sshub                              mt6359rtc             mediatek,mt6358-rtc             scp@10500000              mediatek,mt8188-scp           I    P             r               	  sram cfg                                 q           okay          clock-controller@10b91100             mediatek,mt8188-adsp-audio26m            I                             serial@11001100       *    mediatek,mt8188-uart mediatek,mt6577-uart            I                                                          	  baud bus            okay            default                  serial@11001200       *    mediatek,mt8188-uart mediatek,mt6577-uart            I                                                          	  baud bus          	  disabled          serial@11001300       *    mediatek,mt8188-uart mediatek,mt6577-uart            I                                                          	  baud bus          	  disabled          serial@11001400       *    mediatek,mt8188-uart mediatek,mt6577-uart            I                                                         	  baud bus          	  disabled          adc@11002000          .    mediatek,mt8188-auxadc mediatek,mt8173-auxadc            I                                    main                       okay          syscon@11003000       "    mediatek,mt8188-pericfg-ao syscon            I     0                                    spi@1100a000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +             I                                                 y                    parent-clk sel-clk spi-clk          okay            default                  spi@11010000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +             I                                                 y            2        parent-clk sel-clk spi-clk          okay            default                  spi@11012000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +             I                                                 y            3        parent-clk sel-clk spi-clk          okay            default                  spi@11013000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +             I    0                                            y            4        parent-clk sel-clk spi-clk        	  disabled          spi@11018000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +             I                                                y            8        parent-clk sel-clk spi-clk        	  disabled          spi@11019000          )    mediatek,mt8188-spi-ipm mediatek,spi-ipm                         +             I                                                y            9        parent-clk sel-clk spi-clk        	  disabled          usb@11200000          '    mediatek,mt8188-xhci mediatek,mtk-xhci            I                   >              	  mac ippc                                                            )      *              v      v              	            
        sys_ck ref_ck mcu_ck                  h                    okay          mmc@11230000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc           I    #                                                                             M      !  source hclk source_cg crypto_clk            okay                        H                  (         :         I         X         e         v         ~                    !           "        default state_uhs              #           $      mmc@11240000          (    mediatek,mt8188-mmc mediatek,mt8183-mmc           I    $                                                                      $        source hclk source_cg                                     	  disabled          i2c@11280000              mediatek,mt8188-i2c           I    (             "                                                    %          7      	  main dma                         +            okay            default            &         [       i2c@11281000              mediatek,mt8188-i2c           I    (            "                                                   %         7      	  main dma                         +            okay            default            '         [       i2c@11282000              mediatek,mt8188-i2c           I    (             "                                                   %         7      	  main dma                         +            okay            default            (         [       clock-controller@11283000             mediatek,mt8188-imp-iic-wrap-c           I    (0                              %      usb@112a0000          '    mediatek,mt8188-xhci mediatek,mtk-xhci            I    *             *>              	  mac ippc                                    )                 .      -              v      v                                  sys_ck ref_ck mcu_ck            okay          usb@112b0000          '    mediatek,mt8188-xhci mediatek,mtk-xhci            I    +             +>              	  mac ippc                                    *                 ,      +              v      v                                  sys_ck ref_ck mcu_ck                  `                    okay          spi@1132c000          (    mediatek,mt8188-nor mediatek,mt8186-nor          I    2                      X                    spi sf axi                X              9               okay            default            +                     +       flash@0           jedec,spi-nor            I            u          i2c@11e00000              mediatek,mt8188-i2c           I                 "                                                    ,          7      	  main dma                         +            okay            default            -         [       i2c@11e01000              mediatek,mt8188-i2c           I                "                                                   ,         7      	  main dma                         +            okay            default            .         [       clock-controller@11e02000             mediatek,mt8188-imp-iic-wrap-w           I                                   ,      t-phy@11e30000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0            I                        /           ref da_ref                        *         t-phy@11e40000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0            I                        /           ref da_ref                              usb-phy@700          I                 /              ref da_ref                   	  disabled                        t-phy@11e80000        .    mediatek,mt8188-tphy mediatek,generic-tphy-v3                        +                                okay       usb-phy@0            I                        /           ref da_ref                        )         i2c@11ec0000              mediatek,mt8188-i2c           I                 "                                                   0          7      	  main dma                         +            okay            default            1         [       i2c@11ec1000              mediatek,mt8188-i2c           I                "                                                    0         7      	  main dma                         +            okay            default            2         [       clock-controller@11ec2000              mediatek,mt8188-imp-iic-wrap-en          I                                   0      clock-controller@13fbf000             mediatek,mt8188-mfgcfg           I                             clock-controller@14000000             mediatek,mt8188-vppsys0          I                               clock-controller@14e00000             mediatek,mt8188-wpesys           I                              clock-controller@14e02000             mediatek,mt8188-wpesys-vpp0          I                              clock-controller@14f00000             mediatek,mt8188-vppsys1          I                              clock-controller@15000000             mediatek,mt8188-imgsys           I                               clock-controller@15110000              mediatek,mt8188-imgsys1-dip-top          I                              clock-controller@15130000             mediatek,mt8188-imgsys1-dip-nr           I                              clock-controller@15220000             mediatek,mt8188-imgsys-wpe1          I    "                          clock-controller@15330000             mediatek,mt8188-ipesys           I    3                          clock-controller@15520000             mediatek,mt8188-imgsys-wpe2          I    R                          clock-controller@15620000             mediatek,mt8188-imgsys-wpe3          I    b                          clock-controller@16000000             mediatek,mt8188-camsys           I                               clock-controller@1604f000             mediatek,mt8188-camsys-rawa          I                             clock-controller@1606f000             mediatek,mt8188-camsys-yuva          I                             clock-controller@1608f000             mediatek,mt8188-camsys-rawb          I                             clock-controller@160af000             mediatek,mt8188-camsys-yuvb          I    
                         clock-controller@17200000             mediatek,mt8188-ccusys           I                               clock-controller@1800f000             mediatek,mt8188-vdecsys-soc          I                              clock-controller@1802f000             mediatek,mt8188-vdecsys          I                             clock-controller@1a000000             mediatek,mt8188-vencsys          I                                  aliases         /soc/serial@11001100            /soc/i2c@11280000           /soc/i2c@11e00000           /soc/i2c@11281000           /soc/i2c@11282000           /soc/i2c@11e01000           /soc/i2c@11ec0000           /soc/i2c@11ec1000           /soc/mmc@11230000         chosen          serial0:115200n8          memory@40000000          =memory           I    @                reserved-memory                      +               memory@50000000           shared-dma-pool          I    P                                         	compatible interrupt-parent #address-cells #size-cells model device_type reg enable-method clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified #clock-cells clock-output-names interrupts ranges #interrupt-cells #redistributor-regions interrupt-controller affinity reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-pull-up input-enable drive-strength bias-pull-down bias-disable mediatek,disable-extrst #reset-cells clocks clock-names interrupts-extended regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes memory-region status pinctrl-names pinctrl-0 #io-channel-cells phys assigned-clocks assigned-clock-parents mediatek,syscon-wakeup wakeup-source bus-width hs400-ds-delay max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset no-sdio no-sd non-removable vmmc-supply vqmmc-supply pinctrl-1 clock-div spi-max-frequency #phy-cells serial0 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c6 mmc0 stdout-path no-map 