  I}   8  D   (              D|                                                                      ,Huawei Nexus 6P          2huawei,angler qcom,msm8994           =handset          J               V  	  
                 c  Z       aliases          q/soc@0/mmc@f9824900          v/soc@0/mmc@f98a4900          {/soc@0/serial@f991e000        chosen           serial0:115200n8          clocks     xo-board             2fixed-clock                       $       	   xo_board                      sleep-clk            2fixed-clock                                
   sleep_clk                        cpus                                 cpu@0            cpu          2arm,cortex-a53                            psci                               l2-cache             2cache                                             cpu@1            cpu          2arm,cortex-a53                           psci                                  cpu@2            cpu          2arm,cortex-a53                           psci                                  cpu@3            cpu          2arm,cortex-a53                           psci                                  cpu@100          cpu          2arm,cortex-a57                           psci                               l2-cache             2cache                                             cpu@101          cpu          2arm,cortex-a57                          psci                            	      cpu@102          cpu          2arm,cortex-a57                          psci                            
      cpu@103          cpu          2arm,cortex-a57                          psci                                  cpu-map    cluster0       core0                    core1                    core2                    core3                       cluster1       core0                    core1              	      core2              
      core3                             firmware       scm          2qcom,scm-msm8994 qcom,scm            memory@80000000          memory                                pmu          2arm,cortex-a53-pmu                        psci             2arm,psci-0.2             hvc       remoteproc        $   2qcom,msm8994-rpm-proc qcom,rpm-proc    smd-edge                                                (           6      rpm-requests             2qcom,rpm-msm8994            Frpm_requests       clock-controller             2qcom,rpmcc-msm8994 qcom,rpmcc                           ;      power-controller             2qcom,msm8994-rpmpd          X           l      opp-table            2operating-points-v2                opp1                     opp2                     opp3                     opp4                     opp5                     opp6                                    reserved-memory                                      dfps-data@3400000                @                        memory@3401000               @                       smem@6a00000                                                      memory@7000000                                       memory@ca00000                                      memory@c6400000          2qcom,rmtfs-mem               @                                   memory@c6700000              p                        memory@c7000000                                       memory@c9400000              @                       reserved@6c00000                        @                 tzapp@4800000                                       reserved@6300000                 0       p                    smem          
   2qcom,smem                                             smp2p-lpass          2qcom,smp2p                                                 
                    6      master-kernel           master-kernel                    slave-kernel            slave-kernel                     #            smp2p-modem          2qcom,smp2p                                                                                  6      master-kernel           master-kernel                    slave-kernel            slave-kernel                     #            soc@0                                                         2simple-bus     interrupt-controller@f9000000            2qcom,msm-qgic2                   #                                          mailbox@f900d000          %   2qcom,msm8994-apcs-kpss-global syscon                           4                     watchdog@f9017000         $   2qcom,apss-wdt-msm8994 qcom,kpss-wdt          p                                        @           G   
      timer@f9020000                                             2arm,armv7-timer-mem                  frame@f9021000          S                   	                                     frame@f9023000          S                  
            0          	  `disabled          frame@f9024000          S                              @          	  `disabled          frame@f9025000          S                              P          	  `disabled          frame@f9026000          S                              `          	  `disabled          frame@f9027000          S                              p          	  `disabled          frame@f9028000          S                                        	  `disabled             usb@f92f8800             2qcom,msm8994-dwc3 qcom,dwc3          /                                               @      r      m            s        gcore iface sleep mock_utmi          s      s      r        $ '                           usb@f9200000          
   2snps,dwc3                                                              high-speed          peripheral           mmc@f9824900          %   2qcom,msm8994-sdhci qcom,sdhci-msm-v4             I   @            
hc core                {                     hc_irq pwr_irq          @      v      h           giface core xo           $default sleep           2                    <                    F            P        `okay             ^      mmc@f98a4900          %   2qcom,msm8994-sdhci qcom,sdhci-msm-v4             I   @            
hc core                }                     hc_irq pwr_irq          @            i           giface core xo           $default sleep           2                 <          !        m   "   d            F         	  `disabled          dma-controller@f9904000          2qcom,bam-v1.7.0          @                             @      :        gbam_clk         v                                                          %      serial@f991e000       %   2qcom,msm-uartdm-v1.4 qcom,msm-uartdm                                l           gcore iface          @      H      :        $default sleep           2   #        <   $        `okay          i2c@f9923000             2qcom,i2c-qup-v2.2.1          0                   _           @      ;      :        gcore iface                       %      %           tx rx           $default sleep           2   &        <   '                                	  `disabled          spi@f9923000             2qcom,spi-qup-v2.2.1          0                   _           @      <      :        gcore iface             %      %           tx rx           $default sleep           2   (        <   )                                	  `disabled          i2c@f9924000             2qcom,i2c-qup-v2.2.1          @                   `           @      =      :        gcore iface                       %      %           tx rx           $default sleep           2   *        <   +                                	  `disabled          i2c@f9926000             2qcom,i2c-qup-v2.2.1          `                   b           @      A      :        gcore iface                       %      %           tx rx           $default sleep           2   ,        <   -                                	  `disabled          i2c@f9927000             2qcom,i2c-qup-v2.2.1          p                   c           @      C      :        gcore iface                       .      .           tx rx           $default sleep           2   /        <   0                                	  `disabled          i2c@f9928000             2qcom,i2c-qup-v2.2.1                             d           @      E      :        gcore iface                       %      %           tx rx           $default sleep           2   1        <   2                                	  `disabled          dma-controller@f9944000          2qcom,bam-v1.7.0          @                             @      M        gbam_clk         v                                                          .      serial@f995e000       %   2qcom,msm-uartdm-v1.4 qcom,msm-uartdm                                r           gcore iface          @      [      M           .      .           tx rx           $default sleep           2   3        <   4      	  `disabled          i2c@f9963000             2qcom,i2c-qup-v2.2.1          0                   e           @      N      M        gcore iface                       .      .           tx rx           $default sleep           2   5        <   6                                	  `disabled          spi@f9966000             2qcom,spi-qup-v2.2.1          `                   h           @      U      M        gcore iface             .      .           tx rx           $default sleep           2   7        <   8                                	  `disabled          i2c@f9967000             2qcom,i2c-qup-v2.2.1          p                   i           @      V      M        gcore iface            j           .      .           tx rx           $default sleep           2   9        <   :                                	  `disabled          clock-controller@fc400000            2qcom,gcc-msm8994                                   X            @            	  gxo sleep            @                        sram@fc428000            2qcom,rpm-msg-ram             B   @                   restart@fc4ab000             2qcom,pshold          J          spmi@fc4cf000            2qcom,spmi-pmic-arb           L    L    L            
core intr cnfg          periph_irq                                                                                       #         hwlock@fd484000       (   2qcom,msm8994-tcsr-mutex qcom,tcsr-mutex          H@                                 pinctrl@fd510000             2qcom,msm8994-pinctrl             Q    @                                       "                                       #              U               "   blsp1-uart2-default-state           0gpio4 gpio5         5blsp_uart2          >            M            #      blsp1-uart2-sleep-state         0gpio4 gpio5         5gpio            >            Z            $      blsp2-uart2-default-state           0gpio45 gpio46 gpio47 gpio48         5blsp_uart8          >            M            3      blsp2-uart2-sleep-state         0gpio45 gpio46 gpio47 gpio48         5gpio            >            M            4      i2c1-default-state          0gpio2 gpio3       
  5blsp_i2c1           >            M            &      i2c1-sleep-state            0gpio2 gpio3         5gpio            >            M            '      i2c2-default-state          0gpio6 gpio7       
  5blsp_i2c2           >            M            *      i2c2-sleep-state            0gpio6 gpio7         5gpio            >            M            +      i2c4-default-state          0gpio19 gpio20         
  5blsp_i2c4           >            M            ,      i2c4-sleep-state            0gpio19 gpio20           5gpio            >            Z            -      i2c5-default-state          0gpio23 gpio24         
  5blsp_i2c5           >            M            /      i2c5-sleep-state            0gpio23 gpio24           5gpio            >            M            0      i2c6-default-state          0gpio28 gpio27         
  5blsp_i2c6           >            M            1      i2c6-sleep-state            0gpio28 gpio27           5gpio            >            M            2      i2c7-default-state          0gpio44 gpio43         
  5blsp_i2c7           >            M            5      i2c7-sleep-state            0gpio44 gpio43           5gpio            >            M            6      blsp2-spi10-default-state               7   default-pins            0gpio53 gpio54 gpio55            5blsp_spi10          >   
         Z      cs-pins         0gpio67          5gpio            >            M         blsp2-spi10-sleep-state         0gpio53 gpio54 gpio55            5gpio            >            M            8      i2c11-default-state         0gpio83 gpio84           5blsp_i2c11          >            M            9      i2c11-sleep-state           0gpio83 gpio84           5gpio            >            M            :      blsp1-spi1-default-state                (   default-pins            0gpio0 gpio1 gpio3         
  5blsp_spi1           >   
         Z      cs-pins         0gpio8           5gpio            >            M         blsp1-spi1-sleep-state          0gpio0 gpio1 gpio3           5gpio            >            M            )      clk-on-state          	  0sdc1_clk             M        >                     clk-off-state         	  0sdc1_clk             M        >                     cmd-on-state          	  0sdc1_cmd             i        >                     cmd-off-state         	  0sdc1_cmd             i        >                     data-on-state         
  0sdc1_data            i        >                     data-off-state        
  0sdc1_data            i        >                     rclk-on-state         
  0sdc1_rclk            Z                  rclk-off-state        
  0sdc1_rclk            Z                  sdc2-clk-on-state         	  0sdc2_clk             M        >   
                  sdc2-clk-off-state        	  0sdc2_clk             M        >                     sdc2-cmd-on-state         	  0sdc2_cmd             i        >   
                  sdc2-cmd-off-state        	  0sdc2_cmd             i        >                      sdc2-data-on-state        
  0sdc2_data            i        >   
                  sdc2-data-off-state       
  0sdc2_data            i        >               !         clock-controller@fd8c0000            2qcom,mmcc-msm8994                R                                X         Y  gxo gpll0 mmssnoc_ahb oxili_gfx3d_clk_src dsi0pll dsi0pllbyte dsi1pll dsi1pllbyte hdmipll          0  @            ;      ;                              (  s   <      <      <      <      <   	        / E< 98p #F             <      sram@fdd00000            2qcom,msm8974-ocmem                             	  
ctrl mem                              @   ;   "   <   r        gcore iface                              gmu-sram@0                              timer            2arm,armv8-timer       0                                        vph-pwr-regulator            2regulator-fixed         vvph_pwr          6         6                  	interrupt-parent #address-cells #size-cells model compatible chassis-type qcom,msm-id qcom,pmic-id qcom,board-id mmc1 mmc2 serial0 stdout-path #clock-cells clock-frequency clock-output-names phandle device_type reg enable-method next-level-cache cache-level cache-unified cpu interrupts qcom,ipc qcom,smd-edge qcom,remote-pid qcom,smd-channels #power-domain-cells operating-points-v2 opp-level ranges no-map qcom,client-id memory-region qcom,rpm-msg-ram hwlocks qcom,smem qcom,local-pid qcom,entry-name #qcom,smem-state-cells interrupt-controller #interrupt-cells #mbox-cells clocks timeout-sec frame-number status clock-names assigned-clocks assigned-clock-rates power-domains qcom,select-utmi-as-pipe-clk snps,dis_u2_susphy_quirk snps,dis_enblslpm_quirk maximum-speed dr_mode reg-names interrupt-names pinctrl-names pinctrl-0 pinctrl-1 bus-width non-removable mmc-hs400-1_8v cd-gpios #dma-cells qcom,ee qcom,controlled-remotely num-channels qcom,num-ees dmas dma-names #reset-cells qcom,channel #hwlock-cells gpio-controller gpio-ranges #gpio-cells gpio-reserved-ranges pins function drive-strength bias-disable bias-pull-down bias-pull-up regulator-name regulator-min-microvolt regulator-max-microvolt regulator-always-on 