 C   8 8   (            
 8                                                                      ,Freescale i.MX8QM MEK            2fsl,imx8qm-mek fsl,imx8qm      aliases          =/bus@5b000000/mmc@5b010000           B/bus@5b000000/mmc@5b020000           G/bus@5b000000/mmc@5b030000           L/bus@5a000000/serial@5a060000            T/bus@5a000000/serial@5a070000            \/bus@5a000000/serial@5a080000            d/bus@5a000000/serial@5a090000            l/bus@5a000000/spi@5a000000           q/bus@5a000000/spi@5a010000           v/bus@5a000000/spi@5a020000           {/bus@5a000000/spi@5a030000            /vpu@2c000000/vpu-core@2d080000           /vpu@2c000000/vpu-core@2d090000           /vpu@2c000000/vpu-core@2d0a0000       cpus                                 cpu@0            cpu          2arm,cortex-a53                                               psci                            @                                    @                              ,           @           O   	      cpu@1            cpu          2arm,cortex-a53                                              psci                            @                                    @                              ,           @           O   
      cpu@2            cpu          2arm,cortex-a53                                              psci                            @                                    @                              ,           @           O         cpu@3            cpu          2arm,cortex-a53                                              psci                            @                                    @                              ,           @           O         l2-cache0            2cache           W            c                        @                    O         l2-cache1            2cache           W            c                        @                     opp-table-0          2operating-points-v2          q        O      opp-600000000           |    #F                   I      opp-896000000           |    5g          B@         I      opp-1104000000          |    Aʹ                   I      opp-1200000000          |    G                   I                  opp-table-1          2operating-points-v2          q   opp-600000000           |    #F          B@         I      opp-1056000000          |    >H          B@         I      opp-1296000000          |    M?d                   I      opp-1596000000          |    _!                   I                  interrupt-controller@51a00000            2arm,gic-v3        P       Q             Q             R               R             R                                           	                        O         pmu          2arm,armv8-pmuv3                        psci             2arm,psci-1.0             smc       timer            2arm,armv8-timer       0                                   
         iommu@51400000           2arm,mmu-500                           Q@                                                                                                                                                                                                                                                                                                                                                                                                                         O         system-controller            2fsl,imx-scu         tx0 rx0 gip3          $  
                                 power-controller             2fsl,imx8qm-scu-pd fsl,scu-pd                       O         clock-controller             2fsl,imx8qm-clk fsl,scu-clk          %           O         pinctrl          2fsl,imx8qm-iomuxc           2default         @           O      hoggrp          J   s      L   '     L        O         cs42888_resetgrp            J        L        O         i2c0grp         J   R     !   S     !        O         i2c1grp         J        L        L        O         i2c1gpio-grp            J        L        L        O         adc0grp         J         `        O         cm41i2cgrp          J         L         L        O         esai0grp          x  J   h      @   i      @   j      @   k      @   l      @   m      @   n      @   o      @   p      @   q      @        O   "      fec1grp         J                                                                                                                                                    O         lpspi2grp         $  J   z      @   {      @   |      @        O   x      lpspi2csgrp         J   }      !        O   y      mipi0_lpi2c0grp       $  J   ?          @          B               O   Y      mipi1_lpi2c0grp       $  J   C          D          F               O   i      flexspi0grp         J         !         !         !         !         !         !         !         !         !         !         !         !         !         !         !         !        O         fec2grp         J                 `          `         `         `         `         `         `         `         `  	       `  
       `         `        O         flexcan0grp         J          !          !        O         flexcan1grp         J          !          !        O         flexcan3grp         J          !          !        O         lpuart0grp          J                            O   }      lpuart2grp          J                          O         lpuart3grp          J                          O         lvds0lpi2c1grp          J   6      L   7      L        O   a      lvds1lpi2c1grp          J   <      L   =      L        O   p      pcieagrp          $  J        !        !   +               O         pcieareggrp         J   ;     !        O         pciebgrp          $  J         !        !        !        O         pwmlvds0grp         J   2               O   ]      pwmlvds1grp         J   8               O   m      sai0grp       0  J   y     L   ~     L        L        l        O   &      sai1grp       0  J         @         @         `         @        O   (      typecgrp            J         !        O         typecmuxgrp         J         `         `        O         usdhc1grp           J         A          !          !          !          !          !          !          !          !          !          A        O         usdhc2grp         T  J         A          !          !          !          !          !          !        O            rtc          2fsl,imx8qxp-sc-rtc        ocotp            2fsl,imx8qm-scu-ocotp                                      S   mac@1c4                     mac@1c6                       O            thermal-sensor        *   2fsl,imx8qxp-sc-thermal fsl,imx-sc-thermal           ]           O            thermal-zones      cpu0-thermal            s                               trips      trip0                               passive         O         trip1                            	   critical             cooling-maps       map0                     0     	   
                  gpu0-thermal            s                              trips      trip0                               passive       trip1                            	   critical                gpu1-thermal            s                              trips      trip0                               passive       trip1                            	   critical                drc0-thermal            s                              trips      trip0                               passive       trip1                            	   critical                   clock-dummy          2fixed-clock         %                      
  clk_dummy           O         clock-esai1-rx           2fixed-clock         %                        esai1_rx_clk            O   =      clock-esai1-rx-hf            2fixed-clock         %                        esai1_rx_hf_clk         O   >      clock-esai1-tx           2fixed-clock         %                        esai1_tx_clk            O   ?      clock-esai1-tx-hf            2fixed-clock         %                        esai1_tx_hf_clk         O   @      clock-hdmi-rx-mclk           2fixed-clock         %                        hdmi-rx-mclk            O   6      clock-mlb-clk            2fixed-clock         %                        mlb_clk         O   5      clock-sai5-rx-bclk           2fixed-clock         %                        sai5_rx_bclk            O   I      clock-sai5-tx-bclk           2fixed-clock         %                        sai5_tx_bclk          clock-sai6-rx-bclk           2fixed-clock         %                        sai6_rx_bclk            O   J      clock-sai6-tx-bclk           2fixed-clock         %                        sai6_tx_bclk          clock-spdif1-rx          2fixed-clock         %                      
  spdif1_rx         clock-controller-lvds-ipg            2fixed-clock         %            n6         lvds0_ipg_clk           O   [      clock-controller-dsi-ipg             2fixed-clock         %            '         dsi_ipg_clk         O   S      clock-controller-mipi-div2-pll           2fixed-clock         %                     mipi_pll_div2_clk         bus@55000000             2simple-bus                                   U       U         dsp@556e8000             2fsl,imx8qm-hifi4             Un                             ipg ocram core                                        $  
                                       tx rx rxdb          imx/dsp/hifi4.bin           $okay            +                     clock-cm41-ipg           2fixed-clock         %            )         cm41_ipg_clk            O         bus@38000000             2simple-bus                                   8       8                      i2c@3b230000          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c          ;#                	                                 per ipg         9     4           In6              4        $okay                                               2default         @      gpio@20          2ti,tca6416                        ^        n           O         audio-codec@48           2cirrus,cs42888              H                        mclk            2default         @           z                                                           ,  9     E        E         E                  I.                O            intmux@3b400000          2fsl,imx-intmux           ;@                        `                                                           '                                                               ipg              5        $okay            O         clock-controller@3b630000            2fsl,imx8qxp-lpcg             ;c             %                 4                           (  cm41_lpcg_i2c_clk cm41_lpcg_i2c_ipg_clk              4        O            clock-audio-ipg          2fixed-clock         %            '         audio_ipg_clk           O   $      clock-ext-aud-mclk0          2fixed-clock         %                        ext_aud_mclk0           O   7      clock-ext-aud-mclk1          2fixed-clock         %                        ext_aud_mclk1           O   8      clock-esai0-rx           2fixed-clock         %                        esai0_rx_clk            O   9      clock-esai0-rx-hf            2fixed-clock         %                        esai0_rx_hf_clk         O   :      clock-esai0-tx           2fixed-clock         %                        esai0_tx_clk            O   ;      clock-esai0-tx-hf            2fixed-clock         %                        esai0_tx_hf_clk         O   <      clock-spdif0-rx          2fixed-clock         %                      
  spdif0_rx           O   A      clock-sai0-rx-bclk           2fixed-clock         %                        sai0_rx_bclk            O   B      clock-sai0-tx-bclk           2fixed-clock         %                        sai0_tx_bclk            O   C      clock-sai1-rx-bclk           2fixed-clock         %                        sai1_rx_bclk            O   D      clock-sai1-tx-bclk           2fixed-clock         %                        sai1_tx_bclk            O   E      clock-sai2-rx-bclk           2fixed-clock         %                        sai2_rx_bclk            O   F      clock-sai3-rx-bclk           2fixed-clock         %                        sai3_rx_bclk            O   G      clock-sai4-rx-bclk           2fixed-clock         %                        sai4_rx_bclk            O   H      bus@59000000             2simple-bus                                   Y       Y         asrc@59000000            2fsl,imx8qm-asrc          Y                    t         d                                                                                          mem ipg asrck_0 asrck_1 asrck_2 asrck_3 asrck_4 asrck_5 asrck_6 asrck_7 asrck_8 asrck_9 asrck_a asrck_b asrck_c asrck_d asrck_e asrck_f spba          `                                                                                                  rxa rxb rxc txa txb txc                                                       $okay            O         esai@59010000         !   2fsl,imx8qm-esai fsl,imx6ull-esai             Y                                  !       !      !               core extal fsys spba                                                  rx tx                        $okay            2default         @   "      4  9           E        E         E      !                          I    .                O         spdif@59020000           2fsl,imx8qm-spdif             Y                                     0      #         #               $               :  core rxtx0 rxtx1 rxtx2 rxtx3 rxtx4 rxtx5 rxtx6 rxtx7 spba                                 	               rx tx                      	  $disabled          sai@59040000             2fsl,imx8qm-sai           Y                   :               %          %                 bus mclk0 mclk1 mclk2 mclk3         rx tx                                                      >        $okay                      ,  9     E        E         E      %           I.                2default         @   &        O         sai@59050000             2fsl,imx8qm-sai           Y                   <               '          '                 bus mclk0 mclk1 mclk2 mclk3         rx tx                                                      ?        $okay          ,  9     E        E         E      '           I.                2default         @   (        O         sai@59060000             2fsl,imx8qm-sai           Y                   >               )          )                 bus mclk0 mclk1 mclk2 mclk3         rx                                     @      	  $disabled          sai@59070000             2fsl,imx8qm-sai           Y                   C               *          *                 bus mclk0 mclk1 mclk2 mclk3         rx                                           	  $disabled          dma-controller@591f0000          2fsl,imx8qm-edma          Y             #           .           ;                  v         w         x         y         z         {                                                               ;         ;         =         =         ?         D         F         H                                                                                                                          O          clock-controller@59400000            2fsl,imx8qxp-lpcg             Y@             %               $   $                     &  asrc0_lpcg_ipg_clk asrc0_lpcg_mem_clk                        O         clock-controller@59410000            2fsl,imx8qxp-lpcg             YA             %                     $                     (  esai0_lpcg_extal_clk esai0_lpcg_ipg_clk                      O   !      clock-controller@59420000            2fsl,imx8qxp-lpcg             YB             %                     $                    %  spdif0_lpcg_tx_clk spdif0_lpcg_gclkw                         O   #      clock-controller@59440000            2fsl,imx8qxp-lpcg             YD             %                     $                     !  sai0_lpcg_mclk sai0_lpcg_ipg_clk                 >        O   %      clock-controller@59450000            2fsl,imx8qxp-lpcg             YE             %                     $                     !  sai1_lpcg_mclk sai1_lpcg_ipg_clk                 ?        O   '      clock-controller@59460000            2fsl,imx8qxp-lpcg             YF             %                     $                     !  sai2_lpcg_mclk sai2_lpcg_ipg_clk                 @        O   )      clock-controller@59470000            2fsl,imx8qxp-lpcg             YG             %                     $                     !  sai3_lpcg_mclk sai3_lpcg_ipg_clk                         O   *      clock-controller@59580000            2fsl,imx8qxp-lpcg             YX             %               $   $   $                       4  dsp_lpcg_adb_clk dsp_lpcg_ipg_clk dsp_lpcg_core_clk                     	  $disabled          clock-controller@59590000            2fsl,imx8qxp-lpcg             YY             %               $                   dsp_ram_lpcg_ipg_clk                       	  $disabled          asrc@59800000            2fsl,imx8qm-asrc          Y                   |         d      +       +                                                                             mem ipg asrck_0 asrck_1 asrck_2 asrck_3 asrck_4 asrck_5 asrck_6 asrck_7 asrck_8 asrck_9 asrck_a asrck_b asrck_c asrck_d asrck_e asrck_f spba          `     ,               ,              ,              ,             ,             ,                  rxa rxb rxc txa txb txc           @                                         	  $disabled          sai@59820000             2fsl,imx8qm-sai           Y                   I               -          -                 bus mclk0 mclk1 mclk2 mclk3             ,             ,   	                rx tx                        $okay          4  9                                  -                          I    .                 L        O   0      sai@59830000             2fsl,imx8qm-sai           Y                   K               .          .                 bus mclk0 mclk1 mclk2 mclk3            ,   
                tx                       $okay          4  9                                  .                          I    .                 L        O   1      amix@59840000            2fsl,imx8qm-audmix            Y                 /            ipg                      a   0   1        $okay          mqs@59850000             2fsl,imx8qm-mqs           Y                 2      2          
  mclk core                      	  $disabled          dma-controller@599f0000          2fsl,imx8qm-edma          Y             #           .           ;                 ~                                                                            J         J         L         X                                                                 O   ,      clock-controller@59d00000            2fsl,imx8qxp-lpcg             Y             %                 E                       aud_rec_clk0_lpcg_clk                E        O   3      clock-controller@59d10000            2fsl,imx8qxp-lpcg             Y             %                                        aud_rec_clk1_lpcg_clk                        O   4      clock-controller@59d20000            2fsl,imx8qxp-lpcg             Y             %                 E                        aud_pll_div_clk0_lpcg_clk                E        O         clock-controller@59d30000            2fsl,imx8qxp-lpcg             Y             %                                         aud_pll_div_clk1_lpcg_clk                        O         clock-controller@59d50000            2fsl,imx8qxp-lpcg             Y             %                                      mclkout0_lpcg_clk                        O         clock-controller@59d60000            2fsl,imx8qxp-lpcg             Y             %                                      mclkout1_lpcg_clk                      acm@59e00000             2fsl,imx8qm-acm           Y             %                                    E                              >     ?     @                                              |      3       4                     5   6   7   8   9   :   ;   <   =   >   ?   @   A   A   B   C   D   E   F   G   H   I   J       aud_rec_clk0_lpcg_clk aud_rec_clk1_lpcg_clk aud_pll_div_clk0_lpcg_clk aud_pll_div_clk1_lpcg_clk mlb_clk hdmi_rx_mclk ext_aud_mclk0 ext_aud_mclk1 esai0_rx_clk esai0_rx_hf_clk esai0_tx_clk esai0_tx_hf_clk esai1_rx_clk esai1_rx_hf_clk esai1_tx_clk esai1_tx_hf_clk spdif0_rx spdif1_rx sai0_rx_bclk sai0_tx_bclk sai1_rx_bclk sai1_tx_bclk sai2_rx_bclk sai3_rx_bclk sai4_rx_bclk sai5_tx_bclk sai6_rx_bclk           O         clock-controller@59c00000            2fsl,imx8qxp-lpcg             Y             %               $   $                     &  asrc1_lpcg_ipg_clk asrc1_lpcg_mem_clk                        O   +      clock-controller@59c20000            2fsl,imx8qxp-lpcg             Y             %                     $                     !  sai6_lpcg_mclk sai6_lpcg_ipg_clk                         O   -      clock-controller@59c30000            2fsl,imx8qxp-lpcg             Y             %                     $                     !  sai7_lpcg_mclk sai7_lpcg_ipg_clk                         O   .      clock-controller@59c40000            2fsl,imx8qxp-lpcg             Y             %               $                    amix_lpcg_ipg_clk                        O   /      clock-controller@59c50000            2fsl,imx8qxp-lpcg             Y             %                     $                     !  mqs0_lpcg_mclk mqs0_lpcg_ipg_clk                         O   2      sai@59080000             2fsl,imx8qm-sai           Y                   E               K          K                 bus mclk0 mclk1 mclk2 mclk3         rx                                f                              	  $disabled          sai@59090000             2fsl,imx8qm-sai           Y	                   G               L          L                 bus mclk0 mclk1 mclk2 mclk3         tx                                 f                              	  $disabled          clock-controller@59480000            2fsl,imx8qxp-lpcg             YH             %                     $                     !  sai4_lpcg_mclk sai4_lpcg_ipg_clk                       	  $disabled            O   K      clock-controller@59490000            2fsl,imx8qxp-lpcg             YI             %                     $                     !  sai5_lpcg_mclk sai5_lpcg_ipg_clk                       	  $disabled            O   L      esai@59810000         !   2fsl,imx8qm-esai fsl,imx6ull-esai             Y                                  M       M      M               core extal fsys spba                ,             ,                   rx tx                      	  $disabled          clock-controller@59c10000            2fsl,imx8qxp-lpcg             Y             %                     $                     (  esai1_lpcg_extal_clk esai1_lpcg_ipg_clk                      O   M         vpu@2c000000                                     ,       ,                   ,                             	  $disabled       mailbox@2d000000             2fsl,imx6sx-mu            -                               s                      	  $disabled            O   N      mailbox@2d020000             2fsl,imx6sx-mu            -                              s                      	  $disabled            O   O      mailbox@2d040000             2fsl,imx6sx-mu            -                              s                      	  $disabled            O   P      vpu-core@2d080000            -              2nxp,imx8q-vpu-decoder                        tx0 tx1 rx        $  
   N           N          N             	  $disabled          vpu-core@2d090000            -	              2nxp,imx8q-vpu-encoder                        tx0 tx1 rx        $  
   O           O          O             	  $disabled          vpu-core@2d0a0000            -
              2nxp,imx8q-vpu-encoder                        tx0 tx1 rx        $  
   P           P          P             	  $disabled             bus@53000000             2simple-bus                                   S       S         gpu@53100000             2vivante,gc           S                    @                                      core shader         9                          I)' 2                       bus@56220000             2simple-bus               Q                                 V"      V"        interrupt-controller@56220000         &   2fsl,imx8qxp-irqsteer fsl,imx-irqsteer            V"                    ;                                                R            ipg                                              O   Q      clock-controller@56223000            2fsl,imx8qxp-lpcg             V"0            %                            S                    mipi0_lis_lpcg_ipg_clk          O   R      clock-controller@5622300c            2fsl,imx8qxp-lpcg             V"0           %                                    S                     *  mipi0_pwm_lpcg_clk mipi0_pwm_lpcg_ipg_clk           O   V      clock-controller@56223014            2fsl,imx8qxp-lpcg             V"0           %               T                        mipi0_i2c0_lpcg_ipg_clk                      O   X      clock-controller@56223018            2fsl,imx8qxp-lpcg             V"0           %               S                    mipi0_i2c0_lpcg_ipg_s_clk                        O   T      clock-controller@5622301c            2fsl,imx8qxp-lpcg             V"0           %                                        mipi0_i2c0_lpcg_clk                      O   W      clock-controller@56223024            2fsl,imx8qxp-lpcg             V"0$           %               U                        mipi0_i2c1_lpcg_ipg_clk                    clock-controller@56223028            2fsl,imx8qxp-lpcg             V"0(           %               S                    mipi0_i2c1_lpcg_ipg_s_clk                        O   U      clock-controller@5622302c            2fsl,imx8qxp-lpcg             V"0,           %                                        mipi0_i2c1_lpcg_clk                    pwm@56224000             2fsl,imx8qxp-pwm fsl,imx27-pwm            V"@                V      V            ipg per         9                In6                               	  $disabled          i2c@56226000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           V"`                                                     W       X            per ipg         9   W            In6                      $okay            2default         @   Y                  bus@56240000             2simple-bus                                   V$      V$                  Z   clock-controller@56243000            2fsl,imx8qxp-lpcg             V$0            %           lvds0_lis_lpcg_ipg_clk                           [                   O   _      clock-controller@5624300c            2fsl,imx8qxp-lpcg             V$0           %         A  lvds0_pwm_lpcg_clk lvds0_pwm_lpcg_ipg_clk lvds0_pwm_lpcg_32k_clk                                     [                       O   \      clock-controller@56243010            2fsl,imx8qxp-lpcg             V$0           %         ,  lvds0_i2c0_lpcg_clk lvds0_i2c0_lpcg_ipg_clk                                  [                       O   ^      pwm@56244000             2fsl,imx8qxp-pwm fsl,imx27-pwm            V$@            ipg per         9                In6                                 $okay                \      \            2default         @   ]        O         i2c@56246000          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c          V$`                                                 per ipg         9                In6                    	  $disabled                ^       ^         interrupt-controller@56240000         %   2fsl,imx8qm-irqsteer fsl,imx-irqsteer             V$                    9                                                _           ipg              
                                O   Z      clock-controller@56243014            2fsl,imx8qxp-lpcg             V$0           %                       [                     ,  lvds0_i2c1_lpcg_clk lvds0_i2c1_lpcg_ipg_clk                      O   `      i2c@56247000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           V$p               	            `       `           per ipg         9                In6                      $okay            2default         @   a                  bus@57220000             2simple-bus               b                                 W"      W"        interrupt-controller@57220000         %   2fsl,imx8qm-irqsteer fsl,imx-irqsteer             W"                    <                                                c            ipg                                              O   b      clock-controller@57223000            2fsl,imx8qxp-lpcg             W"0            %               S                    mipi1_lis_lpcg_ipg_clk                       O   c      clock-controller@5722300c            2fsl,imx8qxp-lpcg             W"0           %                       S                     *  mipi1_pwm_lpcg_clk mipi1_pwm_lpcg_ipg_clk                        O   f      clock-controller@5722301c            2fsl,imx8qxp-lpcg             W"0           %                                        mipi1_i2c0_lpcg_clk                      O   g      clock-controller@57223014            2fsl,imx8qxp-lpcg             W"0           %               d                        mipi1_i2c0_lpcg_ipg_clk                      O   h      clock-controller@57223018            2fsl,imx8qxp-lpcg             W"0           %               S                    mipi1_i2c0_lpcg_ipg_s_clk                        O   d      clock-controller@57223024            2fsl,imx8qxp-lpcg             W"0$           %               e                        mipi1_i2c1_lpcg_ipg_clk                    clock-controller@57223028            2fsl,imx8qxp-lpcg             W"0(           %               S                    mipi1_i2c1_lpcg_ipg_s_clk                        O   e      clock-controller@5722302c            2fsl,imx8qxp-lpcg             W"0,           %                                        mipi1_i2c1_lpcg_clk                    pwm@57224000             2fsl,imx8qxp-pwm fsl,imx27-pwm            W"@                f      f            ipg per         9                In6                               	  $disabled          i2c@57226000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           W"`                                                      b            g       h            per ipg         9   g            In6                      $okay            2default         @   i                  bus@57240000             2simple-bus               j                                 W$      W$        interrupt-controller@57240000         %   2fsl,imx8qm-irqsteer fsl,imx-irqsteer             W$                    :                                                k           ipg                                              O   j      clock-controller@57243000            2fsl,imx8qxp-lpcg             W$0            %               [                   lvds1_lis_lpcg_ipg_clk                       O   k      clock-controller@5724300c            2fsl,imx8qxp-lpcg             W$0           %                       [                     *  lvds1_pwm_lpcg_clk lvds1_pwm_lpcg_ipg_clk                        O   l      clock-controller@57243010            2fsl,imx8qxp-lpcg             W$0           %                       [                     ,  lvds1_i2c0_lpcg_clk lvds1_i2c0_lpcg_ipg_clk                      O   n      clock-controller@57243014            2fsl,imx8qxp-lpcg             W$0           %                       [                     ,  lvds1_i2c1_lpcg_clk lvds1_i2c1_lpcg_ipg_clk                      O   o      pwm@57244000             2fsl,imx8qxp-pwm fsl,imx27-pwm            W$@                l      l            ipg per         9                In6                                 $okay            2default         @   m        O         i2c@57246000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           W$`                                                     n       n           per ipg         9                In6                    	  $disabled          i2c@57247000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           W$p               	            o       o           per ipg         9                In6                      $okay            2default         @   p                  clock-img-ipg            2fixed-clock         %                     img_ipg_clk         O   s      bus@58000000             2simple-bus                                   X       X         jpegdec@58400000             X@                   5               q       q           9   q       q           I                          %   2nxp,imx8qm-jpgdec nxp,imx8qxp-jpgdec          jpegenc@58450000             XE                   1               r       r           9   r       r           I                          %   2nxp,imx8qm-jpgenc nxp,imx8qxp-jpgenc          clock-controller@585d0000            2fsl,imx8qxp-lpcg             X]             %               s   s                     0  img_jpeg_dec_lpcg_clk img_jpeg_dec_lpcg_ipg_clk                      O   q      clock-controller@585f0000            2fsl,imx8qxp-lpcg             X_             %               s   s                     0  img_jpeg_enc_lpcg_clk img_jpeg_enc_lpcg_ipg_clk                      O   r         clock-dma-ipg            2fixed-clock         %            '         dma_ipg_clk         O         bus@5a000000             2simple-bus                                   Z       Z         spi@5a000000             2fsl,imx7ulp-spi          Z                                              P                            t       t           per ipg         9      5           I               5            u              u                   tx rx         	  $disabled          spi@5a010000             2fsl,imx7ulp-spi          Z                                             Q                            v       v           per ipg         9      6           I               6            u              u                  tx rx         	  $disabled          spi@5a020000             2fsl,imx7ulp-spi          Z                                             R                            w       w           per ipg         9      7           I               7            u              u                  tx rx           $okay            2default         @   x   y           z   
         spi@5a030000             2fsl,imx7ulp-spi          Z                                             S                            {       {           per ipg         9      8           I               8            u              u                  tx rx         	  $disabled          serial@5a060000          Z                   Y               |      |          	  ipg baud            9      9           IĴ               9        rx tx               u              u                  $okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            2default         @   }      serial@5a070000          Z                   Z               ~      ~          	  ipg baud            9      :           IĴ               :        rx tx               u              u                	  $disabled          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart          serial@5a080000          Z                   [                               	  ipg baud            9      ;           IĴ               ;        rx tx               u              u                  $okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            2default         @         serial@5a090000          Z	                   \                               	  ipg baud            9      <           IĴ               <        rx tx               u              u                  $okay          %   2fsl,imx8qm-lpuart fsl,imx8qxp-lpuart            2default         @         dma-controller@5a1f0000          2fsl,imx8qm-edma          Z             #           .                                                                                                                                                                                                                                      @      A      B      C      D      E      F      G      H      I      J      K      L      M      N      O      P      Q      R      S      T      U        ;           $okay            O   u      clock-controller@5a400000            2fsl,imx8qxp-lpcg             Z@             %                  5                              spi0_lpcg_clk spi0_lpcg_ipg_clk               5        O   t      clock-controller@5a410000            2fsl,imx8qxp-lpcg             ZA             %                  6                              spi1_lpcg_clk spi1_lpcg_ipg_clk               6        O   v      clock-controller@5a420000            2fsl,imx8qxp-lpcg             ZB             %                  7                              spi2_lpcg_clk spi2_lpcg_ipg_clk               7        O   w      clock-controller@5a430000            2fsl,imx8qxp-lpcg             ZC             %                  8                              spi3_lpcg_clk spi3_lpcg_ipg_clk               8        O   {      clock-controller@5a460000            2fsl,imx8qxp-lpcg             ZF             %                  9                           '  uart0_lpcg_baud_clk uart0_lpcg_ipg_clk                9        O   |      clock-controller@5a470000            2fsl,imx8qxp-lpcg             ZG             %                  :                           '  uart1_lpcg_baud_clk uart1_lpcg_ipg_clk                :        O   ~      clock-controller@5a480000            2fsl,imx8qxp-lpcg             ZH             %                  ;                           '  uart2_lpcg_baud_clk uart2_lpcg_ipg_clk                ;        O         clock-controller@5a490000            2fsl,imx8qxp-lpcg             ZI             %                  <                           '  uart3_lpcg_baud_clk uart3_lpcg_ipg_clk                <        O         i2c@5a800000             Z    @                                                                           per ipg         9      `           In6               `        $okay          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c                   2default         @      accelerometer@19             2st,lsm303agr-accel                    gyrometer@20             2nxp,fxas21002c                     light-sensor@44          2isil,isl29023               D                                 pressure-sensor@60           2fsl,mpl3115             `      gpio@68          2maxim,max7322               h         ^        n           O         gyrometer@69             2st,l3g4200d-gyro                i      tcpc@51          2nxp,ptn5110 tcpci           2default         @               Q                                   $okay       connector            2usb-c-connector         USB-C           source          dual            ,   ports                                port@0                  endpoint                       O            port@1                 endpoint                       O                        i2c@5a810000             Z    @                                                                           per ipg         9      a           In6               a        $okay          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c                   2default gpio            @                                                     audio-codec@1a           2wlf,wm8960                                      mclk          ,  9     E        E         E                  I.                                                        *           6           C           P           _           O            i2c@5a820000             Z    @                                                                           per ipg         9      b           In6               b      	  $disabled          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c        i2c@5a830000             Z    @                                                                           per ipg         9      c           In6               c      	  $disabled          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c        adc@5a880000             2nxp,imx8qxp-adc         n            Z                                                                  per ipg         9      e           In6               e        $okay            2default         @                    adc@5a890000             2nxp,imx8qxp-adc         n            Z                                                                  per ipg         9      f           In6               f      	  $disabled          can@5a8d0000             2fsl,imx8qm-flexcan           Z                                                                  ipg per         9      i           IbZ               i                               $okay            2default         @                    can@5a8e0000             2fsl,imx8qm-flexcan           Z                                                                  ipg per         9      j           IbZ               j                              $okay            2default         @                    can@5a8f0000             2fsl,imx8qm-flexcan           Z                                                                  ipg per         9      k           IbZ               k                              $okay            2default         @                    dma-controller@5a9f0000          2fsl,imx8qm-edma          Z   !          #           .   
      x                                                                                                  P        l      m      n      o      p      q      r      s      t      u      clock-controller@5ac00000            2fsl,imx8qxp-lpcg             Z             %                  `                              i2c0_lpcg_clk i2c0_lpcg_ipg_clk               `        O         clock-controller@5ac10000            2fsl,imx8qxp-lpcg             Z             %                  a                              i2c1_lpcg_clk i2c1_lpcg_ipg_clk               a        O         clock-controller@5ac20000            2fsl,imx8qxp-lpcg             Z             %                  b                              i2c2_lpcg_clk i2c2_lpcg_ipg_clk               b        O         clock-controller@5ac30000            2fsl,imx8qxp-lpcg             Z             %                  c                              i2c3_lpcg_clk i2c3_lpcg_ipg_clk               c        O         clock-controller@5ac80000            2fsl,imx8qxp-lpcg             Z             %                  e                              adc0_lpcg_clk adc0_lpcg_ipg_clk               e        O         clock-controller@5ac90000            2fsl,imx8qxp-lpcg             Z             %                  f                              adc1_lpcg_clk adc1_lpcg_ipg_clk               f        O         clock-controller@5acd0000            2fsl,imx8qxp-lpcg             Z             %                  i                                 5  can0_lpcg_pe_clk can0_lpcg_ipg_clk can0_lpcg_chi_clk                  i        O         clock-controller@5a4a0000            2fsl,imx8qxp-lpcg             ZJ             %                  =                           '  uart4_lpcg_baud_clk uart4_lpcg_ipg_clk                =      i2c@5a840000          #   2fsl,imx8qm-lpi2c fsl,imx7ulp-lpi2c           Z    @               X                                              per ipg         9      d           In6               d      	  $disabled          clock-controller@5ac40000            2fsl,imx8qxp-lpcg             Z             %                  d                              i2c4_lpcg_clk i2c4_lpcg_ipg_clk               d        O         clock-controller@5ace0000            2fsl,imx8qxp-lpcg             Z             %                  j                                 5  can1_lpcg_pe_clk can1_lpcg_ipg_clk can1_lpcg_chi_clk                  j        O         clock-controller@5acf0000            2fsl,imx8qxp-lpcg             Z             %                  k                                 5  can2_lpcg_pe_clk can2_lpcg_ipg_clk can2_lpcg_chi_clk                  k        O            clock-conn-axi           2fixed-clock         %            CU        conn_axi_clk            O         clock-conn-ahb           2fixed-clock         %            	!        conn_ahb_clk            O         clock-conn-ipg           2fixed-clock         %                    conn_ipg_clk            O         clock-conn-bch           2fixed-clock         %            ׄ         conn_bch_clk          bus@5b000000             2simple-bus                                   [       [         usb@5b0d0000          -   2fsl,imx7ulp-usb fsl,imx6ul-usb fsl,imx27-usb             [                                                                                                                                 	  $disabled          usbmisc@5b0d0200                     8   2fsl,imx7ulp-usbmisc fsl,imx7d-usbmisc fsl,imx6q-usbmisc          [            O         usbphy@5b100000       %   2fsl,imx8qm-usbphy fsl,imx7ulp-usbphy             [                                       	  $disabled            O         mmc@5b010000                               [                                         ipg ahb per                       $okay          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc                          2default         @                       &         ,         4      mmc@5b020000                               [                                         ipg ahb per                       B           W           $okay          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc                          2default         @                      g           s                 |                mmc@5b030000                               [                                         ipg ahb per                     	  $disabled          3   2fsl,imx8qm-usdhc fsl,imx8qxp-usdhc fsl,imx7d-usdhc                        ethernet@5b040000            [           0                                                                                  ipg ahb enet_clk_ref ptp            9                          I沀sY@                                            $okay             2fsl,imx8qm-fec fsl,imx6sx-fec                           2default         @         	  rgmii-id                           mdio                                 ethernet-phy@0           2ethernet-phy-ieee802.3-c22                       O         ethernet-phy@1           2ethernet-phy-ieee802.3-c22                      O               ethernet@5b050000            [           0                                                                                 ipg ahb enet_clk_ref ptp            9                          I沀sY@                                            $okay             2fsl,imx8qm-fec fsl,imx6sx-fec                           2default         @           rgmii-txid                                           mac-address                          usb@5b110000             2fsl,imx8qm-usb3          [                                             (                                          lpm bus aclk ipg core           9                I沀                     $okay       usb@5b120000          
   2cdns,usb3            [     [     [             otg xhci dev                       0                                              host peripheral otg wakeup          %           *cdns3,usb3-phy          4           $okay            Kotg          S   port       endpoint                       O                  usb-phy@5b160000             2nxp,salvo-phy            [                            salvo_phy_clk                        c            $okay            O         clock-controller@5b200000            2fsl,imx8qxp-lpcg             [              %                                                   9  sdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk                          O         clock-controller@5b210000            2fsl,imx8qxp-lpcg             [!             %                                                   9  sdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk                          O         clock-controller@5b220000            2fsl,imx8qxp-lpcg             ["             %                                                   9  sdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk                          O         clock-controller@5b230000            2fsl,imx8qxp-lpcg             [#             %         0                                                                          enet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk                          O         clock-controller@5b240000            2fsl,imx8qxp-lpcg             [$             %         0                                                                          enet1_lpcg_timer_clk enet1_lpcg_txc_sampling_clk enet1_lpcg_ahb_clk enet1_lpcg_rgmii_txc_clk enet1_lpcg_ipg_clk enet1_lpcg_ipg_s_clk                          O         clock-controller@5b270000            2fsl,imx8qxp-lpcg             ['             %                                      "  usboh3_ahb_clk usboh3_phy_ipg_clk                        O         clock-controller@5b280000            2fsl,imx8qxp-lpcg             [(             %                                    0                                          M  usb3_app_clk usb3_lpm_clk usb3_ipg_clk usb3_core_pclk usb3_phy_clk usb3_aclk                         O         clock-controller@5b290000            2fsl,imx8qxp-lpcg             [)             %                  	        	                                    '  gpmi_bch gpmi_io gpmi_apb gpmi_bch_apb               	        O         clock-controller@5b290004            2fsl,imx8qxp-lpcg             [)            %                                  apbhdma_hclk                 	        O         dma-controller@5b810000       (   2fsl,imx8qxp-dma-apbh fsl,imx28-dma-apbh          [            0                                              #           .                                	        O         nand-controller@5b812000             2fsl,imx8qxp-gpmi-nand            [      [@             gpmi-nand bch                                                      bch                                          '  gpmi_io gpmi_apb gpmi_bch gpmi_bch_apb                         rx-tx                	        9     	           I      	  $disabled             clock-lsio-bus           2fixed-clock         %                     lsio_bus_clk            O         bus@5d000000             2simple-bus                                    ]       ]                      pwm@5d000000             2fsl,imx27-pwm            ]              ipg per                              9                 In6                           ^         	  $disabled          pwm@5d010000             2fsl,imx27-pwm            ]             ipg per                              9                 In6                           _         	  $disabled          pwm@5d020000             2fsl,imx27-pwm            ]             ipg per                              9                 In6                           `         	  $disabled          pwm@5d030000             2fsl,imx27-pwm            ]             ipg per                              9                 In6                           a         	  $disabled          gpio@5d080000            ]                                ^        n                                              2fsl,imx8qm-gpio fsl,imx35-gpio        0  n                                   $           O         gpio@5d090000            ]	                                ^        n                                              2fsl,imx8qm-gpio fsl,imx35-gpio        @  n          (            2            ?            H           O         gpio@5d0a0000            ]
                                ^        n                                              2fsl,imx8qm-gpio fsl,imx35-gpio        0  n          P            U            h   
      gpio@5d0b0000            ]                                ^        n                                              2fsl,imx8qm-gpio fsl,imx35-gpio          n          r            u                                                                                                                                   O   z      gpio@5d0c0000            ]                                ^        n                                              2fsl,imx8qm-gpio fsl,imx35-gpio        `  n                                                                                 O         gpio@5d0d0000            ]                                ^        n                                              2fsl,imx8qm-gpio fsl,imx35-gpio          n                                                                                                         O         gpio@5d0e0000            ]                                ^        n                                              2fsl,imx8qm-gpio fsl,imx35-gpio           n             
      
            gpio@5d0f0000            ]                                ^        n                                              2fsl,imx8qm-gpio fsl,imx35-gpio        spi@5d120000                                       2nxp,imx8qxp-fspi             ]                   fspi_base fspi_mmap                \                                      fspi_en fspi                          $okay            2default         @      flash@0                                                2jedec,spi-nor           zk@                               mailbox@5d1b0000             ]                               s         	  $disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d1c0000             ]                               s         ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu         O         mailbox@5d1d0000             ]                               s         	  $disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d1e0000             ]                               s         	  $disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d1f0000             ]                               s         	  $disabled          ,   2fsl,imx8-mu-scu fsl,imx8qm-mu fsl,imx6sx-mu       mailbox@5d200000             ]                                s                         $okay             2fsl,imx8qm-mu fsl,imx6sx-mu         O         mailbox@5d210000             ]!                               s                         $okay             2fsl,imx8qm-mu fsl,imx6sx-mu         O         mailbox@5d280000             ](                               s                          2fsl,imx8qm-mu fsl,imx6sx-mu         O         clock-controller@5d400000            2fsl,imx8qxp-lpcg             ]@             %         4                                                                        h  pwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk                       O         clock-controller@5d410000            2fsl,imx8qxp-lpcg             ]A             %         4                                                                        h  pwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk                       O         clock-controller@5d420000            2fsl,imx8qxp-lpcg             ]B             %         4                                                                        h  pwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk                       O         clock-controller@5d430000            2fsl,imx8qxp-lpcg             ]C             %         4                                                                        h  pwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk                       O         clock-controller@5d440000            2fsl,imx8qxp-lpcg             ]D             %         4                                                                        h  pwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk                     clock-controller@5d450000            2fsl,imx8qxp-lpcg             ]E             %         4                                                                        h  pwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk                     clock-controller@5d460000            2fsl,imx8qxp-lpcg             ]F             %         4                                                                        h  pwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk                     clock-controller@5d470000            2fsl,imx8qxp-lpcg             ]G             %         4                                                                        h  pwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk                        clock-hsio-axi           2fixed-clock         %            ׄ         hsio_axi_clk            O         clock-hsio-per           2fixed-clock         %            U        hsio_per_clk            O         clock-hsio-refa          2gpio-gate-clock                     %                             O         clock-hsio-refb          2gpio-gate-clock                     %                           clock-xtal100m           2fixed-clock         %                     xtal_100MHz         O         bus@5f000000             2simple-bus        0  _       _      @       `             p                                                       pcie@5f010000            2fsl,imx8q-pcie           _                  dbi config        0                                                                   f          h           msi dma                                                             dbi mstr slv                            pci                                  i                            j                            k                            l                                                                               	  $disabled            %                  	  *pcie-phy            @           2default                         pcie-ep@5f010000             2fsl,imx8q-pcie-ep            _                   dbi addr_space                            h           dma                                    dbi mstr slv                                     &           5         	  $disabled          clock-controller@5f060000            2fsl,imx8qxp-lpcg             _                               %                          F  hsio_pcieb_mstr_axi_clk hsio_pcieb_slv_axi_clk hsio_pcieb_dbi_axi_clk                         O         clock-controller@5f0b0000            2fsl,imx8qxp-lpcg             _                         %                      hsio_phyx1_per_clk                        O         clock-controller@5f0d0000            2fsl,imx8qxp-lpcg             _                         %                      hsio_pcieb_per_clk                        O         clock-controller@5f0f0000            2fsl,imx8qxp-lpcg             _                         %                      hsio_misc_per_clk                         O         pcie@5f000000            2fsl,imx8q-pcie           _      O             dbi config        0             O                @   @                                   F           msi                                                             dbi mstr slv                            pci                                  I                            J                            K                            L                                                                                 $okay            %                    	  *pcie-phy            @           2default                          D         pcie-ep@5f000000             2fsl,imx8q-pcie-ep            _      @              dbi addr_space                            H           dma                                    dbi mstr slv                                     &           5         	  $disabled          sata@5f020000            2fsl,imx8qm-ahci          _                    X                                sata sata_ref           *sata-phy cali-phy0 cali-phy1                        0  %                                               $okay          clock-controller@5f050000            2fsl,imx8qxp-lpcg             _                               %                          F  hsio_pciea_mstr_axi_clk hsio_pciea_slv_axi_clk hsio_pciea_dbi_axi_clk                         O         clock-controller@5f070000            2fsl,imx8qxp-lpcg             _                         %                      hsio_sata_clk                         O         clock-controller@5f080000            2fsl,imx8qxp-lpcg             _                                  %                              L  hsio_phyx2_pclk_0 hsio_phyx2_pclk_1 hsio_phyx2_apbclk_0 hsio_phyx2_apbclk_1                       O         clock-controller@5f090000            2fsl,imx8qxp-lpcg             _	                                  %                              Q  hsio_phyx1_pclk hsio_phyx1_epcs_tx_clk hsio_phyx1_epcs_rx_clk hsio_phyx1_apb_clk                          O         clock-controller@5f0a0000            2fsl,imx8qxp-lpcg             _
                         %                      hsio_phyx2_per_clk                        O         clock-controller@5f0c0000            2fsl,imx8qxp-lpcg             _                         %                      hsio_pciea_per_clk                        O         clock-controller@5f0e0000            2fsl,imx8qxp-lpcg             _                         %                      hsio_sata_per_clk                         O         phy@5f180000             2fsl,imx8qm-hsio           _     _     _     _             reg phy ctrl misc         p                                                                                               v  pclk0 pclk1 apb_pclk0 apb_pclk1 pclk2 epcs_tx epcs_rx apb_pclk2 phy0_crr phy1_crr ctl0_crr ctl1_crr ctl2_crr misc_crr           c                               $okay            Qpciea-pcieb-sata            ^input           O            chosen          r/bus@5a000000/serial@5a060000         memory@80000000          memory                      @         reserved-memory                                      memory@90000000                                 ~        O         memory@90008000                                ~        O         memory@90010000                                ~        O         memory@90018000                               ~        O         memory@900ff000                               ~        O         memory@90100000                                ~        O         memory@90108000                               ~        O         memory@90110000                                ~        O         memory@90118000                               ~        O         memory@901ff000                               ~        O         memory@90400000          2shared-dma-pool              @                  ~        O         memory@92400000              @                  ~        O         memory@942f0000              /                  ~        O         memory@942f8000              /                 ~        O         memory@94300000          2shared-dma-pool              0                  ~        O            backlight-lvds0          2pwm-backlight                                      d           d           P      backlight-lvds1          2pwm-backlight                                      d           d           P      mux-controller           2nxp,cbdtu02043 gpio-sbu-mux         2default         @                                                  port       endpoint                       O               usdhc2-vmmc          2regulator-fixed       	  SD1_SPWR             -        	 -        !                   	+        O         regulator-audio          2regulator-fixed         cs42888_supply           2Z        	 2Z        O         regulator-fec2-nvcc          2regulator-fixed       
  fec2_nvcc            w@        	 w@        !                    	+        O         regulator-can01-gen          2regulator-fixed       	  can01-en             2Z        	 2Z        !                   	+        O         regulator-can2-gen           2regulator-fixed         can2-en          2Z        	 2Z        !                   	+        O         regulator-can01-stby             2regulator-fixed         can01-stby           2Z        	 2Z        !                   	+        	>           O         regulator-can2-stby          2regulator-fixed       
  can2-stby            2Z        	 2Z        !                   	+        	>           O         regulator-pcie           2regulator-fixed         @           2default         	 2Z         2Z      
  mpcie_3v3           !                   	+        O         regulator-adc-vref           2regulator-fixed       	  vref_1v8             w@        	 w@        O         regulator-audio-pwr          2regulator-fixed       	  audio-5v             LK@        	 LK@         	I         	]        O         regulator-audio-3v3          2regulator-fixed       
  audio-3v3            2Z        	 2Z         	I         	]        O         regulator-audio-1v8          2regulator-fixed       
  audio-1v8            w@        	 w@         	I         	]        O         audio-codec-bt           2linux,bt-sco                       O         sound-bt-sco             2simple-audio-card           	obt-sco-audio            	dsp_a            	        	           	      simple-audio-card,cpu           
           
           
            O         simple-audio-card,codec         
               sound-cs42888            2fsl,imx-audio-cs42888            ,imx-cs42888         
3           
=           
I           
TLine Out Jack AOUT1L Line Out Jack AOUT1R Line Out Jack AOUT2L Line Out Jack AOUT2R Line Out Jack AOUT3L Line Out Jack AOUT3R Line Out Jack AOUT4L Line Out Jack AOUT4R AIN1L Line In Jack AIN1R Line In Jack AIN2L Line In Jack AIN2R Line In Jack       sound-wm8960             2fsl,imx-audio-wm8960             ,wm8960-audio            
3           
=           
b                  
THeadphone Jack HP_L Headphone Jack HP_R Ext Spk SPK_LP Ext Spk SPK_LN Ext Spk SPK_RP Ext Spk SPK_RN LINPUT1 Mic Jack Mic Jack MICB        imx8qm-cm4-0             2fsl,imx8qm-cm4                      tx rx rxdb        $  
                                    +                                    )        
n          
~4        imx8qm-cm4-1             2fsl,imx8qm-cm4                      tx rx rxdb        $  
                                    +                               *     =        
n  *        
~8           	interrupt-parent #address-cells #size-cells model compatible mmc0 mmc1 mmc2 serial0 serial1 serial2 serial3 spi0 spi1 spi2 spi3 vpu-core0 vpu-core1 vpu-core2 device_type reg clocks enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache operating-points-v2 #cooling-cells phandle cache-level cache-unified opp-shared opp-hz opp-microvolt clock-latency-ns opp-suspend #interrupt-cells interrupt-controller interrupts #global-interrupts #iommu-cells mbox-names mboxes #power-domain-cells #clock-cells pinctrl-names pinctrl-0 fsl,pins read-only #thermal-sensor-cells polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device clock-frequency clock-output-names ranges clock-names power-domains firmware-name status memory-region assigned-clocks assigned-clock-rates gpio-controller #gpio-cells VA-supply VD-supply VLS-supply VLC-supply reset-gpios clock-indices dmas dma-names fsl,asrc-rate fsl,asrc-width fsl,asrc-clk-map assigned-clock-parents #sound-dai-cells #dma-cells dma-channels dma-channel-mask fsl,sai-asynchronous dais fsl,dataline #mbox-cells fsl,channel fsl,num-irqs #pwm-cells cs-gpios label power-role data-role source-pdos remote-endpoint pinctrl-1 scl-gpios sda-gpios wlf,shared-lrclk wlf,hp-cfg wlf,gpio-cfg AVDD-supply DBVDD-supply DCVDD-supply SPKVDD1-supply SPKVDD2-supply #io-channel-cells vref-supply fsl,clk-source fsl,scu-index xceiver-supply fsl,usbphy fsl,usbmisc ahb-burst-config tx-burst-size-dword rx-burst-size-dword #index-cells iommus bus-width no-sd no-sdio non-removable fsl,tuning-start-tap fsl,tuning-step vmmc-supply cd-gpios wp-gpios fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle fsl,magic-packet phy-supply nvmem-cells nvmem-cell-names rx-internal-delay-ps reg-names interrupt-names phys phy-names cdns,on-chip-buff-size dr_mode usb-role-switch #phy-cells gpio-ranges spi-max-frequency spi-tx-bus-width spi-rx-bus-width enable-gpios dma-ranges bus-range interrupt-map interrupt-map-mask num-lanes num-viewport fsl,max-link-speed reset-gpio num-ib-windows num-ob-windows vpcie-supply fsl,hsio-cfg fsl,refclk-pad-mode stdout-path no-map pwms brightness-levels num-interpolated-steps default-brightness-level select-gpios orientation-switch regulator-name regulator-min-microvolt regulator-max-microvolt enable-active-high vin-supply regulator-always-on regulator-boot-on simple-audio-card,name simple-audio-card,format simple-audio-card,bitclock-inversion simple-audio-card,frame-master simple-audio-card,bitclock-master sound-dai dai-tdm-slot-num dai-tdm-slot-width audio-cpu audio-codec audio-asrc audio-routing hp-det-gpio fsl,resource-id fsl,entry-address 