  ]	   8  U   (              T                             !    bananapi,bpi-r4 mediatek,mt7988a                                     +            7Banana Pi BPI-R4 (2x SFP+)        	   =embedded       cpus                         +       cpu@0             arm,cortex-a73           J             Ncpu          Zpsci             h                      ocpu intermediate             {                           $      cpu@1             arm,cortex-a73           J            Ncpu          Zpsci             h                      ocpu intermediate             {                           %      cpu@2             arm,cortex-a73           J            Ncpu          Zpsci             h                      ocpu intermediate             {                           &      cpu@3             arm,cortex-a73           J            Ncpu          Zpsci             h                      ocpu intermediate             {                           '      opp-table-0           operating-points-v2                          opp-800000000                /           P      opp-1100000000               A           P      opp-1500000000               Yh/           P      opp-1800000000               kI                       oscillator-40m            fixed-clock          bZ                       clkxtal       pmu           arm,cortex-a73-pmu                                      psci              arm,psci-0.2             asmc       reserved-memory                      +                secmon@43000000          J    C                            soc           simple-bus                                 +      interrupt-controller@c000000              arm,gic-v3        P   J                                @              A             B                                     	                    !                     clock-controller@10001000              mediatek,mt7988-infracfg syscon          J                                 2                     clock-controller@1001b000              mediatek,mt7988-topckgen syscon          J                                          watchdog@1001c000             mediatek,mt7988-wdt          J                            n           2           ?okay                      clock-controller@1001e000             mediatek,mt7988-apmixedsys           J                                          pinctrl@1001f000              mediatek,mt7988-pinctrl       p   J                                                                                                7  Fgpio iocfg_tr iocfg_br iocfg_rb iocfg_lb iocfg_tl eint           P        `           l              T                                                !                  pcie0-pins                 mux         xpcie          3  pcie_2l_0_pereset pcie_clk_req_n0_0 pcie_wake_n0_0           pcie1-pins                 mux         xpcie          1  pcie_2l_1_pereset pcie_clk_req_n1 pcie_wake_n1_0             pcie2-pins                 mux         xpcie          3  pcie_1l_0_pereset pcie_clk_req_n2_0 pcie_wake_n2_0           pcie3-pins                 mux         xpcie          1  pcie_1l_1_pereset pcie_clk_req_n3 pcie_wake_n3_0             spi1-pins                  mux         xspi         spi1             uart0-pins                 mux         xuart            uart0            mdio0-pins              (   mux         xeth       
  mdc_mdio0         conf            SMI_0_MDC SMI_0_MDIO                        i2c0-g0-pins                	   mux         xi2c         i2c0_1           i2c1-g0-pins                )   mux         xi2c         i2c1_0           i2c1-sfp-g0-pins                *   mux         xi2c       	  i2c1_sfp             i2c2-g0-pins                +   mux         xi2c         i2c2_0           i2c2-g1-pins                   mux         xi2c         i2c2_1           gbe0-led0-pins              ,   mux         xled       
  gbe0_led0            gbe1-led0-pins              -   mux         xled       
  gbe1_led0            gbe2-led0-pins              .   mux         xled       
  gbe2_led0            gbe3-led0-pins              /   mux         xled       
  gbe3_led0            gbe0-led1-pins              0   mux         xled       
  gbe0_led1            gbe1-led1-pins              1   mux         xled       
  gbe1_led1            gbe2-led1-pins              2   mux         xled       
  gbe2_led1            gbe3-led1-pins              3   mux         xled       
  gbe3_led1            2p5gbe-led0-pins                4   mux         xled         2p5gbe_led0          2p5gbe-led1-pins                5   mux         xled         2p5gbe_led1          mmc0-emmc-45-pins               6   mux         xflash           emmc_45          mmc0-emmc-51-pins               7   mux         xflash           emmc_51          mmc0-sdcard-pins                8   mux         xflash           sdcard           snfi-pins               9   mux         xflash           snfi             spi0-pins               :   mux         xspi         spi0             spi0-flash-pins                mux         xspi         spi0 spi0_wp_hold            spi2-pins               ;   mux         xspi         spi2             spi2-flash-pins             <   mux         xspi         spi2 spi2_wp_hold               pwm@10048000              mediatek,mt7988-pwm          J                  P   h                                                             !      1   otop main pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 pwm8                       ?okay                #      mcusys@100e0000           mediatek,mt7988-mcusys syscon            J                                           serial@11000000       *    mediatek,mt7988-uart mediatek,mt6577-uart            J                              {           uart wakeup          h      '      /      	   obaud bus            default                    ?okay                =      serial@11000100       *    mediatek,mt7988-uart mediatek,mt6577-uart            J                             |           uart wakeup          h      '      0      	   obaud bus          	  ?disabled          serial@11000200       *    mediatek,mt7988-uart mediatek,mt6577-uart            J                             }           uart wakeup          h      '      1      	   obaud bus          	  ?disabled          i2c@11003000              mediatek,mt7981-i2c           J     0            !p                                              h      .      *      	   omain dma                         +            ?okay            default            	            >   rt5190a@64            richtek,rt5190a          J   d           
           
           
            ?   regulators     buck1           rt5190a-buck1            M        $ M        <                T         f            
      buck2           vcore            	'        $ \         T         f      buck3           vproc            	'        $ \         T                  buck4           rt5190a-buck4            w@        $ w@        <                T         f      ldo         rt5190a-ldo          w@        $ w@         T         f               i2c@11004000              mediatek,mt7981-i2c           J     @            !q                                               h      .      *      	   omain dma                         +          	  ?disabled                @      i2c@11005000              mediatek,mt7981-i2c           J     P            !q                                              h      .      *      	   omain dma                         +            ?okay            default                        A   i2c-mux@70            nxp,pca9545          J   p        z                              +                B   i2c@0                        +             J       rtc@51            nxp,pcf8563          J   Q                         C      eeprom@57             atmel,24c02          J   W                    i2c@1                        +             J               D      i2c@2                        +             J               E            spi@11007000          *    mediatek,mt7988-spi-quad mediatek,spi-ipm            J     p                                     h            *      5      8          oparent-clk sel-clk spi-clk hclk                      +            ?okay            default                        F   flash@0       	    spi-nand             J            u                                   G   partitions            fixed-partitions                         +      partition@0         bl2          J                                spi@11008000          ,    mediatek,mt7988-spi-single mediatek,spi-ipm          J                                          h            +      6      9          oparent-clk sel-clk spi-clk hclk                      +            default                    ?okay                H      spi@11009000          *    mediatek,mt7988-spi-quad mediatek,spi-ipm            J                                          h            *      7      :          oparent-clk sel-clk spi-clk hclk                      +          	  ?disabled                I      lvts@1100a000             mediatek,mt7988-lvts-ap                     J                      h      -                                                    lvts-calib-data-1                     usb@11190000          '    mediatek,mt7988-xhci mediatek,mtk-xhci            J            .     >              	  Fmac ippc                             (   h      K      M      I      G      U      $   osys_ck ref_ck mcu_ck dma_ck xhci_ck         	                  	  ?disabled          usb@11200000          '    mediatek,mt7988-xhci mediatek,mtk-xhci            J             .      >              	  Fmac ippc                             (   h      L      N      J      H      V      $   osys_ck ref_ck mcu_ck dma_ck xhci_ck         	                    ?okay                J      mmc@11230000              mediatek,mt7988-mmc           J    #                                                   h      ?      @      B      A              (      )                             osource hclk axi_cg ahb_cg                        +          	  ?disabled                K      pcie@11280000         *    mediatek,mt7986-pcie mediatek,mt8192-pcie            Npci                      +            J    (                	  Fpcie-mac            5                              F             8                                                                 h      ]      Y            a      !   opl_250m tl_26m peri_26m top_133m            default                    ?okay            	            	  Ppcie-phy            !           Z                     `  m                                                                                                 L   interrupt-controller                         !                                 pcie@11290000         *    mediatek,mt7986-pcie mediatek,mt8192-pcie            Npci                      +            J    )                	  Fpcie-mac            5                              F             8          (       (                  (       (                   h      ^      Z            b      !   opl_250m tl_26m peri_26m top_133m            default                    ?okay            !           Z                     `  m                                                                                                 M   interrupt-controller                         !                                 pcie@11300000         *    mediatek,mt7986-pcie mediatek,mt8192-pcie            Npci                      +            J    0                	  Fpcie-mac            5                               F             8          0       0                  0       0                   h      [      W            _      !   opl_250m tl_26m peri_26m top_133m            default                    ?okay            !           Z                     `  m                                                                                                 N   interrupt-controller                         !                                 pcie@11310000         *    mediatek,mt7986-pcie mediatek,mt8192-pcie            Npci                      +            J    1                	  Fpcie-mac            5                              F             8          8       8                  8       8                   h      \      X            `      !   opl_250m tl_26m peri_26m top_133m            default                    ?okay            !           Z                     `  m                                                                                                 O   interrupt-controller                         !                                 t-phy@11c50000        .    mediatek,mt7986-tphy mediatek,generic-tphy-v2                        +                     ?okay                P   usb-phy@11c50000             J                      h      T         oref         {                     usb-phy@11c50700             J           	          h      R         oref         {                        system-controller@11d10084            mediatek,mt7988-topmisc syscon           J                             xs-phy@11e10000       %    mediatek,mt7988-xsphy mediatek,xsphy                         +                     ?okay                Q   usb-phy@11e10000             J                      h      S         oref         {                     usb-phy@11e13000             J    4                 h      Q         oref         {                                         clock-controller@11f40000             mediatek,mt7988-xfi-pll          J                                             efuse@11f50000        %    mediatek,mt7988-efuse mediatek,efuse             J                                  +      calib@918            J  	   (                  calib@940            J  	@               R      calib@954            J  	T               S      calib@968            J  	h               T      calib@97c            J  	|               U         clock-controller@15000000             mediatek,mt7988-ethsys syscon            J                                  2         clock-controller@15031000             mediatek,mt7988-ethwarp          J                                2            thermal-zones      cpu-thermal                                                V   trips      crit             H                	   Ecritical                W      hot                             Ehot             X      active-high          8                   Eactive                     active-med           L                   Eactive              !      active-low            @                   Eactive              "         cooling-maps       map-cpu-active-high                                    map-cpu-active-med                              !      map-cpu-active-low                              "               timer             arm,armv8-timer                   0                                    
         chosen          serial0:115200n8          pwm-fan           pwm-fan                P                         $   #      P        ?okay                      regulator-1p8v            regulator-fixed         fixed-1.8V           w@        $ w@         T         f            Y      regulator-3p3v            regulator-fixed         fixed-3.3V           2Z        $ 2Z         T         f            Z      __symbols__         )/cpus/cpu@0         ./cpus/cpu@1         3/cpus/cpu@2         8/cpus/cpu@3         =/cpus/opp-table-0         "  J/soc/interrupt-controller@c000000           N/soc/clock-controller@10001000          W/soc/clock-controller@1001b000          `/soc/watchdog@1001c000          i/soc/clock-controller@1001e000          t/soc/pinctrl@1001f000         !  x/soc/pinctrl@1001f000/pcie0-pins          !  /soc/pinctrl@1001f000/pcie1-pins          !  /soc/pinctrl@1001f000/pcie2-pins          !  /soc/pinctrl@1001f000/pcie3-pins             /soc/pinctrl@1001f000/spi1-pins       !  /soc/pinctrl@1001f000/uart0-pins          !  /soc/pinctrl@1001f000/mdio0-pins          #  /soc/pinctrl@1001f000/i2c0-g0-pins        #  /soc/pinctrl@1001f000/i2c1-g0-pins        '  /soc/pinctrl@1001f000/i2c1-sfp-g0-pins        #  /soc/pinctrl@1001f000/i2c2-g0-pins        #  /soc/pinctrl@1001f000/i2c2-g1-pins        %  /soc/pinctrl@1001f000/gbe0-led0-pins          %  /soc/pinctrl@1001f000/gbe1-led0-pins          %  /soc/pinctrl@1001f000/gbe2-led0-pins          %  +/soc/pinctrl@1001f000/gbe3-led0-pins          %  :/soc/pinctrl@1001f000/gbe0-led1-pins          %  I/soc/pinctrl@1001f000/gbe1-led1-pins          %  X/soc/pinctrl@1001f000/gbe2-led1-pins          %  g/soc/pinctrl@1001f000/gbe3-led1-pins          '  v/soc/pinctrl@1001f000/2p5gbe-led0-pins        '  /soc/pinctrl@1001f000/2p5gbe-led1-pins        (  /soc/pinctrl@1001f000/mmc0-emmc-45-pins       (  /soc/pinctrl@1001f000/mmc0-emmc-51-pins       '  /soc/pinctrl@1001f000/mmc0-sdcard-pins           /soc/pinctrl@1001f000/snfi-pins          /soc/pinctrl@1001f000/spi0-pins       &  /soc/pinctrl@1001f000/spi0-flash-pins            /soc/pinctrl@1001f000/spi2-pins       &  /soc/pinctrl@1001f000/spi2-flash-pins           /soc/pwm@10048000           /soc/mcusys@100e0000            /soc/serial@11000000             /soc/i2c@11003000           %/soc/i2c@11003000/rt5190a@64          .  0/soc/i2c@11003000/rt5190a@64/regulators/buck1         .  =/soc/i2c@11003000/rt5190a@64/regulators/buck3           J/soc/i2c@11004000           O/soc/i2c@11005000           T/soc/i2c@11005000/i2c-mux@70          *  \/soc/i2c@11005000/i2c-mux@70/i2c@0/rtc@51         #  d/soc/i2c@11005000/i2c-mux@70/i2c@1        #  m/soc/i2c@11005000/i2c-mux@70/i2c@2          v/soc/spi@11007000           {/soc/spi@11007000/flash@0           /soc/spi@11008000           /soc/spi@11009000           /soc/lvts@1100a000          /soc/usb@11200000           /soc/mmc@11230000           /soc/pcie@11280000        (  /soc/pcie@11280000/interrupt-controller         /soc/pcie@11290000        (  /soc/pcie@11290000/interrupt-controller         /soc/pcie@11300000        (  /soc/pcie@11300000/interrupt-controller         /soc/pcie@11310000        (  /soc/pcie@11310000/interrupt-controller         /soc/t-phy@11c50000       %  /soc/t-phy@11c50000/usb-phy@11c50000          %  /soc/t-phy@11c50000/usb-phy@11c50700              /soc/system-controller@11d10084         /soc/xs-phy@11e10000          &  /soc/xs-phy@11e10000/usb-phy@11e10000         &  /soc/xs-phy@11e10000/usb-phy@11e13000           &/soc/efuse@11f50000/calib@918           7/soc/efuse@11f50000/calib@940           J/soc/efuse@11f50000/calib@954           ]/soc/efuse@11f50000/calib@968           p/soc/efuse@11f50000/calib@97c           /thermal-zones/cpu-thermal        &  /thermal-zones/cpu-thermal/trips/crit         %  /thermal-zones/cpu-thermal/trips/hot          -  /thermal-zones/cpu-thermal/trips/active-high          ,  /thermal-zones/cpu-thermal/trips/active-med       ,  /thermal-zones/cpu-thermal/trips/active-low       	  /pwm-fan            /regulator-1p8v         /regulator-3p3v          	compatible interrupt-parent #address-cells #size-cells model chassis-type reg device_type enable-method clocks clock-names operating-points-v2 proc-supply phandle opp-shared opp-hz opp-microvolt clock-frequency #clock-cells clock-output-names interrupts ranges no-map interrupt-controller #interrupt-cells #reset-cells status reg-names gpio-controller #gpio-cells gpio-ranges function groups pins drive-strength #pwm-cells interrupt-names pinctrl-names pinctrl-0 clock-div vin2-supply vin3-supply vin4-supply regulator-name regulator-min-microvolt regulator-max-microvolt regulator-allowed-modes regulator-boot-on regulator-always-on reset-gpios size spi-max-frequency spi-tx-bus-width spi-rx-bus-width label read-only #thermal-sensor-cells resets nvmem-cells nvmem-cell-names phys assigned-clocks assigned-clock-parents linux,pci-domain bus-range phy-names interrupt-map-mask interrupt-map #phy-cells mediatek,syscon-type polling-delay-passive polling-delay thermal-sensors temperature hysteresis cooling-device trip stdout-path cooling-levels #cooling-cells pwms cpu0 cpu1 cpu2 cpu3 cluster0_opp gic infracfg topckgen watchdog apmixedsys pio pcie0_pins pcie1_pins pcie2_pins pcie3_pins spi1_pins uart0_pins mdio0_pins i2c0_pins i2c1_pins i2c1_sfp_pins i2c2_0_pins i2c2_1_pins gbe0_led0_pins gbe1_led0_pins gbe2_led0_pins gbe3_led0_pins gbe0_led1_pins gbe1_led1_pins gbe2_led1_pins gbe3_led1_pins i2p5gbe_led0_pins i2p5gbe_led1_pins mmc0_pins_emmc_45 mmc0_pins_emmc_51 mmc0_pins_sdcard snfi_pins spi0_pins spi0_flash_pins spi2_pins spi2_flash_pins pwm mcusys serial0 i2c0 rt5190a_64 rt5190_buck1 rt5190_buck3 i2c1 i2c2 pca9545 pcf8563 i2c_sfp1 i2c_sfp2 spi0 spi_nand spi1 spi2 lvts ssusb1 mmc0 pcie2 pcie_intc2 pcie3 pcie_intc3 pcie0 pcie_intc0 pcie1 pcie_intc1 tphy tphyu2port0 tphyu3port0 topmisc xsphy xphyu2port0 xphyu3port0 lvts_calibration phy_calibration_p0 phy_calibration_p1 phy_calibration_p2 phy_calibration_p3 cpu_thermal cpu_trip_crit cpu_trip_hot cpu_trip_active_high cpu_trip_active_med cpu_trip_active_low fan reg_1p8v reg_3p3v 