 e   8 X   (             X`                             4    mediatek,mt8395-evk mediatek,mt8395 mediatek,mt8195                                  +         "   7MediaTek Genio 1200 EVK-P1V2-EMMC      aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          /soc/vpp-merge@1c10f000          /soc/vpp-merge@1c110000          /soc/dma-controller@1c104000             /soc/dma-controller@1c105000             /soc/dma-controller@1c106000             /soc/dma-controller@1c107000             /soc/dma-controller@1c108000             /soc/dma-controller@1c109000             /soc/dma-controller@1c10a000             /soc/dma-controller@1c10b000             /soc/serial@11001100             /soc/ethernet@11021000        cpus                         +       cpu@0            cpu           arm,cortex-a55                      psci                           -ec3@        =  4        P              `           m   @                                 @                                            	      cpu@100          cpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `           m   @                                 @                                            
      cpu@200          cpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `           m   @                                 @                                                  cpu@300          cpu           arm,cortex-a55                     psci                           -ec3@        =  4        P              `           m   @                                 @                                                  cpu@400          cpu           arm,cortex-a78                     psci                          -f        =           P              `           m   @                                 @                                                  cpu@500          cpu           arm,cortex-a78                     psci                          -f        =           P              `           m   @                                 @                                                  cpu@600          cpu           arm,cortex-a78                     psci                          -f        =           P              `           m   @                                 @                                                  cpu@700          cpu           arm,cortex-a78                     psci                          -f        =           P              `           m   @                                 @                                                  cpu-map    cluster0       core0              	      core1              
      core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state                                2        *   _        :  D                 cpu-retention-b           arm,idle-state                                -        *           :                   cpu-off-l             arm,idle-state                               7        *           :  H                 cpu-off-b             arm,idle-state                               2        *           :                      l2-cache0             cache           K           b           o   @                               W                 l2-cache1             cache           K           b           o   @                               W                 l3-cache              cache           K           b            o   @                    W                    dsu-pmu           arm,dsu-pmu         e                       p   	   
                          ufail          dmic-codec            dmic-codec          |                    mt8195-sound                     	  udisabled          fixed-factor-clock-13m            fixed-factor-clock                                                       clk13m             *      oscillator-26m            fixed-clock                     -        clk26m                   oscillator-32k            fixed-clock                     -           clk32k        performance-controller@11bc10             mediatek,cpufreq-hw                           0                                   opp-table-gpu             operating-points-v2                     x   opp-390000000               >         	h      opp-410000000               p         	      opp-431000000                        	      opp-473000000               1h@         	<      opp-515000000               F         	<      opp-556000000               !#          	Ҧ      opp-598000000               #         	      opp-640000000               &%          	      opp-670000000               'c         
      opp-700000000               )'          
L      opp-730000000               +         
}      opp-760000000               -L          
`      opp-790000000               /q         
4      opp-820000000               05                opp-850000000               2         @      opp-880000000               4s          q         pmu-a55           arm,cortex-a55-pmu                      e                  pmu-a78           arm,cortex-a78-pmu                      e                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  e                                             
             soc                      +             simple-bus           !        (                          interrupt-controller@c000000              arm,gic-v3          3           D                        [                                             e      	                     ppi-partitions     interrupt-partition-0           p   	   
                       interrupt-partition-1           p                                   syscon@10000000            mediatek,mt8195-topckgen syscon                                                   syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon                                          y                    syscon@10003000           mediatek,mt8195-pericfg syscon               0                              C      pinctrl@10005000              mediatek,mt8195-pinctrl              P                                                                                                         B  iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint                                                      [        e                      3                 audio-default-pins     pins-cmd-dat          4    =  >  A  B  C  D  E  F  G  H  I  J  K         disp-pwm1-default-pins     pins1             h         edp-panel-12v-en-pins                 pins1             `                   edp-panel-3v3-en-pins                 pins1                                eth-default-pins               ?   pins-cc           U  V  W  X                 pins-mdio             Y  Z               pins-power            [   \                pins-rxd              Q  R  S  T      pins-txd              M  N  O  P                    eth-sleep-pins             @   pins-cc           U   V   W   X       pins-mdio             Y   Z                         pins-rxd              Q   R   S   T       pins-txd              M   N   O   P          gpio-keys-pins     pins              j                            i2c0-pins              c   pins                	                              i2c1-pins              d   pins              
                                i2c2-pins              g   pins                                               i2c6-pins              \   pins                                  mmc0-default-pins              H   pins-clk              z                   '   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-rst              x                      e         mmc0-uhs-pins              I   pins-clk              z                   '   f      pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y                               e      pins-ds                              '   f      pins-rst              x                      e         mmc1-default-pins              L   pins-clk              o                   '   f      pins-cmd-dat              n  p  q  r  s                               e         mmc1-uhs-pins              M   pins-clk              o                   '   f      pins-cmd-dat              n  p  q  r  s                               e         mt6360-pins            ]   pins                                             dsi0-vreg-en-pins                 pins-pwr-en           /          6         panel-default-pins                pins-rst              l                pins-en           0          6         pcie0-default-pins             W   pins                                    pcie0-idle-pins            X   pins                                 6         pcie1-default-pins             Z   pins                                    disp-pwm0-pins             6   pins-disp-pwm             a         spi1-pins              7   pins                                      spi-pins               :   pins                                      touch-pins             f   pins-irq                                       pins-reset                               u3-p0-vbus-default-pins            D   pins-vbus             ?                  uart0-pins             1   pins              b  c         uart1-pins             2   pins              d  e  f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd                 `           power-controller          !    mediatek,mt8195-power-controller                         +            A              -   power-domain@8                                  +            A           U      power-domain@9             	                            cmfg alt         o                        +            A           U      power-domain@10            
        A          power-domain@11                    A          power-domain@12                    A          power-domain@13                    A          power-domain@14                    A                power-domain@15                                            	      @      A      K                                                                                                                                cvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           o                        +            A      power-domain@16                  8              $      %      &      '      (      )      D  cvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         o                        +            A      power-domain@17                                              cvppsys1 vppsys1-0 vppsys1-1         o           A          power-domain@22                                                   $  cwepsys-0 wepsys-1 wepsys-2 wepsys-3         o           A          power-domain@23                                    cvdec0-0         o                        +            A       power-domain@24                       !            cvdec1-0         o           A          power-domain@25                       "            cvdec2-0         o           A             power-domain@26                       #            cvenc0-larb          o                        +            A       power-domain@27                       $            cvenc1-larb          o           A             power-domain@18                              %       %      %         &  cvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           o                        +            A      power-domain@19                    o           A          power-domain@20                    o           A          power-domain@21                          Q        chdmi_tx         A             power-domain@28                       &       &   
        cimg-0 img-1         o                        +            A      power-domain@29                    A          power-domain@30                             &      '           cipe ipe-0 ipe-1         o           A             power-domain@31                  (     (       (      (      (      (           ccam-0 cam-1 cam-2 cam-3 cam-4           o                        +            A      power-domain@32                     A          power-domain@33            !        A          power-domain@34            "        A                   power-domain@0                      o           A          power-domain@1                     o           A          power-domain@2                     A          power-domain@3                     A          power-domain@4                           5      7        ccsi_rx_top csi_rx_top1          A          power-domain@5                        )           cether           A          power-domain@6                           X      n        cadsp adsp1                       +            o           A      power-domain@7                            g      "      n      2        caudio audio1 audio2 audio3          o           A                   watchdog@10007000             mediatek,mt8195-wdt                       p                y              0      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon                                                    timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer             p                e      	                  *      pwrap@10024000            mediatek,mt8195-pwrap syscon                @                pwrap           e                                         	  cspi wrap                  $                 pmic              mediatek,mt6359          [        3                                  adc           mediatek,mt6359-auxadc                   audio-codec           mediatek,mt6359-codec                                          regulators            mediatek,mt6359-regulator      buck_vs1            3vs1         B 5         Z !        r                   buck_vgpu11         3vgpu11          B         Z 7                  r                                    buck_vmodem         3vmodem          B         Z           *        r         buck_vpu            3vpu         B         Z 7                  r                                    buck_vcore          3vcore           B         Z                    r                                    buck_vs2            3vs2         B 5         Z j         r                   buck_vpa            3vpa         B          Z 7        r  ,      buck_vproc2         3vproc2          B         Z 7          L        r                           buck_vproc1         3vproc1          B         Z 7          L        r                           buck_vcore_sshub            3vcore_sshub         B         Z 7      buck_vgpu11_sshub           3vgpu11_sshub            B         Z 7      ldo_vaud18          3vaud18          B w@        Z w@        r                  ldo_vsim1           3vsim1           B         Z /M`      ldo_vibr            3vibr            B O        Z 2Z           h      ldo_vrf12           3vrf12           B         Z                 ldo_vusb            3vusb            B -        Z -        r                      E      ldo_vsram_proc2         3vsram_proc2         B          Z           L        r                  ldo_vio18           3vio18           B         Z         r                 ldo_vcamio          3vcamio          B         Z                ldo_vcn18           3vcn18           B w@        Z w@        r         ldo_vfe28           3vfe28           B *        Z *        r   x      ldo_vcn13           3vcn13           B         Z        ldo_vcn33_1_bt          3vcn33_1_bt          B *        Z 5g      ldo_vcn33_1_wifi            3vcn33_1_wifi            B *        Z 5g      ldo_vaux18          3vaux18          B w@        Z w@        r                  ldo_vsram_others            3vsram_others            B q        Z q                  r                    ldo_vefuse          3vefuse          B         Z       ldo_vxo22           3vxo22           B w@        Z !               ldo_vrfck           3vrfck           B `        Z       ldo_vrfck_1         3vrfck           B         Z j       ldo_vbif28          3vbif28          B *        Z *        r         ldo_vio28           3vio28           B *        Z 2Z               ldo_vemc            3vemc            B ,@         Z 2Z      ldo_vemc_1          3vemc            B &%        Z 2Z           J      ldo_vcn33_2_bt          3vcn33_2_bt          B 2Z        Z 2Z           9      ldo_vcn33_2_wifi            3vcn33_2_wifi            B *        Z 5g      ldo_va12            3va12            B O        Z                 ldo_va09            3va09            B 5         Z O      ldo_vrf18           3vrf18           B         Z P      ldo_vsram_md          	  3vsram_md            B          Z           *        r         ldo_vufs            3vufs            B         Z            K      ldo_vm18            3vm18            B         Z                ldo_vbbck           3vbbck           B         Z O               ldo_vsram_proc1         3vsram_proc1         B          Z           L        r                  ldo_vsim2           3vsim2           B         Z /M`      ldo_vsram_others_sshub          3vsram_others_sshub          B          Z          rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi                 p                            pmif spmimst                               E      (  cpmif_sys_ck pmif_tmr_ck spmimst_clk_mux               $                                   +       pmic@6            mediatek,mt6315-regulator                     regulators     vbuck1          3Vbcpu           B         Z 7        r                                          pmic@7            mediatek,mt6315-regulator                     regulators     vbuck1          3Vgpu            B T        Z 8        r                                               infra-iommu@10315000              mediatek,mt8195-iommu-infra             1P       P       P  e                                                                                       T      mailbox@10320000              mediatek,mt8195-gce             2        @         e                                                        mailbox@10330000              mediatek,mt8195-gce             3        @         e                                                  y      scp@10500000              mediatek,mt8195-scp       0      P             r             p                 sram cfg l1tcm          e                     uokay               +        mediatek/mt8195/scp.img            z      clock-controller@10720000             mediatek,mt8195-scp_adsp                r                               ,      dsp@10803000              mediatek,mt8195-dsp              0                           	  cfg sram          ,        X         n         ,          #      K  cadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             -           rx tx              .   /      	  udisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox                           `                e                        .      mailbox@10817000              mediatek,mt8195-adsp-mbox                           p                e                        /      mt8195-afe-pcm@10890000           mediatek,mt8195-audio                                $              -           e      6               6   0         	  =audiosys                                                               g      "      #      n      e      a      b      c      d      2   ,            cclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  udisabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                     	  cbaud bus            uokay            I   1        Sdefault       serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                     	  cbaud bus            uokay            I   2        Sdefault       serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                     	  cbaud bus          	  udisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                    	  cbaud bus          	  udisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                    	  cbaud bus          	  udisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart                                e                                    	  cbaud bus          	  udisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc                                               cmain                     	  udisabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon                0                              )      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 e                                                cparent-clk sel-clk spi-clk        	  udisabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap                              e                                    6               a   3   4      $  mlvts-calib-data-1 lvts-calib-data-2         ~                    svs@1100bc00              mediatek,mt8195-svs                              e                                    cmain            a   5   3      (  msvs-calibration-data t-calibration-data         6              =svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                e                         -                            *      0        cmain mm         uokay            Sdefault         I   6                 pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm                                e                                      +      N        cmain mm       	  udisabled                     spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 e                                        3        cparent-clk sel-clk spi-clk          uokay            I   7        Sdefault                           @      can@0             microchip,mcp2518fd                        8        1-                             9           9         spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                 e                                        4        cparent-clk sel-clk spi-clk          uokay            I   :        Sdefault                   spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                0                e                                        5        cparent-clk sel-clk spi-clk        	  udisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                e                                        <        cparent-clk sel-clk spi-clk        	  udisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +                                e                                        =        cparent-clk sel-clk spi-clk        	  udisabled          spi@1101d000              mediatek,mt8195-spi-slave                               e                            R        cspi                                   	  udisabled          spi@1101e000              mediatek,mt8195-spi-slave                               e                            S        cspi                                   	  udisabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a                      @         e                     macirq        .  caxi apb mac_main ptp_ref rmii_internal mac_cg         0     )       )         R      S      T   )                 R      S      T                                     -                      	   ;           <        ,   =        ?           J           U            uokay            brgmii-rxid          k   >        v      ]                  '  '                           Sdefault sleep           I   ?           @   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916                          >         stmmac-axi-config                                                                     ;      rx-queues-config                                   <   queue0                   /          queue1                   /          queue2                   /          queue3                   /             tx-queues-config            G            ]           =   queue0          o                    {          queue1          o                    {         queue2          o                    {         queue3          o                    {               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3                       -     >              	  mac ippc            !                     ?                      +           e                            /            B        csys_ck ref_ck mcu_ck               A      B                       C      g        uokay            otg         Sdefault         I   D                    E   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         e                            ,      -                          $        /                     B      $  csys_ck ref_ck mcu_ck dma_ck xhci_ck         uokay          ports                        +       port@0                 endpoint               F           _         port@1                endpoint               G           `               mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              #                              e                                                csource hclk source_cg           uokay            Sdefault state_uhs           I   H           I                                      	         	         	#         	4         	<        	B L        	Q   J        	]   K         	j      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              $                              e                                        $        csource hclk source_cg                                       uokay            Sdefault state_uhs           I   L           M                             	x         	         	         	         	4        	Q   N        	]   O         	j      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc              %                              e                                         I        csource hclk source_cg                                      	  udisabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu                '                e                                    6              a   3   4      $  mlvts-calib-data-1 lvts-calib-data-2         ~                    usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci               )             )>              	  mac ippc            e                        P      Q                 .      /                          $     )                     )         $  csys_ck ref_ck mcu_ck dma_ck xhci_ck            C      h                 uokay               E      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               *       -    *>              	  mac ippc            !            *        ?                      +           e                           0                         )            )           csys_ck ref_ck mcu_ck               R                       C      i        uokay               E   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         e                           1                         )           csys_ck          uokay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3               +       -    +>              	  mac ippc            !            +        ?                      +           e                           2                         )            )   	        csys_ck ref_ck mcu_ck               S                       C      j        uokay               E   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci                                 mac         e                           3                         )   	        csys_ck          uokay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            pci                      +               /        @       	  pcie-mac            e                     	             8  !                                                            	       T              	          0        V      #      &      +      K   )         /  cpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                G                         U      	  	pcie-phy               -            6              =mac         3           	                     `  	                  V                      V                     V                     V           uokay            Sdefault idle            I   W           X   interrupt-controller             [                     3              V         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            pci                      +               /       @       	  pcie-mac            e                     	             8  !       $       $                  $       $                 	       T              	          (        W         X         Q   )         /  cpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                H                         Q         	  	pcie-phy               -           3           	                     `  	                  Y                      Y                     Y                     Y         	  udisabled            Sdefault         I   Z   interrupt-controller             [                     3              Y         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor             2                e      9                     o   )      )           cspi sf axi                       +          	  udisabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse                                              +      usb3-tx-imp@184,1                        	                  o      usb3-rx-imp@184,2                        	                 n      usb3-intr@185                        	                 m      usb3-tx-imp@186,1                        	                  l      usb3-rx-imp@186,2                        	                 k      usb3-intr@187                        	                 j      usb2-intr-p0@188,1                       	             usb2-intr-p1@188,2                       	            usb2-intr-p2@189,1                       	            usb2-intr-p3@189,2                       	            pciephy-rx-ln1@190,1                         	                  v      pciephy-tx-ln1-nmos@190,2                        	                 u      pciephy-tx-ln1-pmos@191,1                        	                  t      pciephy-rx-ln0@191,2                         	                 s      pciephy-tx-ln0-nmos@192,1                        	                  r      pciephy-tx-ln0-pmos@192,2                        	                 q      pciephy-glb-intr@193                         	                  p      dp-data@1ac                               lvts1-calib@1bc                         3      lvts2-calib@1d0              8           4      svs-calib@580                d           5      socinfo-data1@7a0                         t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !                     uokay       usb-phy@0                                        cref         	              R         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !                     uokay       usb-phy@0                                        cref         	              S         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                         mipi_tx0_pll                        	            uokay                     dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx                                         mipi_tx1_pll                        	          	  udisabled                     i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               e                                    [          ;      	  cmain dma                         +          	  udisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                          "                e                                    [         ;      	  cmain dma                         +            uokay            -         I   \        Sdefault    pmic@34           mediatek,mt6360            4                    e              IRQB             [        3           I   ]   charger           mediatek,mt6360-chg         
	 @   usb-otg-vbus-regulator          3usb-otg-vbus            B C(        Z X         regulator             mediatek,mt6360-regulator           
"   ^   buck1         	  3emi_vdd2            B         Z                                   buck2         	  3emi_vddq            B         Z                                        ^      ldo1          	  3tp1_p3v0            B 2Z        Z 2Z                                   e      ldo2            3panel1_p1v8         B w@        Z w@                                ldo3            3vmc_pmu         B O        Z 6                          O      ldo5          	  3vmch_pmu            B )2        Z 6                          N      ldo6            3mt6360_ldo1         B          Z                        ldo7            3emi_vmddr_en            B          Z                                    tcpc              mediatek,mt6360-tcpc                             PD_IRQB    connector             usb-c-connector         
2USB-C           
8dual            
B         
Tdual            
_sink            
n"d        
z"        
   altmodes       displayport         
          
  F         ports                        +       port@0                 endpoint               _           F         port@1                endpoint               `           G         port@2                endpoint               a           i                        i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               e                                    [         ;      	  cmain dma                         +          	  udisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s              0                              [      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "                e                                    b          ;      	  cmain dma                         +            uokay            -         I   c        Sdefault       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                          "                e                                    b         ;      	  cmain dma                         +            uokay            -         I   d        Sdefault    touchscreen@5d            goodix,gt9271              ]                         
                  
                  
   e        Sdefault         I   f         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c                           "               e                                    b         ;      	  cmain dma                         +            uokay            -         I   g        Sdefault    typec-mux@48              ite,it5205             H        
   h         
         
        uokay       port       endpoint               i           a               i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              0            "               e                                    b         ;      	  cmain dma                         +          	  udisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c              @            "                e                                    b         ;      	  cmain dma                         +          	  udisabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w              P                              b      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !                        -           uokay       usb-phy@0                                           cref da_ref          	              P      usb-phy@700                                           cref da_ref          a   j   k   l        mintr rx_imp tx_imp          	            
           Q         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           !                     uokay       usb-phy@0                                           cref da_ref          	              A      usb-phy@700                                           cref da_ref          a   m   n   o        mintr rx_imp tx_imp          	              B         phy@11e80000              mediatek,mt8195-pcie-phy                                 sif         a   p   q   r   s   t   u   v      G  mglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             -           	            uokay               U      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy                                            
  cunipro mp           	          	  udisabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm                        @            w          0  e                                               job mmu gpu         
   x      (     -   
   -      -      -      -           core0 core1 core2 core3 core4           uokay            "         clock-controller@13fbf000             mediatek,mt8195-mfgcfg                                            w      syscon@14000000           mediatek,mt8195-vppsys0 syscon                                           .   y                            dma-controller@14001000           mediatek,mt8195-mdp3-rdma                                .   y                  F              Z   z           -           g   {                       <     y         y         y         y         y              n         display@14002000              mediatek,mt8195-mdp3-fg                               .   y                                display@14003000              mediatek,mt8195-mdp3-stitch              0                .   y      0                        display@14004000              mediatek,mt8195-mdp3-hdr                 @                .   y      @                  "      display@14005000              mediatek,mt8195-mdp3-aal                 P                e      F               .   y      P                  
           -         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz                `                .   y      `            F    %                    display@14007000              mediatek,mt8195-mdp3-tdshp               p                .   y      p                  #      display@14008000              mediatek,mt8195-mdp3-color                               e      I               .   y                        $           -         display@14009000              mediatek,mt8195-mdp3-ovl                                 e      J               .   y                        %           -           g   {         display@1400a000              mediatek,mt8195-mdp3-padding                                 .   y                                   -         display@1400b000              mediatek,mt8195-mdp3-tcc                                 .   y                              dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot                              .   y                  F    +                      g   {              -           n         mutex@1400f000            mediatek,mt8195-vpp-mutex                                e      P               .   y                                   -         smi@14010000              mediatek,mt8195-smi-sub-common                                                         capb smi gals0           y   |           -              }      smi@14011000              mediatek,mt8195-smi-sub-common                                                        capb smi gals0           y   |           -                    smi@14012000              mediatek,mt8195-smi-common-vpp                                                                capb smi gals0 gals1            -              |      larb@14013000             mediatek,mt8195-smi-larb                0                           y   }                            capb smi            -                    iommu@14018000            mediatek,mt8195-iommu-vpp                             8     ~                                               e      R                             cbclk                          -              {      clock-controller@14e00000             mediatek,mt8195-wpesys                                                   clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0                                       clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1             0                         larb@14e04000             mediatek,mt8195-smi-larb                @                           y                               capb smi            -                    larb@14e05000             mediatek,mt8195-smi-larb                P                           y   |                                  capb smi gals               -                    syscon@14f00000           mediatek,mt8195-vppsys1 syscon                                          .   y   	                        mutex@14f01000            mediatek,mt8195-vpp-mutex                               e      {               .   y   	                    '           -         larb@14f02000             mediatek,mt8195-smi-larb                                            y                                     capb smi gals               -                    larb@14f03000             mediatek,mt8195-smi-larb                0                           y   }                                  capb smi gals               -                    display@14f06000              mediatek,mt8195-mdp3-split              `                .   y   	  `                        +      ,           -         display@14f07000              mediatek,mt8195-mdp3-tcc                p                .   y   	  p                        dma-controller@14f08000           mediatek,mt8195-mdp3-rdma                               .   y   	              F                          g                 -           n         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma                               .   y   	              F                  
        g                 -           n         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma                               .   y   	              F                          g   {              -           n         display@14f0b000              mediatek,mt8195-mdp3-fg                             .   y   	                    	      display@14f0c000              mediatek,mt8195-mdp3-fg                             .   y   	                          display@14f0d000              mediatek,mt8195-mdp3-fg                             .   y   	                          display@14f0e000              mediatek,mt8195-mdp3-hdr                                .   y   	                          display@14f0f000              mediatek,mt8195-mdp3-hdr                                .   y   	                          display@14f10000              mediatek,mt8195-mdp3-hdr                                 .   y   
                            display@14f11000              mediatek,mt8195-mdp3-aal                                e      i               .   y   
                               -         display@14f12000              mediatek,mt8195-mdp3-aal                                 e      j               .   y   
                                -         display@14f13000              mediatek,mt8195-mdp3-aal                0                e      k               .   y   
  0                  !           -         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               @                .   y   
  @            F                        display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               P                .   y   
  P            F                  $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz               `                .   y   
  `            F                  %      display@14f17000              mediatek,mt8195-mdp3-tdshp              p                .   y   
  p                        display@14f18000              mediatek,mt8195-mdp3-tdshp                              .   y   
                    (      display@14f19000              mediatek,mt8195-mdp3-tdshp                              .   y   
                    )      display@14f1a000              mediatek,mt8195-mdp3-merge                              .   y   
                               -         display@14f1b000              mediatek,mt8195-mdp3-merge                              .   y   
                               -         display@14f1c000              mediatek,mt8195-mdp3-color                              e      t               .   y   
                               -         display@14f1d000              mediatek,mt8195-mdp3-color                              .   y   
              e      u                                -         display@14f1e000              mediatek,mt8195-mdp3-color                              e      v               .   y   
                               -         display@14f1f000              mediatek,mt8195-mdp3-ovl                                e      w               .   y   
                                -           g            display@14f20000              mediatek,mt8195-mdp3-padding                                 .   y                                   -         display@14f21000              mediatek,mt8195-mdp3-padding                                .   y                                  -         display@14f22000              mediatek,mt8195-mdp3-padding                                 .   y                                   -         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             0                .   y     0            F                          g                 -           n         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             @                .   y     @            F                          g                 -           n         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot             P                .   y     P            F                          g   {              -           n         clock-controller@15000000             mediatek,mt8195-imgsys                                              &      larb@15001000             mediatek,mt8195-smi-larb                                    	        y              &       &       &   
        capb smi gals               -                    smi@15002000              mediatek,mt8195-smi-sub-common                                   &      &                 capb smi gals0           y   |           -                    smi@15003000              mediatek,mt8195-smi-sub-common               0                   &       &       &   
        capb smi gals0           y              -                    clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top                                                  larb@15120000             mediatek,mt8195-smi-larb                                    
        y              &                  capb smi            -                    clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr                                        clock-controller@15220000             mediatek,mt8195-imgsys1_wpe             "                                     larb@15230000             mediatek,mt8195-smi-larb                #                            y              &                  capb smi            -                    clock-controller@15330000             mediatek,mt8195-ipesys              3                               '      larb@15340000             mediatek,mt8195-smi-larb                4                            y              '      '           capb smi            -                    clock-controller@16000000             mediatek,mt8195-camsys                                              (      larb@16001000             mediatek,mt8195-smi-larb                                            y              (       (       (           capb smi gals               -                    larb@16002000             mediatek,mt8195-smi-larb                                             y              (      (           capb smi            -                    smi@16004000              mediatek,mt8195-smi-sub-common               @                   (       (       (           capb smi gals0           y              -                    smi@16005000              mediatek,mt8195-smi-sub-common               P                   (      (                 capb smi gals0           y   |           -                    larb@16012000             mediatek,mt8195-smi-larb                                            y                                 capb smi            -                     larb@16013000             mediatek,mt8195-smi-larb                0                           y                                 capb smi            -                     larb@16014000             mediatek,mt8195-smi-larb                @                           y                                 capb smi            -   !                 larb@16015000             mediatek,mt8195-smi-larb                P                           y                                 capb smi            -   !                 clock-controller@1604f000             mediatek,mt8195-camsys_rawa                                                 clock-controller@1606f000             mediatek,mt8195-camsys_yuva                                                 clock-controller@1608f000             mediatek,mt8195-camsys_rawb                                                 clock-controller@160af000             mediatek,mt8195-camsys_yuvb             
                                    clock-controller@16140000             mediatek,mt8195-camsys_mraw                                                  larb@16141000             mediatek,mt8195-smi-larb                                           y              (              (           capb smi gals               -   "                 larb@16142000             mediatek,mt8195-smi-larb                                            y                                 capb smi            -   "                 clock-controller@17200000             mediatek,mt8195-ccusys                                                    larb@17201000             mediatek,mt8195-smi-larb                                            y                                 capb smi            -                    video-codec@18000000              mediatek,mt8195-vcodec-dec          Z   z        g                          +                               @                !                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc                                g   {     {                 A                            csel vdec lat top                  A                         -         video-codec@10000             mediatek,mtk-vcodec-lat                               e                   0  g                                              A                            csel vdec lat top                  A                         -         video-codec@25000             mediatek,mtk-vcodec-core                 P                e                   P  g                                                                 A   !      !                 csel vdec lat top                  A                         -            larb@1800d000             mediatek,mt8195-smi-larb                                            y                                   capb smi            -                    larb@1800e000             mediatek,mt8195-smi-larb                                            y                                 capb smi            -                    clock-controller@1800f000             mediatek,mt8195-vdecsys_soc                                                   larb@1802e000             mediatek,mt8195-smi-larb                                           y              !       !            capb smi            -                    clock-controller@1802f000             mediatek,mt8195-vdecsys                                           !      larb@1803e000             mediatek,mt8195-smi-larb                                           y                    "            capb smi            -                    clock-controller@1803f000             mediatek,mt8195-vdecsys_core1                                             "      clock-controller@190f3000             mediatek,mt8195-apusys_pll              0                         clock-controller@1a000000             mediatek,mt8195-vencsys                                             #      larb@1a010000             mediatek,mt8195-smi-larb                                            y              #      #           capb smi            -                    video-codec@1a020000              mediatek,mt8195-vcodec-enc                             H  g     `     a     b     c     d     v     w     x     y        e      U               Z   z           #         	  cvenc_sel                  @                         -                        +         jpgdec-master             mediatek,mt8195-jpgdec             -         0  g     m     n     r     s     t     u                     +            !   jpgdec@1a040000           mediatek,mt8195-jpgdec-hw                              0  g     m     n     r     s     t     u        e      W                  #           cjpgdec             -         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw                              0  g     m     n     r     s     t     u        e      X                  #           cjpgdec             -         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw                              0  g   {     {     {     {     {     {          e      \                  $           cjpgdec             -            clock-controller@1b000000             mediatek,mt8195-vencsys_core1                                               $      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon                                                             .                          port                         +       endpoint@0                                                jpgenc-master             mediatek,mt8195-jpgenc             -            g   {     {     {     {                       +            !   jpgenc@1a030000           mediatek,mt8195-jpgenc-hw                                 g     g     h     i     l        e      V                  #           cjpgenc             -         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw                                 g   {     {     {     {          e      [                  $           cjpgenc             -            larb@1b010000             mediatek,mt8195-smi-larb                                            y   |           $      $                  capb smi gals               -                    ovl@1c000000              mediatek,mt8195-disp-ovl                                  e      |                  -                          g              .                ports                        +       port@0                 endpoint                                   port@1                endpoint                                         rdma@1c002000             mediatek,mt8195-disp-rdma                                 e      ~                  -                         g               .                ports                        +       port@0                 endpoint                                   port@1                endpoint                                         color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color                0                e                        -                         .        0       ports                        +       port@0                 endpoint                                   port@1                endpoint                                         ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr                @                e                        -                         .        @       ports                        +       port@0                 endpoint                                   port@1                endpoint                                         aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal                P                e                        -                         .        P       ports                        +       port@0                 endpoint                                   port@1                endpoint                                         gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma                `                e                        -                         .        `       ports                        +       port@0                 endpoint                                   port@1                endpoint                                         dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither              p                e                        -                 	        .        p       ports                        +       port@0                 endpoint                                   port@1                endpoint                                         dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              e                        -                       *           cengine digital hs                      	dphy            uokay                         +       panel@0       #    startek,kd070fhfid078 himax,hx8279                                       0            
      l                                  Sdefault         I      port       endpoint                                      ports                        +       port@0                 endpoint                                   port@1                endpoint                                         dsc@1c009000              mediatek,mt8195-disp-dsc                                 e                        -                         .                  dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi                              e                        -                       +           cengine digital hs                      	dphy          	  udisabled          merge@1c014000            mediatek,mt8195-disp-merge              @                e                        -                         .        @          dp-intf@1c015000              mediatek,mt8195-dp-intf             P                e                        -                 ,                    cpixel engine pll          	  udisabled          mutex@1c016000            mediatek,mt8195-disp-mutex              `                e                        -                         .        `            F  U      larb@1c018000             mediatek,mt8195-smi-larb                                            y                 (      (              capb smi gals               -                    larb@1c019000             mediatek,mt8195-smi-larb                                           y   |              (                     capb smi gals               -              ~      syscon@1c100000           mediatek,mt8195-vdosys1 syscon                                                .                                y              %      smi@1c01b000              mediatek,mt8195-smi-common-vdo                                     %      &      )      $        capb smi gals0 gals1            -                    iommu@1c01f000            mediatek,mt8195-iommu-vdo                             8                                                    e                                      '        cbclk               -                    mutex@1c101000            mediatek,mt8195-disp-mutex                              e                        -              %           .                    F        larb@1c102000             mediatek,mt8195-smi-larb                                            y              %       %       %           capb smi gals               -                    larb@1c103000             mediatek,mt8195-smi-larb                0                           y   |           %      %                  capb smi gals               -                    dma-controller@1c104000           mediatek,mt8195-vdo1-rdma               @                e                        %              -           g      @        .        @            n         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma               P                e                        %              -           g   {   `        .        P            n         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma               `                e                        %              -           g      A        .        `            n         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma               p                e                        %              -           g   {   a        .        p            n         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma                               e                        %              -           g      B        .                    n         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma                               e                        %              -           g   {   b        .                    n         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma                               e                        %              -           g      C        .                    n         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma                               e                        %              -           g   {   c        .                    n         vpp-merge@1c10c000            mediatek,mt8195-disp-merge                              e                        %   	   %           cmerge merge_async              -           .                             6   %         vpp-merge@1c10d000            mediatek,mt8195-disp-merge                              e                        %   
   %           cmerge merge_async              -           .                             6   %         vpp-merge@1c10e000            mediatek,mt8195-disp-merge                              e                        %      %           cmerge merge_async              -           .                             6   %         vpp-merge@1c10f000            mediatek,mt8195-disp-merge                              e                        %      %           cmerge merge_async              -           .                             6   %         vpp-merge@1c110000            mediatek,mt8195-disp-merge                               e                        %      %           cmerge merge_async              -           .                              6   %         dp-intf@1c113000              mediatek,mt8195-dp-intf             0                e                        -              %   /   %                 cpixel engine pll          	  udisabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p      @            P            p                                                              4  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  .        @            P            p                                                          h     %   %   %       %   #   %   !   %   $   %   "   %   1   %   &   %   '   %   (   %   )   %   *              cmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             -           g   {   d   {   e        e                   (  6   %   3   %   4   %   5   %   6   %   7      E  =vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx              P                 a           mdp_calibration_data            -           e                             	  udisabled          dp-tx@1c600000            mediatek,mt8195-dp-tx               `                 a           mdp_calibration_data            -           e                             	  udisabled             thermal-zones      cpu0-thermal                                 *         trips      trip-alert          : L        F          passive                  trip-crit           :         F        	  critical             cooling-maps       map0            Q         0  V   	   
                  cpu1-thermal                                 *         trips      trip-alert          : L        F          passive                  trip-crit           :         F        	  critical             cooling-maps       map0            Q         0  V   	   
                  cpu2-thermal                                 *         trips      trip-alert          : L        F          passive                  trip-crit           :         F        	  critical             cooling-maps       map0            Q         0  V   	   
                  cpu3-thermal                                 *         trips      trip-alert          : L        F          passive                  trip-crit           :         F        	  critical             cooling-maps       map0            Q         0  V   	   
                  cpu4-thermal                                 *          trips      trip-alert          : L        F          passive                  trip-crit           :         F        	  critical             cooling-maps       map0            Q         0  V                        cpu5-thermal                                 *         trips      trip-alert          : L        F          passive                  trip-crit           :         F        	  critical             cooling-maps       map0            Q         0  V                        cpu6-thermal                                 *         trips      trip-alert          : L        F          passive                  trip-crit           :         F        	  critical             cooling-maps       map0            Q         0  V                        cpu7-thermal                                 *         trips      trip-alert          : L        F          passive                  trip-crit           :         F        	  critical             cooling-maps       map0            Q         0  V                        vpu0-thermal                                 *         trips      trip-alert          : L        F          passive       trip-crit           :         F        	  critical                vpu1-thermal                                 *      	   trips      trip-alert          : L        F          passive       trip-crit           :         F        	  critical                gpu-thermal                              *      
   trips      trip-alert          : L        F          passive       trip-crit           :         F        	  critical                gpu1-thermal                                 *         trips      trip-alert          : L        F          passive       trip-crit           :         F        	  critical                vdec-thermal                                 *         trips      trip-alert          : L        F          passive       trip-crit           :         F        	  critical                img-thermal                              *         trips      trip-alert          : L        F          passive       trip-crit           :         F        	  critical                infra-thermal                                *         trips      trip-alert          : L        F          passive       trip-crit           :         F        	  critical                cam0-thermal                                 *         trips      trip-alert          : L        F          passive       trip-crit           :         F        	  critical                cam1-thermal                                 *         trips      trip-alert          : L        F          passive       trip-crit           :         F        	  critical                   chosen          eserial0:921600n8          firmware       optee             linaro,optee-tz         smc          memory@40000000          memory              @                reserved-memory                      +            !   optee@43200000           q            C                memory@50000000           shared-dma-pool             P                  q           +      memory@53000000           shared-dma-pool             S       @        memory@54600000          q            T`                memory@60000000           shared-dma-pool             `                  q      memory@62000000           shared-dma-pool             b       @           backlight-lcm0            pwm-backlight           x                @                                            backlight-lcd1            pwm-backlight                                  .            x                          @      	  udisabled          can-clk           fixed-clock                     -1-         can-clk            8      regulator-0           regulator-fixed         3edp_panel_3v3           B 2Z        Z 2Z                                   Sdefault         I         regulator-1           regulator-fixed         3edp_backlight_12v           B          Z                         `            Sdefault         I         gpio-keys         
    gpio-keys      button-volume-up                        d              j         
  
2volume_up              s         regulator-vio18-lcm0              regulator-fixed         3vio18_lcm0                         /            Sdefault         I                               regulator-vsys-lcm0           regulator-fixed       
  3vsys_lcm0                                e                 regulator-2           regulator-fixed       	  3wifi_3v3            B 2Z        Z 2Z                                             	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 ethernet0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux output-high drive-strength input-enable input-disable bias-disable bias-pull-up drive-strength-microamp bias-pull-down output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #sound-dai-cells interrupts-extended #io-channel-cells mediatek,mic-type-0 mediatek,mic-type-1 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-0 pinctrl-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select cs-gpios spi-max-frequency vdd-supply xceiver-supply interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us mediatek,tx-delay-ps mediatek,mac-wol pinctrl-1 snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup dr_mode usb-role-switch vusb33-supply remote-endpoint bus-width cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply label data-role op-sink-microwatt power-role try-power-role source-pdos sink-pdos pd-revision svid vdo irq-gpios reset-gpios AVDD28-supply vcc-supply mode-switch orientation-switch mediatek,force-mode operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs backlight enable-gpios iovcc-supply mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path no-map brightness-levels default-brightness-level num-interpolated-steps pwms enable-active-high debounce-interval linux,code vin-supply regulator-boot-on 