     8     (            %                               9    renesas,rzv2n-evk renesas,r9a09g056n48 renesas,r9a09g056                                  /   &Renesas RZ/V2N EVK Board based on r9a09g056n48     audio-clk             fixed-clock          ,             9X          I         opp-table-0           operating-points-v2          I      opp-1700000000           Q    eS          X          f       opp-850000000            Q    2         X 5          f       opp-425000000            Q    T@         X 5          f       opp-212500000            Q    ~          X 5          f           w         cpus                                cpu@0             arm,cortex-a55                        cpu                      psci                                         cpu@100           arm,cortex-a55                       cpu                      psci                                         cpu@200           arm,cortex-a55                       cpu                      psci                                         cpu@300           arm,cortex-a55                       cpu                      psci                                         cache-controller-0            cache                                              I            psci              arm,psci-1.0 arm,psci-0.2            smc       qextal-clk            fixed-clock          ,             9n6          I         rtxin-clk             fixed-clock          ,             9            I         soc           simple-bus                                                  pinctrl@10410000              renesas,r9a09g056-pinctrl                A                                     
                   &              `        2           @                     I      scif            GSCIF_TXD SCIF_RXD           L            I   	      sd1-pwr-en-hog           e        n   S             t        sd1_pwr_en        sd1          I   
   sd1-cd            L      sd1-clk         GSD1CLK          L                     sd1-dat-cmd       '  GSD1DAT0 SD1DAT1 SD1DAT2 SD1DAT3 SD1CMD                   L                           clock-controller@10420000             renesas,r9a09g056-cpg                B                                   audio_extal rtxin qextal             ,                                   I         system-controller@10430000            renesas,r9a09g056-sys                C                                     @      0      serial@11c01400       .    renesas,scif-r9a09g056 renesas,scif-r9a09g057                              l                                                                                         2  eri rxi txi bri dri tei tei-dri rxi-edge txi-edge                             fck         2           @              okay               	        default       interrupt-controller@14900000             arm,gic-v3                                                                                      	            I         mmc@15c00000          .    renesas,sdhi-r9a09g056 renesas,sdhi-r9a09g057                                                         0                                               core clkh cd aclk           @              2         	  disabled       vqmmc-regulator         5SDHI0-VQMMC         D w@        \ 2Z      	  disabled             mmc@15c10000          .    renesas,sdhi-r9a09g056 renesas,sdhi-r9a09g057                                                         0                                               core clkh cd aclk           @              2           okay               
        t   
        default state_uhs           ~                                              vqmmc-regulator         5SDHI1-VQMMC         D w@        \ 2Z      	  disabled             mmc@15c20000          .    renesas,sdhi-r9a09g056 renesas,sdhi-r9a09g057                                                         0                                               core clkh cd aclk           @              2         	  disabled       vqmmc-regulator         5SDHI2-VQMMC         D w@        \ 2Z      	  disabled                timer             arm,armv8-timer       P                                               
                     %  sec-phys phys virt hyp-phys hyp-virt          aliases         /soc/mmc@15c10000           /soc/serial@11c01400          chosen          ignore_loglevel         serial0:115200n8          memory@48000000          memory               H               regulator-3p3v            regulator-fixed         5fixed-3.3V          D 2Z        \ 2Z                           I         regulator-vqmmc-sdhi1             regulator-gpio          5SDHI1 VqmmC         n      R            D w@        \ 2Z                     2Z     w@            I            	compatible #address-cells #size-cells model #clock-cells clock-frequency phandle opp-hz opp-microvolt clock-latency-ns opp-suspend reg device_type next-level-cache enable-method clocks operating-points-v2 cache-unified cache-size cache-level interrupt-parent ranges gpio-controller #gpio-cells gpio-ranges power-domains resets pins renesas,output-impedance gpio-hog gpios output-high line-name pinmux slew-rate input-enable clock-names #reset-cells #power-domain-cells interrupts interrupt-names status pinctrl-0 pinctrl-names #interrupt-cells interrupt-controller regulator-name regulator-min-microvolt regulator-max-microvolt pinctrl-1 vmmc-supply vqmmc-supply bus-width sd-uhs-sdr50 sd-uhs-sdr104 interrupts-extended mmc1 serial0 bootargs stdout-path regulator-boot-on regulator-always-on gpios-states 