  C-   8  ?    (              >                             =    xlnx,versal-net-vnx-revA xlnx,versal-net-vnx xlnx,versal-net             Xilinx Versal NET VNX revA                                    ,             =   options    u-boot            u-boot,config            J                 cpus                                 cpu-map    cluster0       core0            Z         core1            Z         core2            Z         core3            Z            cluster1       core0            Z         core1            Z         core2            Z         core3            Z   	         cluster2       core0            Z   
      core1            Z         core2            Z         core3            Z            cluster3       core0            Z         core1            Z         core2            Z         core3            Z               cpu@0             arm,cortex-a78           ^cpu          jpsci             x             |                                 cpu@100           arm,cortex-a78           ^cpu          jpsci             x            |                                 cpu@200           arm,cortex-a78           ^cpu          jpsci             x            |                                 cpu@300           arm,cortex-a78           ^cpu          jpsci             x            |                                 cpu@10000             arm,cortex-a78           ^cpu          jpsci             x            |                                 cpu@10100             arm,cortex-a78           ^cpu          jpsci             x           |                                 cpu@10200             arm,cortex-a78           ^cpu          jpsci             x           |                                 cpu@10300             arm,cortex-a78           ^cpu          jpsci             x           |                           	      cpu@20000             arm,cortex-a78           ^cpu          jpsci             x            |                           
      cpu@20100             arm,cortex-a78           ^cpu          jpsci             x           |                                 cpu@20200             arm,cortex-a78           ^cpu          jpsci             x           |                                 cpu@20300             arm,cortex-a78           ^cpu          jpsci             x           |                                 cpu@30000             arm,cortex-a78           ^cpu          jpsci             x            |                                 cpu@30100             arm,cortex-a78           ^cpu          jpsci             x           |                                 cpu@30200             arm,cortex-a78           ^cpu          jpsci             x           |                                 cpu@30300             arm,cortex-a78           ^cpu          jpsci             x           |                                 idle-states          psci       cpu-sleep-0           arm,idle-state           @                        ,           X           '                        opp-table             operating-points-v2                opp-1066000000              ?ހ         B@        $        opp-1866000000              o8         B@        $        opp-1900000000              q?          B@        $        opp-1999000000              w&Q         B@        $        opp-2050000000              z0         B@        $        opp-2100000000              }+u          B@        $        opp-2200000000              !V          B@        $        opp-2400000000                        B@        $           aliases         5/axi/serial@f1920000            =/axi/serial@f1930000            E/dcc            M/axi/mmc@f1040000           R/axi/mmc@f1050000           W/axi/i2c@f1940000           \/axi/i2c@f1950000           a/axi/rtc@f12a0000           e/axi/usb@f1e00000           j/axi/usb@f1e10000           o/axi/spi@f1010000           t/axi/spi@f1030000         dcc           arm,dcc       	  ydisabled                   firmware       psci              arm,psci-1.0             qsmc       versal-net-firmware       .    xlnx,versal-net-firmware xlnx,versal-firmware                     qsmc          fpga-region           fpga-region                                           timer             arm,armv8-timer       0                                   
         versal-fpga           xlnx,versal-fpga                      axi           simple-bus                                                dma-controller@ebd00000           xlnx,zynqmp-dma-1.0       	  ydisabled             x                            H           clk_main clk_apb                          @                    dma-controller@ebd10000           xlnx,zynqmp-dma-1.0       	  ydisabled             x                            I           clk_main clk_apb                          @                    dma-controller@ebd20000           xlnx,zynqmp-dma-1.0       	  ydisabled             x                            J           clk_main clk_apb                          @                    dma-controller@ebd30000           xlnx,zynqmp-dma-1.0       	  ydisabled             x                            K           clk_main clk_apb                          @                    dma-controller@ebd40000           xlnx,zynqmp-dma-1.0       	  ydisabled             x                            L           clk_main clk_apb                          @                    dma-controller@ebd50000           xlnx,zynqmp-dma-1.0       	  ydisabled             x                            M           clk_main clk_apb                          @                    dma-controller@ebd60000           xlnx,zynqmp-dma-1.0       	  ydisabled             x                            N           clk_main clk_apb                          @                    dma-controller@ebd70000           xlnx,zynqmp-dma-1.0       	  ydisabled             x                            O           clk_main clk_apb                          @                    can@f1980000              xlnx,canfd-2.0        	  ydisabled             x            `                           can_clk s_axi_aclk             @                                can@f1990000              xlnx,canfd-2.0        	  ydisabled             x            `                           can_clk s_axi_aclk             @                                ethernet@f19e0000             xlnx,versal-gem cdns,gem          	  ydisabled             x                            '          '            pclk hclk tx_clk rx_clk tsu_clk                              ethernet@f19f0000             xlnx,versal-gem cdns,gem            yokay             x                            )          )            pclk hclk tx_clk rx_clk tsu_clk                                     5                   rmii       mdio                                 ethernet-phy@4           x                           interrupt-controller@e2000000             arm,gic-v3                       x                                                   	                                                    msi-controller@e2040000           arm,gic-v3-its           3        B            x                      gpio@f19d0000             xlnx,versal-gpio-1.0          	  ydisabled             x                                       M            Y                                     gpio@f1020000             xlnx,pmc-gpio-1.0         	  ydisabled             x                                       M            Y                                     i2c@f1940000              cdns,i2c-r1p14        	  ydisabled             x                                       i                                            i2c@f1950000              cdns,i2c-r1p14        	  ydisabled             x                                       i                                            i3c@f1948000              snps,dw-i3c-master-1.00a          	  ydisabled             x                                                                         i3c@f1958000              snps,dw-i3c-master-1.00a          	  ydisabled             x                                                                         spi@f1010000          #    xlnx,versal-ospi-1.0 cdns,qspi-nor        	  ydisabled              x                                                      y                                                                       E                                spi@f1030000              xlnx,versal-qspi-1.0          	  ydisabled             x                                       ref_clk pclk                        rtc@f12a0000              xlnx,zynqmp-rtc       	  ydisabled             x    *                                           
  alarm sec                    mmc@f1040000          #    xlnx,versal-8.9a arasan,sdhci-8.9a        	  ydisabled             x                                       clk_xin clk_ahb gate                       clk_out_sd0 clk_in_sd0                         mmc@f1050000              xlnx,versal-net-emmc            yokay             x                                       clk_xin clk_ahb gate                       clk_out_sd1 clk_in_sd1                                C                                             $                    5      serial@f1920000                    arm,pl011 arm,primecell       	  ydisabled             x                                       >           uartclk apb_pclk                        serial@f1930000                    arm,pl011 arm,primecell         yokay             x                                       >           uartclk apb_pclk                        iommu@ec000000            arm,smmu-v3         yokay             x                      K         	  combined                                =                  spi@f1960000              cdns,spi-r1p6         	  ydisabled                               x                     ref_clk pclk                        spi@f1970000              cdns,spi-r1p6         	  ydisabled                               x                     ref_clk pclk                        timer@f1dc0000        	    cdns,ttc          	  ydisabled          $         +          ,          -           X             x                              timer@f1dd0000        	    cdns,ttc          	  ydisabled          $         .          /          0           X             x                   timer@f1de0000        	    cdns,ttc          	  ydisabled          $         1          2          3           X             x                   timer@f1df0000        	    cdns,ttc          	  ydisabled          $         4          5          6           X             x                   usb@f1e00000              xlnx,versal-dwc3          	  ydisabled             x                     bus_clk ref_clk                                                      usb@f1b00000          
    snps,dwc3         	  ydisabled             x                     host peripheral otg wakeup        0                             !          b            d         }                    peripheral          high-speed                   ref                      usb@f1e10000              xlnx,versal-dwc3          	  ydisabled             x                     bus_clk ref_clk                                                      usb@f1c00000          
    snps,dwc3         	  ydisabled             x                     host peripheral otg wakeup        0         "          "          &          c            d         }                    host            high-speed                   ref                      watchdog@ecc10000             xlnx,versal-wwdt          	  ydisabled             x                                         watchdog@ecd10000             xlnx,versal-wwdt          	  ydisabled             x                                         watchdog@ece10000             xlnx,versal-wwdt          	  ydisabled             x                                         watchdog@ecf10000             xlnx,versal-wwdt          	  ydisabled             x                                         watchdog@ea420000             xlnx,versal-wwdt          	  ydisabled             x    B                                     watchdog@ea430000             xlnx,versal-wwdt          	  ydisabled             x    C                                        clk60             fixed-clock                     i                    clk100            fixed-clock                     i                   clk125            fixed-clock                     isY@                  clk150            fixed-clock                     iр                  clk160            fixed-clock                     i	h                   clk200            fixed-clock                     i                   clk250            fixed-clock                     i沀                  clk300            fixed-clock                     i                   clk450            fixed-clock                     it                  clk1200           fixed-clock                     iG                   memory@0             x                        ^memory        memory@800000000             x                      ^memory        memory@50000000000           x                       ^memory        chosen          console=ttyAMA1,115200n8            serial1:115200n8          reserved-memory                                      rproc@bbf14000           x    @                       rpu0vdev0vring0@bbf15000             x    P                       rpu0vdev0vring1@bbf16000             x    `                       rpu0vdev0buffer@bbf17000             x    p                       reserveothers@0          x                              pdiupdate@1c200000           x                             reserveopteeatf@22200000             x    "                              	compatible model #address-cells #size-cells interrupt-parent dma-coherent bootscr-address cpu device_type enable-method reg operating-points-v2 cpu-idle-states phandle entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us opp-hz opp-microvolt clock-latency-ns serial0 serial1 serial2 mmc0 mmc1 i2c0 i2c1 rtc usb0 usb1 spi0 spi1 status bootph-all fpga-mgr interrupts ranges clock-names #dma-cells xlnx,bus-width clocks rx-fifo-depth tx-mailbox-count iommus phy-handle phy-mode #interrupt-cells interrupt-controller msi-controller #msi-cells #gpio-cells gpio-controller clock-frequency cdns,fifo-depth cdns,fifo-width cdns,is-dma cdns,trigger-address num-cs interrupt-names calibration #clock-cells clock-output-names non-removable disable-wp no-sd no-sdio cap-mmc-hw-reset no-1-8-v reg-io-width #iommu-cells timer-width snps,dis_u2_susphy_quirk snps,dis_u3_susphy_quirk snps,quirk-frame-length-adjustment dr_mode maximum-speed snps,usb3_lpm_capable timeout-sec bootargs stdout-path no-map 